From nobody Mon Feb 9 19:05:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561748175; cv=none; d=zoho.com; s=zohoarc; b=AQnCUTNWA7PXpOhan+3YQRpyZpDNDLkPyQlX1EX+GBecxeCftGvIEKSFnBFoF2kxmTXlk/OPegNjnYY143zKlVakmfZADU3yMLSZljkNOBbYwFmZFPmAyOUbEMDkX458fM7mIPJPY1RgTliCxkB1LtC6olNO+0/DlR2oPg6sTsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561748175; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=x7CCYfkk9BOp3hR6i5ahuwrPzhBnbhQa+o1qqhYQXns=; b=RO+7BfetK9cw11DYHKRMvgdB+zU3Cjz14NQ6GFBVconO4opOJi3xiEhVsMdxW1k+px4HGBrt2YTJEDaiILg4fhMr2WF8ZzP3ebLk6tW/VgC5PV9F/hmxwaKLonKT2O8v3zV7Ov9vl0Zf/7IKbcGkRiALhuvysybyfUqv/2u0pvQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561748175538786.36795653505; Fri, 28 Jun 2019 11:56:15 -0700 (PDT) Received: from localhost ([::1]:35548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgw2e-0007tF-Ls for importer@patchew.org; Fri, 28 Jun 2019 14:56:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40200) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgvv9-00025c-HD for qemu-devel@nongnu.org; Fri, 28 Jun 2019 14:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgvv6-00018Q-Na for qemu-devel@nongnu.org; Fri, 28 Jun 2019 14:48:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46754) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgvv6-00017U-E1 for qemu-devel@nongnu.org; Fri, 28 Jun 2019 14:48:24 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B7CAD2F8BCC; Fri, 28 Jun 2019 18:48:23 +0000 (UTC) Received: from localhost (ovpn-116-7.gru2.redhat.com [10.97.116.7]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12CF5608CA; Fri, 28 Jun 2019 18:48:22 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org, Marcel Apfelbaum Date: Fri, 28 Jun 2019 15:47:18 -0300 Message-Id: <20190628184742.5961-6-ehabkost@redhat.com> In-Reply-To: <20190628184742.5961-1-ehabkost@redhat.com> References: <20190628184742.5961-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 28 Jun 2019 18:48:23 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL v2 05/29] hw/riscv: Replace global smp variables with machine smp properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , Like Xu , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Like Xu The global smp variables in riscv are replaced with smp machine properties. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like Xu Message-Id: <20190518205428.90532-6-like.xu@linux.intel.com> Reviewed-by: Alistair Francis [ehabkost: fix spike_board_init()] Signed-off-by: Eduardo Habkost --- hw/riscv/sifive_e.c | 6 ++++-- hw/riscv/sifive_plic.c | 3 +++ hw/riscv/sifive_u.c | 6 ++++-- hw/riscv/spike.c | 3 +++ hw/riscv/virt.c | 1 + 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 80ac56fa7d..bd25e11a87 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -137,6 +137,7 @@ static void riscv_sifive_e_init(MachineState *machine) =20 static void riscv_sifive_e_soc_init(Object *obj) { + MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveESoCState *s =3D RISCV_E_SOC(obj); =20 object_initialize_child(obj, "cpus", &s->cpus, @@ -144,7 +145,7 @@ static void riscv_sifive_e_soc_init(Object *obj) &error_abort, NULL); object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", &error_abort); - object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", + object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", &s->gpio, sizeof(s->gpio), @@ -153,6 +154,7 @@ static void riscv_sifive_e_soc_init(Object *obj) =20 static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) { + MachineState *ms =3D MACHINE(qdev_get_machine()); const struct MemmapEntry *memmap =3D sifive_e_memmap; Error *err =3D NULL; =20 @@ -183,7 +185,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev= , Error **errp) SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_PLIC].size); sifive_clint_create(memmap[SIFIVE_E_CLINT].base, - memmap[SIFIVE_E_CLINT].size, smp_cpus, + memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 70a4413599..0950e89e15 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -24,6 +24,7 @@ #include "qemu/error-report.h" #include "hw/sysbus.h" #include "hw/pci/msi.h" +#include "hw/boards.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "hw/riscv/sifive_plic.h" @@ -439,6 +440,8 @@ static void sifive_plic_irq_request(void *opaque, int i= rq, int level) =20 static void sifive_plic_realize(DeviceState *dev, Error **errp) { + MachineState *ms =3D MACHINE(qdev_get_machine()); + unsigned int smp_cpus =3D ms->smp.cpus; SiFivePLICState *plic =3D SIFIVE_PLIC(dev); int i; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5ecc47cea3..43bf256946 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -321,13 +321,14 @@ static void riscv_sifive_u_init(MachineState *machine) =20 static void riscv_sifive_u_soc_init(Object *obj) { + MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveUSoCState *s =3D RISCV_U_SOC(obj); =20 object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", &error_abort); - object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", + object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); =20 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), @@ -336,6 +337,7 @@ static void riscv_sifive_u_soc_init(Object *obj) =20 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { + MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveUSoCState *s =3D RISCV_U_SOC(dev); const struct MemmapEntry *memmap =3D sifive_u_memmap; MemoryRegion *system_memory =3D get_system_memory(); @@ -371,7 +373,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, - memmap[SIFIVE_U_CLINT].size, smp_cpus, + memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); =20 for (i =3D 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5b33d4be3b..d91d49dcae 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -172,6 +172,7 @@ static void spike_board_init(MachineState *machine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; + unsigned int smp_cpus =3D machine->smp.cpus; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), @@ -254,6 +255,7 @@ static void spike_v1_10_0_board_init(MachineState *mach= ine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; + unsigned int smp_cpus =3D machine->smp.cpus; =20 if (!qtest_enabled()) { info_report("The Spike v1.10.0 machine has been deprecated. " @@ -342,6 +344,7 @@ static void spike_v1_09_1_board_init(MachineState *mach= ine) MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; + unsigned int smp_cpus =3D machine->smp.cpus; =20 if (!qtest_enabled()) { info_report("The Spike v1.09.1 machine has been deprecated. " diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84d94d0c42..8e11fe5f2f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -394,6 +394,7 @@ static void riscv_virt_board_init(MachineState *machine) char *plic_hart_config; size_t plic_hart_config_len; int i; + unsigned int smp_cpus =3D machine->smp.cpus; void *fdt; =20 /* Initialize SOC */ --=20 2.18.0.rc1.1.g3f1ff2140