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[87.145.213.125]) by smtp.gmail.com with ESMTPSA id s10sm3331447wmf.8.2019.06.28.11.15.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 28 Jun 2019 11:15:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u9zhG8rg54XfiTs94v7mHs1mcSSNli/GonRCvA/Rm7M=; b=U0s2crETJzgvYEyO5VrBnNIBSxMz0jSGPVFwwJ7jBDA1V19jIUH9LJ84ROurP9fCsP 9a9L9oV1kMhQHAgrQqZJBZc/qDJTosmzii5C5G/OAW2Ii9YylvwasyVP+QySCZf3ABui LPN4TfZKc/WcUpsXVljcsVhYi0g/QTV+OBIjCjOQmhLUCczoxMHv4zRCCtAnv5lO/iLP bOX4EyX4ThXkrHGpoP+puJVFpsLHjt6Yg5DqWxDr62H8bGxMHEUq2sdKIaZz/YR4V0T2 OkJXU3qi/J/Dy+Zf8FnO98rdB2bzwCSWDy6sHbvBNW2SSmYnzAJGiMnyJcDkzTjLSCRU T3aA== X-Gm-Message-State: APjAAAWf3e7HjroeG6uUSjwhEAMO99jb2FTKcjdHAzq4gO5QKOkXzQBS aEYY+igUTI1h+4SnFP/jBpepuGsT X-Google-Smtp-Source: APXvYqwq7dp6EbJJvwNO2IyEWxgZlURhcxY/0AXywyf3NcxlcagouSSXzPp0BZvES8W3H3aGrs+/GQ== X-Received: by 2002:a05:600c:2189:: with SMTP id e9mr7670688wme.56.1561745745275; Fri, 28 Jun 2019 11:15:45 -0700 (PDT) From: Thomas Huth To: qemu-devel@nongnu.org Date: Fri, 28 Jun 2019 20:15:33 +0200 Message-Id: <20190628181536.13729-2-huth@tuxfamily.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190628181536.13729-1-huth@tuxfamily.org> References: <20190628181536.13729-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.65 Subject: [Qemu-devel] [PATCH v2 1/4] m68k: Add NeXTcube framebuffer device emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The NeXTcube uses a linear framebuffer with 4 greyscale colors and a fixed resolution of 1120 * 832. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c and altered to fit the latest interface of the current QEMU (e.g. the device has been "qdev"-ified etc.). Signed-off-by: Thomas Huth --- default-configs/m68k-softmmu.mak | 1 + hw/display/Makefile.objs | 1 + hw/display/next-fb.c | 157 +++++++++++++++++++++++++++++++ hw/m68k/Kconfig | 4 + include/hw/m68k/next-cube.h | 8 ++ 5 files changed, 171 insertions(+) create mode 100644 hw/display/next-fb.c create mode 100644 include/hw/m68k/next-cube.h diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmm= u.mak index 4049a8f2ba..d67ab8b96d 100644 --- a/default-configs/m68k-softmmu.mak +++ b/default-configs/m68k-softmmu.mak @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=3Dy # CONFIG_AN5206=3Dy CONFIG_MCF5208=3Dy +CONFIG_NEXTCUBE=3Dy diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index a64998fc7b..8d1c71026d 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -38,6 +38,7 @@ obj-$(CONFIG_RASPI) +=3D bcm2835_fb.o obj-$(CONFIG_SM501) +=3D sm501.o obj-$(CONFIG_TCX) +=3D tcx.o obj-$(CONFIG_CG3) +=3D cg3.o +obj-$(CONFIG_NEXTCUBE) +=3D next-fb.o =20 obj-$(CONFIG_VGA) +=3D vga.o =20 diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c new file mode 100644 index 0000000000..740102d7e9 --- /dev/null +++ b/hw/display/next-fb.c @@ -0,0 +1,157 @@ +/* + * NeXT Cube/Station Framebuffer Emulation + * + * Copyright (c) 2011 Bryce Lanham + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "ui/console.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/display/framebuffer.h" +#define BITS 8 +#include "ui/pixel_ops.h" +#include "hw/m68k/next-cube.h" + +#define TYPE_NEXTFB "next-fb" +#define NEXTFB(obj) OBJECT_CHECK(NeXTFbState, (obj), TYPE_NEXTFB) + +struct NeXTFbState { + SysBusDevice parent_obj; + + MemoryRegion fb_mr; + MemoryRegionSection fbsection; + QemuConsole *con; + + uint32_t pitch; + uint32_t cols; + uint32_t rows; + int invalidate; +}; +typedef struct NeXTFbState NeXTFbState; + +static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s, + int width, int pitch) +{ + NeXTFbState *nfbstate =3D NEXTFB(opaque); + static const uint32_t pal[4] =3D { + 0xFFFFFFFF, 0xFFAAAAAA, 0xFF555555, 0xFF000000 + }; + uint32_t *buf =3D (uint32_t *)d; + int i =3D 0; + + for (i =3D 0; i < nfbstate->cols / 4; i++) { + int j =3D i * 4; + uint8_t src =3D s[i]; + buf[j + 3] =3D pal[src & 0x3]; + src >>=3D 2; + buf[j + 2] =3D pal[src & 0x3]; + src >>=3D 2; + buf[j + 1] =3D pal[src & 0x3]; + src >>=3D 2; + buf[j + 0] =3D pal[src & 0x3]; + } +} + +static void nextfb_update(void *opaque) +{ + NeXTFbState *s =3D NEXTFB(opaque); + int dest_width =3D 4; + int src_width; + int first =3D 0; + int last =3D 0; + DisplaySurface *surface =3D qemu_console_surface(s->con); + + src_width =3D s->cols / 4 + 8; + dest_width =3D s->cols * 4; + + if (s->invalidate) { + framebuffer_update_memory_section(&s->fbsection, &s->fb_mr, 0, + s->cols, src_width); + s->invalidate =3D 0; + } + + framebuffer_update_display(surface, &s->fbsection, 1120, 832, + src_width, dest_width, 0, 1, nextfb_draw_li= ne, + s, &first, &last); + + dpy_gfx_update(s->con, 0, 0, 1120, 832); +} + +static void nextfb_invalidate(void *opaque) +{ + NeXTFbState *s =3D NEXTFB(opaque); + s->invalidate =3D 1; +} + +static const GraphicHwOps nextfb_ops =3D { + .invalidate =3D nextfb_invalidate, + .gfx_update =3D nextfb_update, +}; + +static void nextfb_realize(DeviceState *dev, Error **errp) +{ + NeXTFbState *s =3D NEXTFB(dev); + + memory_region_init_ram(&s->fb_mr, OBJECT(dev), "next-video", 0x1CB100, + &error_fatal); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->fb_mr); + + s->invalidate =3D 1; + s->cols =3D 1120; + s->rows =3D 832; + + s->con =3D graphic_console_init(dev, 0, &nextfb_ops, s); + qemu_console_resize(s->con, s->cols, s->rows); +} + +static void nextfb_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); + dc->realize =3D nextfb_realize; +} + +static const TypeInfo nextfb_info =3D { + .name =3D TYPE_NEXTFB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NeXTFbState), + .class_init =3D nextfb_class_init, +}; + +static void nextfb_register_types(void) +{ + type_register_static(&nextfb_info); +} + +type_init(nextfb_register_types) + +void nextfb_init(void) +{ + DeviceState *dev; + + dev =3D qdev_create(NULL, TYPE_NEXTFB); + qdev_init_nofail(dev); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xB000000); +} diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index 49ef0b3f6d..ec58a2eb06 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -7,3 +7,7 @@ config MCF5208 bool select COLDFIRE select PTIMER + +config NEXTCUBE + bool + select FRAMEBUFFER diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h new file mode 100644 index 0000000000..cf07243bda --- /dev/null +++ b/include/hw/m68k/next-cube.h @@ -0,0 +1,8 @@ + +#ifndef NEXT_CUBE_H +#define NEXT_CUBE_H + +/* next-fb.c */ +void nextfb_init(void); + +#endif /* NEXT_CUBE_H */ --=20 2.21.0 From nobody Fri May 10 11:36:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[87.145.213.125]) by smtp.gmail.com with ESMTPSA id s10sm3331447wmf.8.2019.06.28.11.15.45 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 28 Jun 2019 11:15:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ptZAvXji36H4DCrgwSc0bv82c/INssHi19QN1vQ+pkM=; b=mu9dYXONNKj5EHzIrZqGIt7kiHdTZRf8N28+XsnsPa5fMUJ5Bl70tMSrkykUzE4edA SU0HN8Df6sNHITThC0wpNqByq9Z6SgcYvt+hCsemVknzkmBnk99DaiL3QHA8qCoeVpGK RFbzsdDGFnCHQJZq4OWDF3R+VMdAU41pC7ZhI2QSEUrZUPrAQ69L1oU6zApr9mbc7T8o EhvaNl4K0XJ7NSK7OP8Cj3RogVVwZ+nJxpC/yx0SPfIeXhkNjL/yHtMfCkT8xXa+Y0Kz Dv+CQ3PQQBcD44+w04VwIRb5tvza804HnFwE4J9cU1trd24OOAy+FvAzeEyAa9klLOQx UzzQ== X-Gm-Message-State: APjAAAUalNSIsEYPm9PL1N7UuCuhWnlWmHzOTjDvh5AJyqe3IxM60a37 DhYzZIyeThopgN+zRpVkCUT6wiGQ X-Google-Smtp-Source: APXvYqxVYwkpeZUi6a+fcTR4X/RjFt1M2mlRHmH3SN4K94eXMq6UFU3SeG1HGevNkRRaZXY/tw/OvA== X-Received: by 2002:a1c:a483:: with SMTP id n125mr7922698wme.3.1561745746117; Fri, 28 Jun 2019 11:15:46 -0700 (PDT) From: Thomas Huth To: qemu-devel@nongnu.org Date: Fri, 28 Jun 2019 20:15:34 +0200 Message-Id: <20190628181536.13729-3-huth@tuxfamily.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190628181536.13729-1-huth@tuxfamily.org> References: <20190628181536.13729-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.53 Subject: [Qemu-devel] [PATCH v2 2/4] m68k: Add NeXTcube keyboard device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" It is likely still quite incomplete (e.g. mouse and interrupts are not implemented yet), but it is good enough for keyboard input at the firmware monitor. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-kbd.c and altered to fit the latest interface of the current QEMU (e.g. to use memory_region_init_io() instead of cpu_register_physical_memory()). Signed-off-by: Thomas Huth --- hw/m68k/Makefile.objs | 1 + hw/m68k/next-kbd.c | 320 ++++++++++++++++++++++++++++++++++++ include/hw/m68k/next-cube.h | 3 + 3 files changed, 324 insertions(+) create mode 100644 hw/m68k/next-kbd.c diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs index 482f8477b4..688002cac1 100644 --- a/hw/m68k/Makefile.objs +++ b/hw/m68k/Makefile.objs @@ -1,2 +1,3 @@ obj-$(CONFIG_AN5206) +=3D an5206.o mcf5206.o obj-$(CONFIG_MCF5208) +=3D mcf5208.o mcf_intc.o +obj-$(CONFIG_NEXTCUBE) +=3D next-kbd.o diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c new file mode 100644 index 0000000000..73e90f9b62 --- /dev/null +++ b/hw/m68k/next-kbd.c @@ -0,0 +1,320 @@ +/* + * QEMU NeXT Keyboard/Mouse emulation + * + * Copyright (c) 2011 Bryce Lanham + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +/* + * This is admittedly hackish, but works well enough for basic input. Mouse + * support will be added once we can boot something that needs the mouse. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/m68k/next-cube.h" +#include "ui/console.h" +#include "sysemu/sysemu.h" + +#define TYPE_NEXTKBD "next-kbd" +#define NEXTKBD(obj) OBJECT_CHECK(NextKBDState, (obj), TYPE_NEXTKBD) + +/* following defintions from next68k netbsd */ +#define CSR_INT 0x00800000 +#define CSR_DATA 0x00400000 + +#define KD_KEYMASK 0x007f +#define KD_DIRECTION 0x0080 /* pressed or released */ +#define KD_CNTL 0x0100 +#define KD_LSHIFT 0x0200 +#define KD_RSHIFT 0x0400 +#define KD_LCOMM 0x0800 +#define KD_RCOMM 0x1000 +#define KD_LALT 0x2000 +#define KD_RALT 0x4000 +#define KD_VALID 0x8000 /* only set for scancode keys ? */ +#define KD_MODS 0x4f00 + +#define KBD_QUEUE_SIZE 256 + +typedef struct { + uint8_t data[KBD_QUEUE_SIZE]; + int rptr, wptr, count; +} KBDQueue; + + +typedef struct NextKBDState { + SysBusDevice sbd; + MemoryRegion mr; + KBDQueue queue; + uint16_t shift; +} NextKBDState; + +static void queue_code(void *opaque, int code); + +/* lots of magic numbers here */ +static uint32_t kbd_read_byte(void *opaque, hwaddr addr) +{ + switch (addr & 0x3) { + case 0x0: /* 0xe000 */ + return 0x80 | 0x20; + + case 0x1: /* 0xe001 */ + return 0x80 | 0x40 | 0x20 | 0x10; + + case 0x2: /* 0xe002 */ + /* returning 0x40 caused mach to hang */ + return 0x10 | 0x2 | 0x1; + + default: + qemu_log_mask(LOG_UNIMP, "NeXT kbd read byte %"HWADDR_PRIx"\n", ad= dr); + } + + return 0; +} + +static uint32_t kbd_read_word(void *opaque, hwaddr addr) +{ + qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr); + return 0; +} + +/* even more magic numbers */ +static uint32_t kbd_read_long(void *opaque, hwaddr addr) +{ + int key =3D 0; + NextKBDState *s =3D NEXTKBD(opaque); + KBDQueue *q =3D &s->queue; + + switch (addr & 0xf) { + case 0x0: /* 0xe000 */ + return 0xA0F09300; + + case 0x8: /* 0xe008 */ + /* get keycode from buffer */ + if (q->count > 0) { + key =3D q->data[q->rptr]; + if (++q->rptr =3D=3D KBD_QUEUE_SIZE) { + q->rptr =3D 0; + } + + q->count--; + + if (s->shift) { + key |=3D s->shift; + } + + if (key & 0x80) { + return 0; + } else { + return 0x10000000 | KD_VALID | key; + } + } else { + return 0; + } + + default: + qemu_log_mask(LOG_UNIMP, "NeXT kbd read long %"HWADDR_PRIx"\n", ad= dr); + return 0; + } +} + +static void kbd_write_byte(void *opaque, hwaddr addr, uint32_t val) +{ + qemu_log_mask(LOG_UNIMP, "NeXT kbd write byte %"HWADDR_PRIx"\n", addr); +} +static void kbd_write_word(void *opaque, hwaddr addr, uint32_t val) +{ + qemu_log_mask(LOG_UNIMP, "NeXT kbd write addr %"HWADDR_PRIx"\n", addr); +} +static void kbd_write_long(void *opaque, hwaddr addr, uint32_t val) +{ + qemu_log_mask(LOG_UNIMP, "NeXT kbd write long %"HWADDR_PRIx"\n", addr); +} + +static uint64_t kbd_readfn(void *opaque, hwaddr addr, unsigned size) +{ + switch (size) { + case 1: + return kbd_read_byte(opaque, addr); + case 2: + return kbd_read_word(opaque, addr); + case 4: + return kbd_read_long(opaque, addr); + default: + g_assert_not_reached(); + } +} + +static void kbd_writefn(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + switch (size) { + case 1: + kbd_write_byte(opaque, addr, value); + break; + case 2: + kbd_write_word(opaque, addr, value); + break; + case 4: + kbd_write_long(opaque, addr, value); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps kbd_ops =3D { + .read =3D kbd_readfn, + .write =3D kbd_writefn, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void nextkbd_event(void *opaque, int ch) +{ + /* + * Will want to set vars for caps/num lock + * if (ch & 0x80) -> key release + * there's also e0 escaped scancodes that might need to be handled + */ + queue_code(opaque, ch); +} + +static const unsigned char next_keycodes[128] =3D { + 0x00, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x50, 0x4F, + 0x4E, 0x1E, 0x1F, 0x20, 0x1D, 0x1C, 0x1B, 0x00, + 0x42, 0x43, 0x44, 0x45, 0x48, 0x47, 0x46, 0x06, + 0x07, 0x08, 0x00, 0x00, 0x2A, 0x00, 0x39, 0x3A, + 0x3B, 0x3C, 0x3D, 0x40, 0x3F, 0x3E, 0x2D, 0x2C, + 0x2B, 0x26, 0x00, 0x00, 0x31, 0x32, 0x33, 0x34, + 0x35, 0x37, 0x36, 0x2e, 0x2f, 0x30, 0x00, 0x00, + 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static void queue_code(void *opaque, int code) +{ + NextKBDState *s =3D NEXTKBD(opaque); + KBDQueue *q =3D &s->queue; + int key =3D code & 0x7F; + int release =3D code & 0x80; + static int ext; + + if (code =3D=3D 0xE0) { + ext =3D 1; + } + + if (code =3D=3D 0x2A || code =3D=3D 0x1D || code =3D=3D 0x36) { + if (code =3D=3D 0x2A) { + s->shift =3D KD_LSHIFT; + } else if (code =3D=3D 0x36) { + s->shift =3D KD_RSHIFT; + ext =3D 0; + } else if (code =3D=3D 0x1D && !ext) { + s->shift =3D KD_LCOMM; + } else if (code =3D=3D 0x1D && ext) { + ext =3D 0; + s->shift =3D KD_RCOMM; + } + return; + } else if (code =3D=3D (0x2A | 0x80) || code =3D=3D (0x1D | 0x80) || + code =3D=3D (0x36 | 0x80)) { + s->shift =3D 0; + return; + } + + if (q->count >=3D KBD_QUEUE_SIZE) { + return; + } + + q->data[q->wptr] =3D next_keycodes[key] | release; + + if (++q->wptr =3D=3D KBD_QUEUE_SIZE) { + q->wptr =3D 0; + } + + q->count++; + + /* + * might need to actually trigger the NeXT irq, but as the keyboard wo= rks + * at the moment, I'll worry about it later + */ + /* s->update_irq(s->update_arg, 1); */ +} + +static void nextkbd_reset(DeviceState *dev) +{ + NextKBDState *nks =3D NEXTKBD(dev); + + memset(&nks->queue, 0, sizeof(KBDQueue)); + nks->shift =3D 0; +} + +static void nextkbd_realize(DeviceState *dev, Error **errp) +{ + NextKBDState *s =3D NEXTKBD(dev); + + memory_region_init_io(&s->mr, OBJECT(dev), &kbd_ops, s, "next.kbd", 0x= 1000); + + qemu_add_kbd_event_handler(nextkbd_event, s); +} + +static void nextkbd_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); + dc->realize =3D nextkbd_realize; + dc->reset =3D nextkbd_reset; +} + +static const TypeInfo nextkbd_info =3D { + .name =3D TYPE_NEXTKBD, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NextKBDState), + .class_init =3D nextkbd_class_init, +}; + +static void nextkbd_register_types(void) +{ + type_register_static(&nextkbd_info); +} + +type_init(nextkbd_register_types) + +void nextkbd_init(void) +{ + DeviceState *dev; + NextKBDState *nks; + + dev =3D qdev_create(NULL, TYPE_NEXTKBD); + qdev_init_nofail(dev); + + nks =3D NEXTKBD(dev); + memory_region_add_subregion(get_system_memory(), 0x200e000, &nks->mr); +} diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h index cf07243bda..88e94f6595 100644 --- a/include/hw/m68k/next-cube.h +++ b/include/hw/m68k/next-cube.h @@ -5,4 +5,7 @@ /* next-fb.c */ void nextfb_init(void); =20 +/* next-kbd.c */ +void nextkbd_init(void); + #endif /* NEXT_CUBE_H */ --=20 2.21.0 From nobody Fri May 10 11:36:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561747222; 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[87.145.213.125]) by smtp.gmail.com with ESMTPSA id s10sm3331447wmf.8.2019.06.28.11.15.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 28 Jun 2019 11:15:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ctOnUjdzBq+9hv7ad1WbaxXVvCp9AS1kNTDWQXFBG0M=; b=CRRsrnA0fr9r9EkmFBmyxcXYmX3DyKmCn03/oUgW8tMMIzyzNyiRdXQURbk3hbQeiJ csN4v9ER3MYrNu0O+ixsp61vRLkENwhIBQK0EOwZq0427Ch3icKRtXNDG3jew4oW4hr1 hi1lUvC2H2bRP5xuwo+bHrmw3eVC/s5CaMlw572ZMNimxvBMPCw8cO8IAHsfS2rjvV22 tjFSK5Y5M3R8G5xqwzxvaAVi0Xq/GCz4HAytawpdJ02eed4Bln1eCPGKNlAInN0Q9fxZ 8K8YE1yAk0dygZ5Yuwuid8AkXSNKJFszSibc6cr28lFMU3i1ENrRJRNHte3XUVOpMaSs xWPg== X-Gm-Message-State: APjAAAVp6QnzrGZNlba1FcvKlKaiagekkDByj/GB2JneafEN/2fG4aUG qU1YyvSjXP2zLbLghLBDumMDHtPr X-Google-Smtp-Source: APXvYqxQHHFh3l1wH1b2WmQxPDfO6TCvjVwrUiz/eNiSmtzsxX2kjuKTSb70VipFB6gbQFqjVRdrug== X-Received: by 2002:a5d:5692:: with SMTP id f18mr8906522wrv.104.1561745747220; Fri, 28 Jun 2019 11:15:47 -0700 (PDT) From: Thomas Huth To: qemu-devel@nongnu.org Date: Fri, 28 Jun 2019 20:15:35 +0200 Message-Id: <20190628181536.13729-4-huth@tuxfamily.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190628181536.13729-1-huth@tuxfamily.org> References: <20190628181536.13729-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.52 Subject: [Qemu-devel] [PATCH v2 3/4] m68k: Add NeXTcube machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" It is still quite incomplete (no SCSI, no floppy emulation, no network, etc.), but the firmware already shows up the debug monitor prompt in the framebuffer display, so at least the very basics are already working. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-cube.c and altered quite a bit to fit the latest interface and coding conventions of the current QEMU. Signed-off-by: Thomas Huth --- hw/m68k/Makefile.objs | 2 +- hw/m68k/next-cube.c | 988 ++++++++++++++++++++++++++++++++++++ include/hw/m68k/next-cube.h | 38 ++ 3 files changed, 1027 insertions(+), 1 deletion(-) create mode 100644 hw/m68k/next-cube.c diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs index 688002cac1..f25854730d 100644 --- a/hw/m68k/Makefile.objs +++ b/hw/m68k/Makefile.objs @@ -1,3 +1,3 @@ obj-$(CONFIG_AN5206) +=3D an5206.o mcf5206.o obj-$(CONFIG_MCF5208) +=3D mcf5208.o mcf_intc.o -obj-$(CONFIG_NEXTCUBE) +=3D next-kbd.o +obj-$(CONFIG_NEXTCUBE) +=3D next-kbd.o next-cube.o diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c new file mode 100644 index 0000000000..700d386fb9 --- /dev/null +++ b/hw/m68k/next-cube.c @@ -0,0 +1,988 @@ +/* + * NeXT Cube System Driver + * + * Copyright (c) 2011 Bryce Lanham + * + * This code is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "sysemu/qtest.h" +#include "hw/hw.h" +#include "hw/m68k/next-cube.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/scsi/esp.h" +#include "hw/sysbus.h" +#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ +#include "hw/block/fdc.h" +#include "qapi/error.h" +#include "ui/console.h" +#include "target/m68k/cpu.h" + +/* #define DEBUG_NEXT */ +#ifdef DEBUG_NEXT +#define DPRINTF(fmt, ...) \ + do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do { } while (0) +#endif + +#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") +#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE) + +#define ENTRY 0x0100001e +#define RAM_SIZE 0x4000000 +#define ROM_FILE "rom66.bin" + +typedef struct next_dma { + uint32_t csr; + + uint32_t saved_next; + uint32_t saved_limit; + uint32_t saved_start; + uint32_t saved_stop; + + uint32_t next; + uint32_t limit; + uint32_t start; + uint32_t stop; + + uint32_t next_initbuf; + uint32_t size; +} next_dma; + +typedef struct { + MachineState parent; + + uint32_t int_mask; + uint32_t int_status; + + uint8_t scsi_csr_1; + uint8_t scsi_csr_2; + next_dma dma[10]; + qemu_irq *scsi_irq; + qemu_irq scsi_dma; + qemu_irq scsi_reset; + qemu_irq *fd_irq; + + uint32_t scr1; + uint32_t scr2; + + uint8_t rtc_ram[32]; +} NeXTState; + +/* Thanks to NeXT forums for this */ +/* +static const uint8_t rtc_ram3[32] =3D { + 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, + 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 +}; +*/ +static const uint8_t rtc_ram2[32] =3D { + 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, + 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, +}; + +#define SCR2_RTCLK 0x2 +#define SCR2_RTDATA 0x4 +#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) + +static void nextscr2_write(NeXTState *s, uint32_t val, int size) +{ + static int led; + static int phase; + static uint8_t old_scr2; + static uint8_t rtc_command; + static uint8_t rtc_value; + static uint8_t rtc_status =3D 0x90; + static uint8_t rtc_return; + uint8_t scr2_2; + + if (size =3D=3D 4) { + scr2_2 =3D (val >> 8) & 0xFF; + } else { + scr2_2 =3D val & 0xFF; + } + + if (val & 0x1) { + DPRINTF("fault!\n"); + led++; + if (led =3D=3D 10) { + DPRINTF("LED flashing, possible fault!\n"); + led =3D 0; + } + } + + if (scr2_2 & 0x1) { + /* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */ + if (phase =3D=3D -1) { + phase =3D 0; + } + /* If we are in going down clock... do something */ + if (((old_scr2 & SCR2_RTCLK) !=3D (scr2_2 & SCR2_RTCLK)) && + ((scr2_2 & SCR2_RTCLK) =3D=3D 0)) { + if (phase < 8) { + rtc_command =3D (rtc_command << 1) | + ((scr2_2 & SCR2_RTDATA) ? 1 : 0); + } + if (phase >=3D 8 && phase < 16) { + rtc_value =3D (rtc_value << 1) | ((scr2_2 & SCR2_RTDATA) ?= 1 : 0); + + /* if we read RAM register, output RT_DATA bit */ + if (rtc_command <=3D 0x1F) { + scr2_2 =3D scr2_2 & (~SCR2_RTDATA); + if (s->rtc_ram[rtc_command] & (0x80 >> (phase - 8))) { + scr2_2 |=3D SCR2_RTDATA; + } + + rtc_return =3D (rtc_return << 1) | + ((scr2_2 & SCR2_RTDATA) ? 1 : 0); + } + /* read the status 0x30 */ + if (rtc_command =3D=3D 0x30) { + scr2_2 =3D scr2_2 & (~SCR2_RTDATA); + /* for now status =3D 0x98 (new rtc + FTU) */ + if (rtc_status & (0x80 >> (phase - 8))) { + scr2_2 |=3D SCR2_RTDATA; + } + + rtc_return =3D (rtc_return << 1) | + ((scr2_2 & SCR2_RTDATA) ? 1 : 0); + } + /* read the status 0x31 */ + if (rtc_command =3D=3D 0x31) { + scr2_2 =3D scr2_2 & (~SCR2_RTDATA); + /* for now 0x00 */ + if (0x00 & (0x80 >> (phase - 8))) { + scr2_2 |=3D SCR2_RTDATA; + } + rtc_return =3D (rtc_return << 1) | + ((scr2_2 & SCR2_RTDATA) ? 1 : 0); + } + + if ((rtc_command >=3D 0x20) && (rtc_command <=3D 0x2F)) { + scr2_2 =3D scr2_2 & (~SCR2_RTDATA); + /* for now 0x00 */ + time_t time_h =3D time(NULL); + struct tm *info =3D localtime(&time_h); + int ret =3D 0; + + switch (rtc_command) { + case 0x20: + ret =3D SCR2_TOBCD(info->tm_sec); + break; + case 0x21: + ret =3D SCR2_TOBCD(info->tm_min); + break; + case 0x22: + ret =3D SCR2_TOBCD(info->tm_hour); + break; + case 0x24: + ret =3D SCR2_TOBCD(info->tm_mday); + break; + case 0x25: + ret =3D SCR2_TOBCD((info->tm_mon + 1)); + break; + case 0x26: + ret =3D SCR2_TOBCD((info->tm_year - 100)); + break; + + } + + if (ret & (0x80 >> (phase - 8))) { + scr2_2 |=3D SCR2_RTDATA; + } + rtc_return =3D (rtc_return << 1) | + ((scr2_2 & SCR2_RTDATA) ? 1 : 0); + } + + } + + phase++; + if (phase =3D=3D 16) { + if (rtc_command >=3D 0x80 && rtc_command <=3D 0x9F) { + s->rtc_ram[rtc_command - 0x80] =3D rtc_value; +#ifdef READ_RTC + FILE *fp =3D fopen("rtc.ram", "wb+"); + int ret =3D fwrite(s->rtc_ram, 1, 32, fp); + if (ret !=3D 32) { + abort(); + } + fclose(fp); +#endif + } + /* write to x30 register */ + if (rtc_command =3D=3D 0xB1) { + /* clear FTU */ + if (rtc_value & 0x04) { + rtc_status =3D rtc_status & (~0x18); + s->int_status =3D s->int_status & (~0x04); + } + } + } + } + } else { + /* else end or abort */ + phase =3D -1; + rtc_command =3D 0; + rtc_value =3D 0; + } + s->scr2 =3D val & 0xFFFF00FF; + s->scr2 |=3D scr2_2 << 8; + old_scr2 =3D scr2_2; +} + + +static uint32_t mmio_readb(NeXTState *s, hwaddr addr) +{ + switch (addr) { + case 0xc000: + return (s->scr1 >> 24) & 0xFF; + case 0xc001: + return (s->scr1 >> 16) & 0xFF; + case 0xc002: + return (s->scr1 >> 8) & 0xFF; + case 0xc003: + return (s->scr1 >> 0) & 0xFF; + + case 0xd000: + return (s->scr2 >> 24) & 0xFF; + case 0xd001: + return (s->scr2 >> 16) & 0xFF; + case 0xd002: + return (s->scr2 >> 8) & 0xFF; + case 0xd003: + return (s->scr2 >> 0) & 0xFF; + case 0x14020: + DPRINTF("MMIO Read 0x4020\n"); + return 0x7f; + + default: + DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr); + return 0x0; + } +} +static uint32_t mmio_readw(NeXTState *s, hwaddr addr) +{ + switch (addr) { + default: + DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr); + return 0x0; + } +} + +static uint32_t mmio_readl(NeXTState *s, hwaddr addr) +{ + switch (addr) { + case 0x7000: + DPRINTF("Read INT status: %x\n", s->int_status); + return s->int_status; + + case 0x7800: + DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); + return s->int_mask; + + case 0xc000: + return s->scr1; + + /* + * case 0xc800: + * return 0x01000000; + */ + + case 0xd000: + return s->scr2; + + default: + DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr); + return 0x0; + } +} + +static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val) +{ + switch (addr) { + case 0xd003: + nextscr2_write(s, val, 1); + break; + default: + DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val); + } + +} +static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val) +{ + DPRINTF("MMIO Write W\n"); +} + +static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val) +{ + switch (addr) { + case 0x7000: + DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); + s->int_status =3D val; + break; + case 0x7800: + DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); + s->int_mask =3D val; + break; + case 0xc000: + DPRINTF("SCR1 Write: %x\n", val); + break; + case 0xd000: + nextscr2_write(s, val, 4); + break; + + default: + DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val); + } +} + +static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 1: + return mmio_readb(ns, addr); + case 2: + return mmio_readw(ns, addr); + case 4: + return mmio_readl(ns, addr); + default: + g_assert_not_reached(); + } +} + +static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 1: + mmio_writeb(ns, addr, value); + break; + case 2: + mmio_writew(ns, addr, value); + break; + case 4: + mmio_writel(ns, addr, value); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps mmio_ops =3D { + .read =3D mmio_readfn, + .write =3D mmio_writefn, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static uint32_t scr_readb(NeXTState *s, hwaddr addr) +{ + switch (addr) { + case 0x14108: + DPRINTF("FD read @ %x\n", (unsigned int)addr); + return 0x40 | 0x04 | 0x2 | 0x1; + case 0x14020: + DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); + return s->scsi_csr_1; + + case 0x14021: + DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); + return 0x40; + + /* + * These 4 registers are the hardware timer, not sure which register + * is the latch instead of data, but no problems so far + */ + case 0x1a000: + return 0xff & (clock() >> 24); + case 0x1a001: + return 0xff & (clock() >> 16); + case 0x1a002: + return 0xff & (clock() >> 8); + case 0x1a003: + /* Hack: We need to have this change consistently to make it work = */ + return 0xFF & clock(); + + default: + DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr); + return 0; + } +} + +static uint32_t scr_readw(NeXTState *s, hwaddr addr) +{ + DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); + return 0; +} + +static uint32_t scr_readl(NeXTState *s, hwaddr addr) +{ + DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); + return 0; +} + +#define SCSICSR_ENABLE 0x01 +#define SCSICSR_RESET 0x02 /* reset scsi dma */ +#define SCSICSR_FIFOFL 0x04 +#define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ +#define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ +#define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ + +static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) +{ + switch (addr) { + case 0x14108: + DPRINTF("FDCSR Write: %x\n", value); + + if (value =3D=3D 0x0) { + /* qemu_irq_raise(s->fd_irq[0]); */ + } + break; + case 0x14020: /* SCSI Control Register */ + if (value & SCSICSR_FIFOFL) { + DPRINTF("SCSICSR FIFO Flush\n"); + /* will have to add another irq to the esp if this is needed */ + /* esp_puflush_fifo(esp_g); */ + /* qemu_irq_pulse(s->scsi_dma); */ + } + + if (value & SCSICSR_ENABLE) { + DPRINTF("SCSICSR Enable\n"); + /* + * qemu_irq_raise(s->scsi_dma); + * s->scsi_csr_1 =3D 0xc0; + * s->scsi_csr_1 |=3D 0x1; + * qemu_irq_pulse(s->scsi_dma); + */ + } + /* + * else + * s->scsi_csr_1 &=3D ~SCSICSR_ENABLE; + */ + + if (value & SCSICSR_RESET) { + DPRINTF("SCSICSR Reset\n"); + /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ + /* qemu_irq_raise(s->scsi_reset); */ + /* s->scsi_csr_1 &=3D ~(SCSICSR_INTMASK |0x80|0x1); */ + + } + if (value & SCSICSR_DMADIR) { + DPRINTF("SCSICSR DMAdir\n"); + } + if (value & SCSICSR_CPUDMA) { + DPRINTF("SCSICSR CPUDMA\n"); + /* qemu_irq_raise(s->scsi_dma); */ + + s->int_status |=3D 0x4000000; + } else { + s->int_status &=3D ~(0x4000000); + } + if (value & SCSICSR_INTMASK) { + DPRINTF("SCSICSR INTMASK\n"); + /* + * int_mask &=3D ~0x1000; + * s->scsi_csr_1 |=3D value; + * s->scsi_csr_1 &=3D ~SCSICSR_INTMASK; + * if (s->scsi_queued) { + * s->scsi_queued =3D 0; + * next_irq(s, NEXT_SCSI_I, level); + * } + */ + } else { + /* int_mask |=3D 0x1000; */ + } + if (value & 0x80) { + /* int_mask |=3D 0x1000; */ + /* s->scsi_csr_1 |=3D 0x80; */ + } + DPRINTF("SCSICSR Write: %x\n", value); + /* s->scsi_csr_1 =3D value; */ + return; + /* Hardware timer latch - not implemented yet */ + case 0x1a000: + default: + DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value); + } +} + +static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value) +{ + DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); +} + +static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value) +{ + DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); +} + +static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 1: + return scr_readb(ns, addr); + case 2: + return scr_readw(ns, addr); + case 4: + return scr_readl(ns, addr); + default: + g_assert_not_reached(); + } +} + +static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 1: + scr_writeb(ns, addr, value); + break; + case 2: + scr_writew(ns, addr, value); + break; + case 4: + scr_writel(ns, addr, value); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps scr_ops =3D { + .read =3D scr_readfn, + .write =3D scr_writefn, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +#define NEXTDMA_SCSI(x) (0x10 + x) +#define NEXTDMA_FD(x) (0x10 + x) +#define NEXTDMA_ENTX(x) (0x110 + x) +#define NEXTDMA_ENRX(x) (0x150 + x) +#define NEXTDMA_CSR 0x0 +#define NEXTDMA_SAVED_NEXT 0x3FF0 +#define NEXTDMA_SAVED_LIMIT 0x3FF4 +#define NEXTDMA_SAVED_START 0x3FF8 +#define NEXTDMA_SAVED_STOP 0x3FFc +#define NEXTDMA_NEXT 0x4000 +#define NEXTDMA_LIMIT 0x4004 +#define NEXTDMA_START 0x4008 +#define NEXTDMA_STOP 0x400c +#define NEXTDMA_NEXT_INIT 0x4200 +#define NEXTDMA_SIZE 0x4204 + +static void dma_writel(NeXTState *next_state, hwaddr addr, uint32_t value) +{ + /* + * uint16_t reg =3D addr; + * int channel =3D 0; + * switch (reg) { + * case SCSI"all registers: + * channel =3D NEXTDMA_SCSI; + * addr =3D addr - NEXTDMA_SCSI(0); + * } + */ + + switch (addr) { + case NEXTDMA_ENRX(NEXTDMA_CSR): + if (value & DMA_DEV2M) { + next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_DEV2M; + } + + if (value & DMA_SETENABLE) { + /* DPRINTF("SCSI DMA ENABLE\n"); */ + next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_ENABLE; + /* + * if (!(next_state->dma[NEXTDMA_ENRX].csr & DMA_DEV2M)) + * DPRINTF("DMA TO DEVICE\n"); + * else + * DPRINTF("DMA TO CPU\n"); + * if (next_state->scsi_csr_1 & 1<<3) + * DPRINTF("SCSI DIR\n"); + */ + } + if (value & DMA_SETSUPDATE) { + next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_SUPDATE; + } + if (value & DMA_CLRCOMPLETE) { + next_state->dma[NEXTDMA_ENRX].csr &=3D ~DMA_COMPLETE; + } + + if (value & DMA_RESET) { + next_state->dma[NEXTDMA_ENRX].csr &=3D ~(DMA_COMPLETE | DMA_SU= PDATE | + DMA_ENABLE | DMA_DEV2M); + } + /* DPRINTF("RXCSR \tWrite: %x\n",value); */ + break; + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): + next_state->dma[NEXTDMA_ENRX].next_initbuf =3D value; + break; + case NEXTDMA_ENRX(NEXTDMA_NEXT): + next_state->dma[NEXTDMA_ENRX].next =3D value; + break; + case NEXTDMA_ENRX(NEXTDMA_LIMIT): + next_state->dma[NEXTDMA_ENRX].limit =3D value; + break; + case NEXTDMA_SCSI(NEXTDMA_CSR): + if (value & DMA_DEV2M) { + next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_DEV2M; + } + if (value & DMA_SETENABLE) { + /* DPRINTF("SCSI DMA ENABLE\n"); */ + next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_ENABLE; + /* + * if (!(next_state->dma[NEXTDMA_SCSI].csr & DMA_DEV2M)) { + * DPRINTF("DMA TO DEVICE\n"); + * } else { + * DPRINTF("DMA TO CPU\n"); + * } + * if (next_state->scsi_csr_1 & 1<<3) { + * DPRINTF("SCSI DIR\n"); + * } + */ + } + if (value & DMA_SETSUPDATE) { + next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_SUPDATE; + } + if (value & DMA_CLRCOMPLETE) { + next_state->dma[NEXTDMA_SCSI].csr &=3D ~DMA_COMPLETE; + } + + if (value & DMA_RESET) { + next_state->dma[NEXTDMA_SCSI].csr &=3D ~(DMA_COMPLETE | DMA_SU= PDATE | + DMA_ENABLE | DMA_DEV2M); + /* DPRINTF("SCSI DMA RESET\n"); */ + } + /* DPRINTF("RXCSR \tWrite: %x\n",value); */ + break; + + case NEXTDMA_SCSI(NEXTDMA_NEXT): + next_state->dma[NEXTDMA_SCSI].next =3D value; + break; + + case NEXTDMA_SCSI(NEXTDMA_LIMIT): + next_state->dma[NEXTDMA_SCSI].limit =3D value; + break; + + case NEXTDMA_SCSI(NEXTDMA_START): + next_state->dma[NEXTDMA_SCSI].start =3D value; + break; + + case NEXTDMA_SCSI(NEXTDMA_STOP): + next_state->dma[NEXTDMA_SCSI].stop =3D value; + break; + + case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): + next_state->dma[NEXTDMA_SCSI].next_initbuf =3D value; + break; + + default: + DPRINTF("DMA write @ %x w/ %x\n", (unsigned int)addr, value); + } +} + +static uint32_t dma_readl(NeXTState *next_state, hwaddr addr) +{ + switch (addr) { + case NEXTDMA_SCSI(NEXTDMA_CSR): + DPRINTF("SCSI DMA CSR READ\n"); + return next_state->dma[NEXTDMA_SCSI].csr; + case NEXTDMA_ENRX(NEXTDMA_CSR): + return next_state->dma[NEXTDMA_ENRX].csr; + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): + return next_state->dma[NEXTDMA_ENRX].next_initbuf; + case NEXTDMA_ENRX(NEXTDMA_NEXT): + return next_state->dma[NEXTDMA_ENRX].next; + case NEXTDMA_ENRX(NEXTDMA_LIMIT): + return next_state->dma[NEXTDMA_ENRX].limit; + + case NEXTDMA_SCSI(NEXTDMA_NEXT): + return next_state->dma[NEXTDMA_SCSI].next; + case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): + return next_state->dma[NEXTDMA_SCSI].next_initbuf; + case NEXTDMA_SCSI(NEXTDMA_LIMIT): + return next_state->dma[NEXTDMA_SCSI].limit; + case NEXTDMA_SCSI(NEXTDMA_START): + return next_state->dma[NEXTDMA_SCSI].start; + case NEXTDMA_SCSI(NEXTDMA_STOP): + return next_state->dma[NEXTDMA_SCSI].stop; + + default: + DPRINTF("DMA read @ %x\n", (unsigned int)addr); + return 0; + } + + /* + * once the csr's are done, subtract 0x3FEC from the addr, and that wi= ll + * normalize the upper registers + */ +} + +static uint64_t dma_readfn(void *opaque, hwaddr addr, unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 4: + return dma_readl(ns, addr); + default: + g_assert_not_reached(); + } +} + +static void dma_writefn(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + NeXTState *ns =3D NEXT_MACHINE(opaque); + + switch (size) { + case 4: + dma_writel(ns, addr, value); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps dma_ops =3D { + .read =3D dma_readfn, + .write =3D dma_writefn, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +/* + * TODO: set the shift numbers as values in the enum, so the first switch + * will not be needed + */ +void next_irq(void *opaque, int number, int level) +{ + M68kCPU *cpu =3D opaque; + int shift =3D 0; + NeXTState *ns =3D NEXT_MACHINE(qdev_get_machine()); + + /* first switch sets interupt status */ + /* DPRINTF("IRQ %i\n",number); */ + switch (number) { + /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ + case NEXT_FD_I: + shift =3D 7;; + break; + case NEXT_KBD_I: + shift =3D 3; + break; + case NEXT_PWR_I: + shift =3D 2; + break; + case NEXT_ENRX_I: + shift =3D 9; + break; + case NEXT_ENTX_I: + shift =3D 10; + break; + case NEXT_SCSI_I: + shift =3D 12; + break; + case NEXT_CLK_I: + shift =3D 5; + break; + + /* level 5 - scc (serial) */ + case NEXT_SCC_I: + shift =3D 17; + break; + + /* level 6 - audio etherrx/tx dma */ + case NEXT_ENTX_DMA_I: + shift =3D 28; + break; + case NEXT_ENRX_DMA_I: + shift =3D 27; + break; + case NEXT_SCSI_DMA_I: + shift =3D 26; + break; + case NEXT_SND_I: + shift =3D 23; + break; + case NEXT_SCC_DMA_I: + shift =3D 21; + break; + + } + /* + * this HAS to be wrong, the interrupt handlers in mach and together + * int_status and int_mask and return if there is a hit + */ + if (ns->int_mask & (1 << shift)) { + DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); + /* return; */ + } + + /* second switch triggers the correct interrupt */ + if (level) { + ns->int_status |=3D 1 << shift; + + switch (number) { + /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ + case NEXT_FD_I: + case NEXT_KBD_I: + case NEXT_PWR_I: + case NEXT_ENRX_I: + case NEXT_ENTX_I: + case NEXT_SCSI_I: + case NEXT_CLK_I: + m68k_set_irq_level(cpu, 3, 27); + break; + + /* level 5 - scc (serial) */ + case NEXT_SCC_I: + m68k_set_irq_level(cpu, 5, 29); + break; + + /* level 6 - audio etherrx/tx dma */ + case NEXT_ENTX_DMA_I: + case NEXT_ENRX_DMA_I: + case NEXT_SCSI_DMA_I: + case NEXT_SND_I: + case NEXT_SCC_DMA_I: + m68k_set_irq_level(cpu, 6, 30); + break; + } + } else { + ns->int_status &=3D ~(1 << shift); + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } +} + +static void next_cube_init(MachineState *machine) +{ + M68kCPU *cpu; + CPUM68KState *env; + MemoryRegion *ram =3D g_new(MemoryRegion, 1); + MemoryRegion *rom =3D g_new(MemoryRegion, 1); + MemoryRegion *mmiomem =3D g_new(MemoryRegion, 1); + MemoryRegion *scrmem =3D g_new(MemoryRegion, 1); + MemoryRegion *dmamem =3D g_new(MemoryRegion, 1); + MemoryRegion *unknownmem =3D g_new(MemoryRegion, 1); + MemoryRegion *sysmem =3D get_system_memory(); + NeXTState *ns =3D NEXT_MACHINE(machine); + + /* Initialize the cpu core */ + cpu =3D M68K_CPU(cpu_create(machine->cpu_type)); + if (!cpu) { + error_report("Unable to find m68k CPU definition"); + exit(1); + } + env =3D &cpu->env; + + /* Initialize CPU registers. */ + env->vbr =3D 0; + env->pc =3D 0x100001e; /* technically should read vector */ + env->sr =3D 0x2700; + + /* Set internal registers to initial values */ + /* 0x0000XX00 << vital bits */ + ns->scr1 =3D 0x00011102; + ns->scr2 =3D 0x00ff0c80; + + ns->int_mask =3D 0x0; /* 88027640; */ + ns->int_status =3D 0x0; /* 200; */ + + /* Load RTC RAM - TODO: provide possibility to load contents from file= */ + memcpy(ns->rtc_ram, rtc_ram2, 32); + + /* 64MB RAM starting at 0x4000000 */ + memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size); + memory_region_add_subregion(sysmem, 0x4000000, ram); + + /* Framebuffer */ + nextfb_init(); + + /* MMIO */ + memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio", + 0xD0000); + memory_region_add_subregion(sysmem, 0x2000000, mmiomem); + + /* BMAP - acts as a catch-all for now */ + memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr", + 0x3A7FF); + memory_region_add_subregion(sysmem, 0x2100000, scrmem); + + /* KBD */ + nextkbd_init(); + + /* Load ROM here */ + if (bios_name =3D=3D NULL) { + bios_name =3D ROM_FILE; + } + /* still not sure if the rom should also be mapped at 0x0*/ + memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal); + memory_region_add_subregion(sysmem, 0x1000000, rom); + if (load_image_targphys(bios_name, 0x1000000, 0x20000) < 0) { + if (!qtest_enabled()) { + error_report("Failed to load firmware '%s'", bios_name); + } + } + + /* TODO: */ + /* Serial */ + /* Network */ + /* SCSI */ + + /* DMA */ + memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5= 000); + memory_region_add_subregion(sysmem, 0x2000000, dmamem); + + /* FIXME: Why does the bios access this memory area? */ + memory_region_allocate_system_memory(unknownmem, NULL, "next.unknown",= 16); + memory_region_add_subregion(sysmem, 0x820c0020, unknownmem); +} + +static void next_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "NeXT Cube"; + mc->init =3D next_cube_init; + mc->default_ram_size =3D RAM_SIZE; + mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); +} + +static const TypeInfo next_typeinfo =3D { + .name =3D TYPE_NEXT_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D next_machine_class_init, + .instance_size =3D sizeof(NeXTState), +}; + +static void next_register_type(void) +{ + type_register_static(&next_typeinfo); +} + +type_init(next_register_type) diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h index 88e94f6595..d7df6a223b 100644 --- a/include/hw/m68k/next-cube.h +++ b/include/hw/m68k/next-cube.h @@ -2,6 +2,44 @@ #ifndef NEXT_CUBE_H #define NEXT_CUBE_H =20 +enum next_dma_chan { + NEXTDMA_FD, + NEXTDMA_ENRX, + NEXTDMA_ENTX, + NEXTDMA_SCSI, + NEXTDMA_SCC, + NEXTDMA_SND +}; + +#define DMA_ENABLE 0x01000000 +#define DMA_SUPDATE 0x02000000 +#define DMA_COMPLETE 0x08000000 + +#define DMA_M2DEV 0x0 +#define DMA_SETENABLE 0x00010000 +#define DMA_SETSUPDATE 0x00020000 +#define DMA_DEV2M 0x00040000 +#define DMA_CLRCOMPLETE 0x00080000 +#define DMA_RESET 0x00100000 + +enum next_irqs { + NEXT_FD_I, + NEXT_KBD_I, + NEXT_PWR_I, + NEXT_ENRX_I, + NEXT_ENTX_I, + NEXT_SCSI_I, + NEXT_CLK_I, + NEXT_SCC_I, + NEXT_ENTX_DMA_I, + NEXT_ENRX_DMA_I, + NEXT_SCSI_DMA_I, + NEXT_SCC_DMA_I, + NEXT_SND_I +}; + +void next_irq(void *opaque, int number, int level); + /* next-fb.c */ void nextfb_init(void); =20 --=20 2.21.0 From nobody Fri May 10 11:36:36 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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[87.145.213.125]) by smtp.gmail.com with ESMTPSA id s10sm3331447wmf.8.2019.06.28.11.15.47 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 28 Jun 2019 11:15:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0qTyUXfjgsv4FS3LlpdkisQ54fw5sFRwJhSEO6vox+M=; b=r6mU2k+qcIHxy+OHCbbjtq5mGKKmWXuTUA6VzGIs/bJoOQhvFZ9vI8LW/nhgg998kM S9Yh87ExEqSWOJwks/Q/RWuwQ9n2BafozaL06M3KLEsM/O4ye/jd4HkGrVa1VBGZtr3d NsyG/xYGoN7s1HHCj7nIqaP1hK7OdP48JwVTbrg6isvvNZLTkTFRELJI5s922AG2YRI/ c02fbJ8ruIbEVOF+2zo3W4Semd9C2lOh2P7sPhXMyMK4iN/gGWjq5qbncAuLz379zaB7 W0rmd2qn4xHYBT3s/9eimH0svXqxo6Xgs8Z78zl+OxZZFI0aMNenJz5Fggt9pppRT1/7 75FQ== X-Gm-Message-State: APjAAAVjmwzMBplwXAfqHQAm/IlZAouA90Lp3mIZg8in4zpzykinWas/ qFi0NwykFClLbZJnenMaSXC9jEoU X-Google-Smtp-Source: APXvYqz5m9fmJWwWhP183vfd6UN64GWe7mZAm7LEAo3kWJ9e9SmZPMBLbQRda9ChBgjrD/uhqMmAFw== X-Received: by 2002:a5d:5706:: with SMTP id a6mr8263268wrv.224.1561745748031; Fri, 28 Jun 2019 11:15:48 -0700 (PDT) From: Thomas Huth To: qemu-devel@nongnu.org Date: Fri, 28 Jun 2019 20:15:36 +0200 Message-Id: <20190628181536.13729-5-huth@tuxfamily.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190628181536.13729-1-huth@tuxfamily.org> References: <20190628181536.13729-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PATCH v2 4/4] m68k: Add an entry for the NeXTcube machine to the MAINTAINERS file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I don't have much clue about the NeXT hardware, but at least I know now the source files a little bit, so I volunteer to pick up patches and send PULL requests for them until someone else with more knowledge steps up to do this job instead. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cad58b9487..6b4fa7221f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -900,6 +900,13 @@ F: hw/char/mcf_uart.c F: hw/net/mcf_fec.c F: include/hw/m68k/mcf*.h =20 +NeXTcube +M: Thomas Huth +S: Odd Fixes +F: hw/m68k/next-*.c +F: hw/display/next-fb.c +F: include/hw/m68k/next-cube.h + MicroBlaze Machines ------------------- petalogix_s3adsp1800 --=20 2.21.0