From nobody Tue Oct 7 20:06:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561687914; cv=none; d=zoho.com; s=zohoarc; b=CxJBTb/UGRR8BWWP9obmYFrlCZM+Sb8N+6kcbgpWWCauCXGbLn7+3yfndWCjLJhaOVsL0u5ncivg4siB+XAQXuyiw8YPenhtQ+mztnLAKOwVxkoSVfrV9sCU2G/E3Uj9k2pOIgOyPU+X6EjbI2E52wsc/lqmRGp7oBE6IV18rQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561687914; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nepRu4h44ZDQ1bzaVnB5Rx9j6WEaC1aK7YPMrGkqQdA=; b=ZKRRR9VcDrrNTpmp1uvGVYVdx3Nqxbr0Sa42zM7lhKCcAMNb7rIEq5SCPyI/v7D9mJl0NUn5Stei7pg8juqUtYVlNP/Gzwwu/a/BtkqV+2GsEKrml3fSUqT5CIjE4Oh8qZuuqqjlUpGZllKd/EyOYTXgHWiLqUiqMU10zdABZUM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561687914345402.12766655568555; Thu, 27 Jun 2019 19:11:54 -0700 (PDT) Received: from localhost ([::1]:55698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hggMf-0001HM-J2 for importer@patchew.org; Thu, 27 Jun 2019 22:11:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49817) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgg7u-0000Iv-1Z for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgg7s-0007sf-5W for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36706) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgg7r-0007qo-Sz for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:32 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2B1A1307C941; Fri, 28 Jun 2019 01:56:31 +0000 (UTC) Received: from localhost (ovpn-116-7.gru2.redhat.com [10.97.116.7]) by smtp.corp.redhat.com (Postfix) with ESMTP id 96EC05D71C; Fri, 28 Jun 2019 01:56:30 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org, Marcel Apfelbaum Date: Thu, 27 Jun 2019 22:55:44 -0300 Message-Id: <20190628015606.32107-8-ehabkost@redhat.com> In-Reply-To: <20190628015606.32107-1-ehabkost@redhat.com> References: <20190628015606.32107-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Fri, 28 Jun 2019 01:56:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 07/29] hw/i386: Replace global smp variables with machine smp properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Like Xu , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Like Xu The global smp variables in i386 are replaced with smp machine properties. To avoid calling qdev_get_machine() as much as possible, some related funti= ons for acpi data generations are refactored. No semantic changes. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like Xu Message-Id: <20190518205428.90532-8-like.xu@linux.intel.com> Reviewed-by: Eduardo Habkost Signed-off-by: Eduardo Habkost --- hw/i386/acpi-build.c | 11 +++++++---- hw/i386/kvmvapic.c | 7 +++++-- hw/i386/pc.c | 24 +++++++++++++++--------- hw/i386/xen/xen-hvm.c | 4 ++++ target/i386/cpu.c | 4 +++- 5 files changed, 34 insertions(+), 16 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 8ae7d88b11..d281ffa89e 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,6 +43,7 @@ #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" #include "hw/acpi/vmgenid.h" +#include "hw/boards.h" #include "sysemu/tpm_backend.h" #include "hw/timer/mc146818rtc_regs.h" #include "hw/mem/memory-device.h" @@ -123,7 +124,8 @@ typedef struct FwCfgTPMConfig { =20 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); =20 -static void init_common_fadt_data(Object *o, AcpiFadtData *data) +static void init_common_fadt_data(MachineState *ms, Object *o, + AcpiFadtData *data) { uint32_t io =3D object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, N= ULL); AmlAddressSpace as =3D AML_AS_SYSTEM_IO; @@ -139,7 +141,8 @@ static void init_common_fadt_data(Object *o, AcpiFadtDa= ta *data) * CPUs for more than 8 CPUs, "Clustered Logical" mode has to = be * used */ - ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) = : 0), + ((ms->smp.max_cpus > 8) ? + (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), .int_model =3D 1 /* Multiple APIC */, .rtc_century =3D RTC_CENTURY, .plvl2_lat =3D 0xfff /* C2 state not supported */, @@ -173,7 +176,7 @@ static Object *object_resolve_type_unambiguous(const ch= ar *typename) return o; } =20 -static void acpi_get_pm_info(AcpiPmInfo *pm) +static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) { Object *piix =3D object_resolve_type_unambiguous(TYPE_PIIX4_PM); Object *lpc =3D object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); @@ -2612,7 +2615,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState= *machine) AcpiSlicOem slic_oem =3D { .id =3D NULL, .table_id =3D NULL }; Object *vmgenid_dev; =20 - acpi_get_pm_info(&pm); + acpi_get_pm_info(machine, &pm); acpi_get_misc_info(&misc); acpi_get_pci_holes(&pci_hole, &pci_hole64); acpi_get_slic_oem(&slic_oem); diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index ca8df462b6..9c2ab4aac5 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -18,6 +18,7 @@ #include "sysemu/kvm.h" #include "hw/i386/apic_internal.h" #include "hw/sysbus.h" +#include "hw/boards.h" #include "tcg/tcg.h" =20 #define VAPIC_IO_PORT 0x7e @@ -442,11 +443,12 @@ static void do_patch_instruction(CPUState *cs, run_on= _cpu_data data) =20 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong = ip) { + MachineState *ms =3D MACHINE(qdev_get_machine()); CPUState *cs =3D CPU(cpu); VAPICHandlers *handlers; PatchInfo *info; =20 - if (smp_cpus =3D=3D 1) { + if (ms->smp.cpus =3D=3D 1) { handlers =3D &s->rom_state.up; } else { handlers =3D &s->rom_state.mp; @@ -747,6 +749,7 @@ static void do_vapic_enable(CPUState *cs, run_on_cpu_da= ta data) static void kvmvapic_vm_state_change(void *opaque, int running, RunState state) { + MachineState *ms =3D MACHINE(qdev_get_machine()); VAPICROMState *s =3D opaque; uint8_t *zero; =20 @@ -755,7 +758,7 @@ static void kvmvapic_vm_state_change(void *opaque, int = running, } =20 if (s->state =3D=3D VAPIC_ACTIVE) { - if (smp_cpus =3D=3D 1) { + if (ms->smp.cpus =3D=3D 1) { run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s)); } else { zero =3D g_malloc0(s->rom_state.vapic_size); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index da1cdd6853..73de30cc20 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -928,12 +928,14 @@ void enable_compat_apic_id_mode(void) * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC = ID of * all CPUs up to max_cpus. */ -static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) +static uint32_t x86_cpu_apic_id_from_index(MachineState *ms, + unsigned int cpu_index) { uint32_t correct_id; static bool warned; =20 - correct_id =3D x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_ind= ex); + correct_id =3D x86_apicid_from_cpu_idx(ms->smp.cores, + ms->smp.threads, cpu_index); if (compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -1532,7 +1534,7 @@ static void pc_new_cpu(const char *typename, int64_t = apic_id, Error **errp) =20 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) { - int64_t apic_id =3D x86_cpu_apic_id_from_index(id); + int64_t apic_id =3D x86_cpu_apic_id_from_index(ms, id); Error *local_err =3D NULL; =20 if (id < 0) { @@ -1568,9 +1570,10 @@ void pc_cpus_init(PCMachineState *pcms) * * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). */ - pcms->apic_id_limit =3D x86_cpu_apic_id_from_index(max_cpus - 1) + 1; + pcms->apic_id_limit =3D x86_cpu_apic_id_from_index(ms, + ms->smp.max_cpus - 1)= + 1; possible_cpus =3D mc->possible_cpu_arch_ids(ms); - for (i =3D 0; i < smp_cpus; i++) { + for (i =3D 0; i < ms->smp.cpus; i++) { pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arc= h_id, &error_fatal); } @@ -2294,6 +2297,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, X86CPU *cpu =3D X86_CPU(dev); MachineState *ms =3D MACHINE(hotplug_dev); PCMachineState *pcms =3D PC_MACHINE(hotplug_dev); + unsigned int smp_cores =3D ms->smp.cores; + unsigned int smp_threads =3D ms->smp.threads; =20 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", @@ -2303,7 +2308,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, =20 /* if APIC ID is not set, set it based on socket/core/thread propertie= s */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (max_cpus - 1) / smp_threads / smp_cores; + int max_socket =3D (ms->smp.max_cpus - 1) / smp_threads / smp_core= s; =20 if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); @@ -2653,13 +2658,14 @@ static int64_t pc_get_default_cpu_node_id(const Mac= hineState *ms, int idx) =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - smp_cores, smp_threads, &topo); + ms->smp.cores, ms->smp.threads, &topo); return topo.pkg_id % nb_numa_nodes; } =20 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) { int i; + unsigned int max_cpus =3D ms->smp.max_cpus; =20 if (ms->possible_cpus) { /* @@ -2678,9 +2684,9 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) =20 ms->possible_cpus->cpus[i].type =3D ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count =3D 1; - ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= i); + ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= ms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - smp_cores, smp_threads, &topo); + ms->smp.cores, ms->smp.threads, &topo); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; ms->possible_cpus->cpus[i].props.has_core_id =3D true; diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 2939122e7c..941bd25e66 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -750,6 +750,8 @@ static ioreq_t *cpu_get_ioreq_from_shared_memory(XenIOS= tate *state, int vcpu) /* retval--the number of ioreq packet */ static ioreq_t *cpu_get_ioreq(XenIOState *state) { + MachineState *ms =3D MACHINE(qdev_get_machine()); + unsigned int max_cpus =3D ms->smp.max_cpus; int i; evtchn_port_t port; =20 @@ -1377,6 +1379,8 @@ static int xen_map_ioreq_server(XenIOState *state) =20 void xen_hvm_init(PCMachineState *pcms, MemoryRegion **ram_memory) { + MachineState *ms =3D MACHINE(pcms); + unsigned int max_cpus =3D ms->smp.max_cpus; int i, rc; xen_pfn_t ioreq_pfn; XenIOState *state; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index da6eb67cfb..78830d403a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -56,6 +56,7 @@ #include "hw/hw.h" #include "hw/xen/xen.h" #include "hw/i386/apic_internal.h" +#include "hw/boards.h" #endif =20 #include "disas/capstone.h" @@ -5384,9 +5385,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY + MachineState *ms =3D MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); =20 - if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) { + if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { x86_cpu_apic_create(cpu, &local_err); if (local_err !=3D NULL) { goto out; --=20 2.18.0.rc1.1.g3f1ff2140