From nobody Tue Oct 7 20:15:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561688673; cv=none; d=zoho.com; s=zohoarc; b=gNgofxKgMZU6YG8ZL357UBQ6kuj/CdUhH9RW6l2t+gebwvtG8mq5DewlhoH/xsiVOHX9xVXNvOzUSIuNdzkxXI+9YUxBWbp3fmqBpoWyEgv1sDk/H7WgMNgoeQw/S1ZlJDh3agNNjEsopJh/CunZD6dbwIhvB8BntcARn4KefmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561688673; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=CrlutvsJvPCHpD7OCwr1kgTDnunhWS4PL+TJUito/D8=; b=b+GIKiSUb78mmAvPdHxh4YTZanooHZjb4jUOg8FtzFEWchRDSObnomWzvA0JEUH4u/rPDSCpmILQbgK/ninpyc+eYl4ysRW35kg33PYiIOLsK8s/m3hAllAUnEH6wG+aQ7DsxIiBx3XX57vHKIgIcKHqKFY0Uo/hzC1Kys3LDGM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561688673873542.6427480347503; Thu, 27 Jun 2019 19:24:33 -0700 (PDT) Received: from localhost ([::1]:55778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hggYs-0005Fg-BL for importer@patchew.org; Thu, 27 Jun 2019 22:24:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50146) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgg8n-0000wP-Kf for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:57:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgg8l-0001hd-O2 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:57:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50686) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgg8l-0001T7-DV for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:57:27 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 828AA85540; Fri, 28 Jun 2019 01:57:21 +0000 (UTC) Received: from localhost (ovpn-116-7.gru2.redhat.com [10.97.116.7]) by smtp.corp.redhat.com (Postfix) with ESMTP id E8E4D5D9D2; Fri, 28 Jun 2019 01:57:20 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org, Marcel Apfelbaum Date: Thu, 27 Jun 2019 22:56:04 -0300 Message-Id: <20190628015606.32107-28-ehabkost@redhat.com> In-Reply-To: <20190628015606.32107-1-ehabkost@redhat.com> References: <20190628015606.32107-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 28 Jun 2019 01:57:21 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 27/29] target/i386: Add CPUID.1F generation support for multi-dies PCMachine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Like Xu , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Like Xu The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be exposed if guests want to emulate multiple software-visible die within each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they can be generated by almost same code as 0xb except die_offset setting. If the number of dies per package is greater than 1, the cpuid_min_level would be adjusted to 0x1f regardless of whether the host supports CPUID.1F. Likewise, the CPUID.1F wouldn't be exposed if env->nr_dies < 2. Suggested-by: Eduardo Habkost Signed-off-by: Like Xu Message-Id: <20190620054525.37188-2-like.xu@linux.intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + target/i386/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++ target/i386/kvm.c | 12 ++++++++++++ 3 files changed, 54 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 85319f4ae1..0a96c78669 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -736,6 +736,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) +#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 35ecb4113c..ea52db0600 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4413,6 +4413,42 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; } =20 + assert(!(*eax & ~0x1f)); + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + break; + case 0x1F: + /* V2 Extended Topology Enumeration Leaf */ + if (env->nr_dies < 2) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + switch (count) { + case 0: + *eax =3D apicid_core_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_die_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + case 2: + *eax =3D apicid_pkg_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; @@ -5094,6 +5130,11 @@ static void x86_cpu_expand_features(X86CPU *cpu, Err= or **errp) x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); } =20 + /* CPU topology with multi-dies support requires CPUID[0x1F] */ + if (env->nr_dies > 1) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); + } + /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); diff --git a/target/i386/kvm.c b/target/i386/kvm.c index e4b4f5756a..473a17e9a5 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1451,6 +1451,10 @@ int kvm_arch_init_vcpu(CPUState *cs) } break; } + case 0x1f: + if (env->nr_dies < 2) { + break; + } case 4: case 0xb: case 0xd: @@ -1458,6 +1462,11 @@ int kvm_arch_init_vcpu(CPUState *cs) if (i =3D=3D 0xd && j =3D=3D 64) { break; } + + if (i =3D=3D 0x1f && j =3D=3D 64) { + break; + } + c->function =3D i; c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; c->index =3D j; @@ -1469,6 +1478,9 @@ int kvm_arch_init_vcpu(CPUState *cs) if (i =3D=3D 0xb && !(c->ecx & 0xff00)) { break; } + if (i =3D=3D 0x1f && !(c->ecx & 0xff00)) { + break; + } if (i =3D=3D 0xd && c->eax =3D=3D 0) { continue; } --=20 2.18.0.rc1.1.g3f1ff2140