From nobody Tue Oct 7 20:21:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561687914; cv=none; d=zoho.com; s=zohoarc; b=EDbB62aUbtHx+assLSnjnHCoa7TMs/9p1kibRg/A/NvDTMk8Kl/i5COPf+tAj3u1th/AiXk9tA4EolYzo9zQRcky0ukjBf17EvnzEpBGT3uR0ucnkgfua+icmIH0l9pWhA5YYZoWqZzP9q6N65wONnSM/0L6tneoDbiYzw9yUBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561687914; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kM1++zGcHHsANfP06AK1HUBQewDkZuQhDXqx4qRFgfE=; b=CDtJM3tTfW2SRvqMl3aqJiyIHoQ5vcgo9tx82nbL1AswusiBtZVGRoi5KNZ/+By8mwmU/2jH+tcV/vQ48Ktz42UD2/V2vvBLTeaDEcna/D3xonmHKCurmZ+b6k3jgRmunBkxZLvIlD8nUIiFMr3z/ttXoNhizoXvRqtjfG9ur2k= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561687914396190.5842762909624; Thu, 27 Jun 2019 19:11:54 -0700 (PDT) Received: from localhost ([::1]:55694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hggMd-0001CM-Hi for importer@patchew.org; Thu, 27 Jun 2019 22:11:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49956) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgg8A-0000gE-Qq for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgg88-00006e-IQ for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52334) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgg88-0008Vs-68 for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:48 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 713AA307CDD5; Fri, 28 Jun 2019 01:56:47 +0000 (UTC) Received: from localhost (ovpn-116-7.gru2.redhat.com [10.97.116.7]) by smtp.corp.redhat.com (Postfix) with ESMTP id BD7C11972E; Fri, 28 Jun 2019 01:56:46 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org, Marcel Apfelbaum Date: Thu, 27 Jun 2019 22:55:51 -0300 Message-Id: <20190628015606.32107-15-ehabkost@redhat.com> In-Reply-To: <20190628015606.32107-1-ehabkost@redhat.com> References: <20190628015606.32107-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Fri, 28 Jun 2019 01:56:47 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 14/29] i386: Update new x86_apicid parsing rules with die_offset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Like Xu , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Like Xu In new sockets/dies/cores/threads model, the apicid of logical cpu could imply die level info of guest cpu topology thus x86_apicid_from_cpu_idx() need to be refactored with #dies value, so does apicid_*_offset(). To keep semantic compatibility, the legacy pkg_offset which helps to generate CPUIDs such as 0x3 for L3 cache should be mapping to die_offset. Signed-off-by: Like Xu Message-Id: <20190612084104.34984-5-like.xu@linux.intel.com> [ehabkost: squash unit test patch] Message-Id: <20190612084104.34984-6-like.xu@linux.intel.com> Reviewed-by: Eduardo Habkost Signed-off-by: Eduardo Habkost --- include/hw/i386/topology.h | 76 ++++++++++++++++++++++++---------- hw/i386/pc.c | 29 ++++++++----- target/i386/cpu.c | 13 +++--- tests/test-x86-cpuid.c | 84 ++++++++++++++++++++------------------ 4 files changed, 126 insertions(+), 76 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index c9fb41588e..4ff5b2da6c 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -63,88 +63,120 @@ static unsigned apicid_bitwidth_for_count(unsigned cou= nt) =20 /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_cores, unsigned nr_thr= eads) +static inline unsigned apicid_smt_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_threads); } =20 /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_core_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_cores); } =20 +/* Bit width of the Die_ID field */ +static inline unsigned apicid_die_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_bitwidth_for_count(nr_dies); +} + /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_cores, +static inline unsigned apicid_core_offset(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads) { - return apicid_smt_width(nr_cores, nr_threads); + return apicid_smt_width(nr_dies, nr_cores, nr_threads); +} + +/* Bit offset of the Die_ID field */ +static inline unsigned apicid_die_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_core_offset(nr_dies, nr_cores, nr_threads) + + apicid_core_width(nr_dies, nr_cores, nr_threads); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_pkg_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { - return apicid_core_offset(nr_cores, nr_threads) + - apicid_core_width(nr_cores, nr_threads); + return apicid_die_offset(nr_dies, nr_cores, nr_threads) + + apicid_die_width(nr_dies, nr_cores, nr_threads); } =20 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores, +static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, const X86CPUTopoInfo *topo) { - return (topo->pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) | - (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) | + return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threa= ds)) | topo->smt_id; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_cores, +static inline void x86_topo_ids_from_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, X86CPUTopoInfo *topo) { - unsigned core_index =3D cpu_index / nr_threads; + topo->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo->core_id =3D cpu_index / nr_threads % nr_cores; topo->smt_id =3D cpu_index % nr_threads; - topo->core_id =3D core_index % nr_cores; - topo->pkg_id =3D core_index / nr_cores; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, + unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, X86CPUTopoInfo *topo) { topo->smt_id =3D apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_cores, nr_threads= )); - topo->core_id =3D (apicid >> apicid_core_offset(nr_cores, nr_threads))= & - ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_thread= s)); - topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_cores, nr_threads); - topo->die_id =3D 0; + ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); + topo->core_id =3D + (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_thre= ads)); + topo->die_id =3D + (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threa= ds)); + topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_thr= eads); } =20 /* Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores, +static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index) { X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_cores, nr_threads, &topo); + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); } =20 #endif /* HW_I386_TOPOLOGY_H */ diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 98a314dcf0..9921ce4f5e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -931,10 +931,11 @@ void enable_compat_apic_id_mode(void) static uint32_t x86_cpu_apic_id_from_index(MachineState *ms, unsigned int cpu_index) { + PCMachineState *pcms =3D PC_MACHINE(ms); uint32_t correct_id; static bool warned; =20 - correct_id =3D x86_apicid_from_cpu_idx(ms->smp.cores, + correct_id =3D x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, ms->smp.threads, cpu_index); if (compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { @@ -2353,18 +2354,21 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, topo.die_id =3D cpu->die_id; topo.core_id =3D cpu->core_id; topo.smt_id =3D cpu->thread_id; - cpu->apic_id =3D apicid_from_topo_ids(smp_cores, smp_threads, &top= o); + cpu->apic_id =3D apicid_from_topo_ids(pcms->smp_dies, smp_cores, + smp_threads, &topo); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &to= po); - error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] w= ith" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, - ms->possible_cpus->len - 1); + x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, + smp_cores, smp_threads, &topo); + error_setg(errp, + "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" + " APIC ID %" PRIu32 ", valid index range 0:%d", + topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + cpu->apic_id, ms->possible_cpus->len - 1); return; } =20 @@ -2380,7 +2384,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); + x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, + smp_cores, smp_threads, &topo); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pk= g_id); @@ -2678,10 +2683,12 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cp= u_index) static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { X86CPUTopoInfo topo; + PCMachineState *pcms =3D PC_MACHINE(ms); =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - ms->smp.cores, ms->smp.threads, &topo); + pcms->smp_dies, ms->smp.cores, + ms->smp.threads, &topo); return topo.pkg_id % nb_numa_nodes; } =20 @@ -2689,6 +2696,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) { int i; unsigned int max_cpus =3D ms->smp.max_cpus; + PCMachineState *pcms =3D PC_MACHINE(ms); =20 if (ms->possible_cpus) { /* @@ -2709,7 +2717,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) ms->possible_cpus->cpus[i].vcpus_count =3D 1; ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= ms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - ms->smp.cores, ms->smp.threads, &topo); + pcms->smp_dies, ms->smp.cores, + ms->smp.threads, &topo); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id =3D true; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bd0f873883..3a38fe3633 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4267,7 +4267,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t pkg_offset; + uint32_t die_offset; uint32_t limit; uint32_t signature[3]; =20 @@ -4356,10 +4356,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - pkg_offset =3D apicid_pkg_offset(cs->nr_cores, cs->nr_thre= ads); + die_offset =3D apicid_die_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << pkg_offset), cs->nr_cores, + (1 << die_offset), cs->nr_cores, eax, ebx, ecx, edx); break; } @@ -4441,12 +4442,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: - *eax =3D apicid_core_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_core_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_pkg_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c index ff225006e4..1942287f33 100644 --- a/tests/test-x86-cpuid.c +++ b/tests/test-x86-cpuid.c @@ -28,74 +28,80 @@ =20 static void test_topo_bits(void) { - /* simple tests for 1 thread per core, 1 core per socket */ - g_assert_cmpuint(apicid_smt_width(1, 1), =3D=3D, 0); - g_assert_cmpuint(apicid_core_width(1, 1), =3D=3D, 0); + /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ + g_assert_cmpuint(apicid_smt_width(1, 1, 1), =3D=3D, 0); + g_assert_cmpuint(apicid_core_width(1, 1, 1), =3D=3D, 0); + g_assert_cmpuint(apicid_die_width(1, 1, 1), =3D=3D, 0); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 2), =3D=3D, 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 3), =3D=3D, 3); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), =3D=3D, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), =3D=3D, 3); =20 =20 /* Test field width calculation for multiple values */ - g_assert_cmpuint(apicid_smt_width(1, 2), =3D=3D, 1); - g_assert_cmpuint(apicid_smt_width(1, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_smt_width(1, 4), =3D=3D, 2); + g_assert_cmpuint(apicid_smt_width(1, 1, 2), =3D=3D, 1); + g_assert_cmpuint(apicid_smt_width(1, 1, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_smt_width(1, 1, 4), =3D=3D, 2); =20 - g_assert_cmpuint(apicid_smt_width(1, 14), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 15), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 16), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 17), =3D=3D, 5); + g_assert_cmpuint(apicid_smt_width(1, 1, 14), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 15), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 16), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 17), =3D=3D, 5); =20 =20 - g_assert_cmpuint(apicid_core_width(30, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(31, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(32, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(33, 2), =3D=3D, 6); + g_assert_cmpuint(apicid_core_width(1, 30, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 31, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 32, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 33, 2), =3D=3D, 6); =20 + g_assert_cmpuint(apicid_die_width(1, 30, 2), =3D=3D, 0); + g_assert_cmpuint(apicid_die_width(2, 30, 2), =3D=3D, 1); + g_assert_cmpuint(apicid_die_width(3, 30, 2), =3D=3D, 2); + g_assert_cmpuint(apicid_die_width(4, 30, 2), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly */ =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - g_assert_cmpuint(apicid_smt_width(6, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_core_width(6, 3), =3D=3D, 3); - g_assert_cmpuint(apicid_pkg_offset(6, 3), =3D=3D, 5); + g_assert_cmpuint(apicid_smt_width(1, 6, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_core_offset(1, 6, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_die_offset(1, 6, 3), =3D=3D, 5); + g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), =3D=3D, 5); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2), =3D=3D, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), =3D=3D, 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), =3D=3D, (1 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), =3D=3D, (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), =3D=3D, (1 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), =3D=3D, (2 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), =3D=3D, (2 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), =3D=3D, (2 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), =3D=3D, (5 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), =3D=3D, (5 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), =3D=3D, (5 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 0 * 3 + 0),= =3D=3D, - (1 << 5)); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 1 * 3 + 1),= =3D=3D, - (1 << 5) | (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 3 * 6 * 3 + 5 * 3 + 2),= =3D=3D, - (3 << 5) | (5 << 2) | 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 1 * 6 * 3 + 0 * 3 + 0), =3D=3D, (1 << 5)); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 1 * 6 * 3 + 1 * 3 + 1), =3D=3D, (1 << 5) | (1 << 2) |= 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 3 * 6 * 3 + 5 * 3 + 2), =3D=3D, (3 << 5) | (5 << 2) |= 2); } =20 int main(int argc, char **argv) --=20 2.18.0.rc1.1.g3f1ff2140