From nobody Tue Oct 7 20:06:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561687382; cv=none; d=zoho.com; s=zohoarc; b=DhQqa8g3wEY1YfWO9F7fK8bv+7DQvtq2AyNJxKMt1Np6UI3Ty3bQnCA9KWsD6r05sFunlEgNunWn29SbJF278X60LXLVEhS6fINQwXvVIuSqHest9tz9iGnimAm8RHoPcUoDPnmugKS7aLKBM5+Jm5zcS/13Dseayq9DCacCelg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561687382; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8pmT9EzPSOaSBI97+9vDFbZGI5zx1aiZhUi1BA9ECv0=; b=CtkPptI8/rBUdMo9LEN1qpq0RevHXjA77vxWh695GyrsYjiixqebZ25Ws5tzQjf7W6txAkJQ+X1vE0YZwW1OdA7aVbo1j4QGEMNoqZhBQ5WGUBIYNYtyicwiDyeOOPZVsTL/WFiQwaAAiYFp3OYINBHF2ZrsFD3e3hHdPqQNOfE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561687382936699.2149097413776; Thu, 27 Jun 2019 19:03:02 -0700 (PDT) Received: from localhost ([::1]:55620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hggDm-00065N-GE for importer@patchew.org; Thu, 27 Jun 2019 22:02:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49851) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgg7y-0000S6-To for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgg7x-00085v-7E for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49526) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgg7w-00083u-Sr for qemu-devel@nongnu.org; Thu, 27 Jun 2019 21:56:37 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 254F1308212A; Fri, 28 Jun 2019 01:56:36 +0000 (UTC) Received: from localhost (ovpn-116-7.gru2.redhat.com [10.97.116.7]) by smtp.corp.redhat.com (Postfix) with ESMTP id 965E860BE0; Fri, 28 Jun 2019 01:56:35 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org, Marcel Apfelbaum Date: Thu, 27 Jun 2019 22:55:46 -0300 Message-Id: <20190628015606.32107-10-ehabkost@redhat.com> In-Reply-To: <20190628015606.32107-1-ehabkost@redhat.com> References: <20190628015606.32107-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.42]); Fri, 28 Jun 2019 01:56:36 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 09/29] hw: Replace global smp variables with MachineState for all remaining archs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Like Xu , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Like Xu The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes are replaced with smp properties from MachineState. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like Xu Reviewed-by: Alistair Francis Message-Id: <20190518205428.90532-10-like.xu@linux.intel.com> Signed-off-by: Eduardo Habkost --- hw/alpha/dp264.c | 1 + hw/hppa/machine.c | 2 ++ hw/mips/boston.c | 2 +- hw/mips/mips_malta.c | 2 ++ hw/openrisc/openrisc_sim.c | 1 + hw/sparc/sun4m.c | 2 ++ hw/sparc64/sun4u.c | 4 ++-- hw/xtensa/sim.c | 2 +- hw/xtensa/xtfpga.c | 1 + 9 files changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 0347eb897c..9dfb835013 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -63,6 +63,7 @@ static void clipper_init(MachineState *machine) char *palcode_filename; uint64_t palcode_entry, palcode_low, palcode_high; uint64_t kernel_entry, kernel_low, kernel_high; + unsigned int smp_cpus =3D machine->smp.cpus; =20 /* Create up to 4 cpus. */ memset(cpus, 0, sizeof(cpus)); diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 416e67bab1..662838d83b 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -72,6 +72,7 @@ static void machine_hppa_init(MachineState *machine) MemoryRegion *ram_region; MemoryRegion *cpu_region; long i; + unsigned int smp_cpus =3D machine->smp.cpus; =20 ram_size =3D machine->ram_size; =20 @@ -242,6 +243,7 @@ static void machine_hppa_init(MachineState *machine) =20 static void hppa_machine_reset(MachineState *ms) { + unsigned int smp_cpus =3D ms->smp.cpus; int i; =20 qemu_devices_reset(); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 749582e5aa..9eeccbea9a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -458,7 +458,7 @@ static void boston_mach_init(MachineState *machine) sizeof(s->cps), TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", &err); - object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); + object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", = &err); object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); =20 if (err !=3D NULL) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 132127882d..20e019bf66 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1095,6 +1095,8 @@ static int64_t load_kernel (void) =20 static void malta_mips_config(MIPSCPU *cpu) { + MachineState *ms =3D MACHINE(qdev_get_machine()); + unsigned int smp_cpus =3D ms->smp.cpus; CPUMIPSState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 87b9feaa96..b85f0df323 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -130,6 +130,7 @@ static void openrisc_sim_init(MachineState *machine) qemu_irq *cpu_irqs[2]; qemu_irq serial_irq; int n; + unsigned int smp_cpus =3D machine->smp.cpus; =20 for (n =3D 0; n < smp_cpus; n++) { cpu =3D OPENRISC_CPU(cpu_create(machine->cpu_type)); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 7e4f61fc3e..a8004a5fe3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -871,6 +871,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwd= ef, FWCfgState *fw_cfg; DeviceState *dev; SysBusDevice *s; + unsigned int smp_cpus =3D machine->smp.cpus; + unsigned int max_cpus =3D machine->smp.max_cpus; =20 /* init CPUs */ for(i =3D 0; i < smp_cpus; i++) { diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 4230b17b87..5d87be811d 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -697,8 +697,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem, &FW_CFG_IO(dev)->comb_iomem); =20 fw_cfg =3D FW_CFG(dev); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpu= s); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index b6922c39d5..09165b6f4d 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -59,7 +59,7 @@ static void xtensa_sim_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; int n; =20 - for (n =3D 0; n < smp_cpus; n++) { + for (n =3D 0; n < machine->smp.cpus; n++) { cpu =3D XTENSA_CPU(cpu_create(machine->cpu_type)); env =3D &cpu->env; =20 diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index e05ef75a75..f7f3e11e93 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -238,6 +238,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, M= achineState *machine) const unsigned system_io_size =3D 224 * MiB; uint32_t freq =3D 10000000; int n; + unsigned int smp_cpus =3D machine->smp.cpus; =20 if (smp_cpus > 1) { mx_pic =3D xtensa_mx_pic_init(31); --=20 2.18.0.rc1.1.g3f1ff2140