From nobody Mon Feb 9 10:12:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561670335; cv=none; d=zoho.com; s=zohoarc; b=dh+WTiEZxfgR/cJahUX9V405FJy0M0ogH8twO5g27l7qhyoUwGGbpnVwA7blmQW5/Q3XS/5Se79mLbBbwOWFdi7iVLFwAg5AAMUUf8DDiSSNVyoRbZqaJDpg4ugOxQmUWfGdi+HGQIiIipDM3Rm0LKodu7FEZvRAuAHgNmtd7YY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561670335; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=CFx0AAXnlVFEA1QgKUukpBbJKJW2g1mYQFOkRkMEzHI=; b=NYLKmMJvwY9dSwjOoKwh2e6GWuXj9Z0AH9pUf84FRco/viePNf0w16m54gPVKgoFGd5xICFRzYbPsKS2RyAC9oZ5EblIcISE+GZbxJBwHoEOosFRYCGgGyqHvxOrfzEM4WBG8qcxqFSIfyz/Eg/BUoL8ZRlNq+rQ09WQe7hdeP8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561670335004786.7786719532472; Thu, 27 Jun 2019 14:18:55 -0700 (PDT) Received: from localhost ([::1]:54462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgbX4-0000Fc-VY for importer@patchew.org; Thu, 27 Jun 2019 17:02:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47034) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgb3Q-0004Vc-4T for qemu-devel@nongnu.org; Thu, 27 Jun 2019 16:31:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgb3O-0003k4-Mu for qemu-devel@nongnu.org; Thu, 27 Jun 2019 16:31:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40484) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgb32-00036Y-1b; Thu, 27 Jun 2019 16:31:12 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7209330BB54B; Thu, 27 Jun 2019 20:31:07 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-69.brq.redhat.com [10.40.204.69]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 01734600CC; Thu, 27 Jun 2019 20:30:57 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Stephen Checkoway , qemu-devel@nongnu.org Date: Thu, 27 Jun 2019 22:27:18 +0200 Message-Id: <20190627202719.17739-28-philmd@redhat.com> In-Reply-To: <20190627202719.17739-1-philmd@redhat.com> References: <20190627202719.17739-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Thu, 27 Jun 2019 20:31:07 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v5 27/28] hw/block/pflash_cfi02: Document commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Laurent Vivier , Thomas Huth , qemu-block@nongnu.org, Peter Maydell , John Snow , Paolo Bonzini , Alistair Francis , Magnus Damm , Markus Armbruster , Max Reitz , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Michael Walle , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Antony Pavlov , "Edgar E. Iglesias" , Jan Kiszka , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/block/pflash_cfi02.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index e9519cbae8..db9dc7d8fb 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -327,7 +327,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset= , unsigned int width) pfl->wcycle =3D 0; pfl->cmd =3D 0; /* fall through to the read code */ - case 0x80: + case 0x80: /* Erase (unlock) */ /* We accept reads during second unlock sequence... */ case 0x00: if (pflash_erase_suspend_mode(pfl) && @@ -342,8 +342,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset= , unsigned int width) /* Flash area read */ ret =3D pflash_data_read(pfl, offset, width); break; - case 0x90: - /* flash ID read */ + case 0x90: /* flash ID read */ switch (boff) { case 0x00: case 0x01: @@ -364,11 +363,11 @@ static uint64_t pflash_read(void *opaque, hwaddr offs= et, unsigned int width) } DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff,= ret); break; - case 0x10: - case 0x30: + case 0x10: /* Chip Erase */ + case 0x30: /* Sector Erase */ /* Toggle bit 2 during erase, but not program. */ toggle_dq2(pfl); - case 0xA0: + case 0xA0: /* Program */ /* Toggle bit 6 */ toggle_dq6(pfl); /* Status register read */ @@ -470,7 +469,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, return; } /* Handle erase resume in erase suspend mode, otherwise reset. */ - if (cmd =3D=3D 0x30) { + if (cmd =3D=3D 0x30) { /* Erase Resume */ if (pflash_erase_suspend_mode(pfl)) { /* Resume the erase. */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUA= L) + @@ -485,7 +484,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, goto reset_flash; } /* Ignore erase suspend. */ - if (cmd =3D=3D 0xB0) { + if (cmd =3D=3D 0xB0) { /* Erase Suspend */ return; } if (boff !=3D pfl->unlock_addr0 || cmd !=3D 0xAA) { @@ -516,9 +515,9 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, case 0x20: pfl->bypass =3D 1; goto do_bypass; - case 0x80: - case 0x90: - case 0xA0: + case 0x80: /* Erase */ + case 0x90: /* Autoselect */ + case 0xA0: /* Program */ pfl->cmd =3D cmd; DPRINTF("%s: starting command %02x\n", __func__, cmd); break; @@ -529,10 +528,10 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, break; case 3: switch (pfl->cmd) { - case 0x80: + case 0x80: /* Erase */ /* We need another unlock sequence */ goto check_unlock0; - case 0xA0: + case 0xA0: /* Program */ if (pflash_erase_suspend_mode(pfl) && pflash_sector_is_erasing(pfl, offset)) { /* Ignore writes to erasing sectors. */ @@ -562,7 +561,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, if (pfl->bypass) goto do_bypass; goto reset_flash; - case 0x90: + case 0x90: /* Autoselect */ if (pfl->bypass && cmd =3D=3D 0x00) { /* Unlock bypass reset */ goto reset_flash; @@ -585,11 +584,11 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, } case 4: switch (pfl->cmd) { - case 0xA0: + case 0xA0: /* Program */ /* Ignore writes while flash data write is occurring */ /* As we suppose write is immediate, this should never happen = */ return; - case 0x80: + case 0x80: /* Erase */ goto check_unlock1; default: /* Should never happen */ @@ -604,7 +603,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, goto reset_flash; } switch (cmd) { - case 0x10: + case 0x10: /* Chip Erase */ if (boff !=3D pfl->unlock_addr0) { DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx = "\n", __func__, offset); @@ -621,8 +620,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); break; - case 0x30: - /* Sector erase */ + case 0x30: /* Sector erase */ pflash_sector_erase(pfl, offset); break; default: @@ -633,10 +631,10 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, break; case 6: switch (pfl->cmd) { - case 0x10: + case 0x10: /* Chip Erase */ /* Ignore writes during chip erase */ return; - case 0x30: + case 0x30: /* Sector erase */ if (cmd =3D=3D 0xB0) { /* * If erase suspend happens during the erase timeout (so D= Q3 is --=20 2.20.1