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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v23 3/7] target/avr: Add instruction decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Rolnik , richard.henderson@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target/avr/insn.decode b/target/avr/insn.decode new file mode 100644 index 0000000000..6b387762c6 --- /dev/null +++ b/target/avr/insn.decode @@ -0,0 +1,175 @@ +# +# A =3D [16 .. 31] +# B =3D [16 .. 23] +# C =3D [24, 26, 28, 30] +# D =3D [0, 2, 4, 6, 8, .. 30] + +%rd 4:5 +%rr 9:1 0:4 + +&rd_rr rd rr +&rd_imm rd imm + +@op_rd_rr .... .. . ..... .... &rd_rr rd=3D%rd rr=3D%rr +ADD 0000 11 . ..... .... @op_rd_rr +ADC 0001 11 . ..... .... @op_rd_rr +AND 0010 00 . ..... .... @op_rd_rr +CP 0001 01 . ..... .... @op_rd_rr +CPC 0000 01 . ..... .... @op_rd_rr +CPSE 0001 00 . ..... .... @op_rd_rr +EOR 0010 01 . ..... .... @op_rd_rr +MOV 0010 11 . ..... .... @op_rd_rr +MUL 1001 11 . ..... .... @op_rd_rr +OR 0010 10 . ..... .... @op_rd_rr +SBC 0000 10 . ..... .... @op_rd_rr +SUB 0001 10 . ..... .... @op_rd_rr + + +%rd_c 4:2 !function=3Dto_C +%imm6 6:2 0:4 + +@op_rd_imm6 .... .... .. .. .... &rd_imm rd=3D%rd_c imm=3D%= imm6 +ADIW 1001 0110 .. .. .... @op_rd_imm6 +SBIW 1001 0111 .. .. .... @op_rd_imm6 + + +%rd_a 4:4 !function=3Dto_A +%rr_a 0:4 !function=3Dto_A +%rd_d 4:4 !function=3Dto_D +%rr_d 0:4 !function=3Dto_D +%imm8 8:4 0:4 + +@op_rd_imm8 .... .... .... .... &rd_imm rd=3D%rd_a imm=3D%= imm8 +ANDI 0111 .... .... .... @op_rd_imm8 +CPI 0011 .... .... .... @op_rd_imm8 +LDI 1110 .... .... .... @op_rd_imm8 +ORI 0110 .... .... .... @op_rd_imm8 +SBCI 0100 .... .... .... @op_rd_imm8 +SUBI 0101 .... .... .... @op_rd_imm8 + + +@op_rd .... ... rd:5 .... +ASR 1001 010 ..... 0101 @op_rd +COM 1001 010 ..... 0000 @op_rd +DEC 1001 010 ..... 1010 @op_rd +ELPM2 1001 000 ..... 0110 @op_rd +ELPMX 1001 000 ..... 0111 @op_rd +INC 1001 010 ..... 0011 @op_rd +LDX1 1001 000 ..... 1100 @op_rd +LDX2 1001 000 ..... 1101 @op_rd +LDX3 1001 000 ..... 1110 @op_rd +LDY2 1001 000 ..... 1001 @op_rd +LDY3 1001 000 ..... 1010 @op_rd +LDZ2 1001 000 ..... 0001 @op_rd +LDZ3 1001 000 ..... 0010 @op_rd +LPM2 1001 000 ..... 0100 @op_rd +LPMX 1001 000 ..... 0101 @op_rd +LSR 1001 010 ..... 0110 @op_rd +NEG 1001 010 ..... 0001 @op_rd +POP 1001 000 ..... 1111 @op_rd +PUSH 1001 001 ..... 1111 @op_rd +ROR 1001 010 ..... 0111 @op_rd +STY2 1001 001 ..... 1001 @op_rd +STY3 1001 001 ..... 1010 @op_rd +STZ2 1001 001 ..... 0001 @op_rd +STZ3 1001 001 ..... 0010 @op_rd +SWAP 1001 010 ..... 0010 @op_rd + + +@op_bit .... .... . bit:3 .... +BCLR 1001 0100 1 ... 1000 @op_bit +BSET 1001 0100 0 ... 1000 @op_bit + + +@op_rd_bit .... ... rd:5 . bit:3 +BLD 1111 100 ..... 0 ... @op_rd_bit +BST 1111 101 ..... 0 ... @op_rd_bit + + +@op_bit_imm .... .. imm:s7 bit:3 +BRBC 1111 01 ....... ... @op_bit_imm +BRBS 1111 00 ....... ... @op_bit_imm + + +BREAK 1001 0101 1001 1000 +EICALL 1001 0101 0001 1001 +EIJMP 1001 0100 0001 1001 +ELPM1 1001 0101 1101 1000 +ICALL 1001 0101 0000 1001 +IJMP 1001 0100 0000 1001 +LPM1 1001 0101 1100 1000 +NOP 0000 0000 0000 0000 +RET 1001 0101 0000 1000 +RETI 1001 0101 0001 1000 +SLEEP 1001 0101 1000 1000 +SPM 1001 0101 1110 1000 +SPMX 1001 0101 1111 1000 +WDR 1001 0101 1010 1000 + + +@op_reg_bit .... .... reg:5 bit:3 +CBI 1001 1000 ..... ... @op_reg_bit +SBI 1001 1010 ..... ... @op_reg_bit +SBIC 1001 1001 ..... ... @op_reg_bit +SBIS 1001 1011 ..... ... @op_reg_bit + + +DES 1001 0100 imm:4 1011 + + +%rd_b 4:3 !function=3Dto_B +%rr_b 0:3 !function=3Dto_B +@fmul .... .... . ... . ... &rd_rr rd=3D%rd_b rr=3D%r= r_b +FMUL 0000 0011 0 ... 1 ... @fmul +FMULS 0000 0011 1 ... 0 ... @fmul +FMULSU 0000 0011 1 ... 1 ... @fmul +MULSU 0000 0011 0 ... 0 ... @fmul + + +%io_imm 9:2 0:4 +@io_rd_imm .... . .. ..... .... &rd_imm rd=3D%rd imm=3D%io= _imm +IN 1011 0 .. ..... .... @io_rd_imm +OUT 1011 1 .. ..... .... @io_rd_imm + + +XCH 1001 001 rd:5 0100 +LAC 1001 001 rd:5 0110 +LAS 1001 001 rd:5 0101 +LAT 1001 001 rd:5 0111 +STX1 1001 001 rr:5 1100 +STX2 1001 001 rr:5 1101 +STX3 1001 001 rr:5 1110 + + +%ldst_d_imm 13:1 10:2 0:3 +@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=3D%ldst_d_imm +LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d +LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d +STDY 10 . 0 .. 1 ..... 1 ... @ldst_d +STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d + + +MOVW 0000 0001 .... .... &rd_rr rd=3D%rd_d rr=3D%r= r_d +MULS 0000 0010 .... .... &rd_rr rd=3D%rd_a rr=3D%r= r_a + +RCALL 1101 imm:s12 +RJMP 1100 imm:s12 + +SBRC 1111 110 rr:5 0 bit:3 +SBRS 1111 111 rr:5 0 bit:3 + +# The 22-bit immediate is partially in the opcode word, +# and partially in the next. Use append_16 to build the +# complete 22-bit value. +%imm_call 4:5 0:1 !function=3Dappend_16 +CALL 1001 010 ..... 111 . imm=3D%imm_call +JMP 1001 010 ..... 110 . imm=3D%imm_call + + +# The 16-bit immediate is completely in the next word. +# Fields cannot be defined with no bits, so we cannot play +# the same trick and append to a zero-bit value. +# Defer reading the immediate until trans_{LDS,STS}. +@ldst_s .... ... rd:5 .... imm=3D0 +LDS 1001 000 ..... 0000 @ldst_s +STS 1001 001 ..... 0000 @ldst_s --=20 2.18.0