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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id y193sm13717005pgd.41.2019.06.25.03.08.34 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 25 Jun 2019 03:08:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=7wvZosJ1yqszSgub/Ojdg6XCIa9KX+av7xHMiaUWf30=; b=ukuvRUIvsQ1K3HDsKJKiB/xMenOJfpLdCut4I8F1cM70n7mUoxNQv1sT2F2dDq8Nbf 682pJwcKD5E6b/8SZDMxxKDP8UVmncZ9TM0sJVBdBqrMZwcvcdQg3FXYoh+vWQItAmGR +yjCIPTHsLmIyfaJ/6ZBj97LIJxUxVs7qR9LlECugRkL5cLZpmCgymBDO2FUhtVPJtrY oCW/T71zy0rnrhfuViUSAH0XY5M1ZzyCxhm4iByb+EoXlCTUE1jbGVAYB8VgWepoYMq7 kKpF0h3/oN66ar2CP4e4QgvlYlpHzqD/p0iiR2JkW0IJXyZZ9iP0WZqCedOtS2Mq4FUY /ziA== X-Gm-Message-State: APjAAAX63cEwv3NqmViDcag3DAfiGqI+5Kbvgs5rhdDwkcE8adsoELCu +vtZXk9aiQYh/8oe4X6vNz5CJg97miwpFeeM X-Google-Smtp-Source: APXvYqw5s9vRuR4YZ0jyxqpcxR9Ry0hi4GcUetfhULDhp2REhv8jbhDevzDeoLZJjVvXCpCYeqEfsA== X-Received: by 2002:a63:3383:: with SMTP id z125mr24262769pgz.8.1561457315890; Tue, 25 Jun 2019 03:08:35 -0700 (PDT) Date: Tue, 25 Jun 2019 03:07:58 -0700 Message-Id: <20190625100757.12580-1-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Palmer Dabbelt To: Alistair Francis X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.196 Subject: [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/csr.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bbad39a337b3..915b9e77df33 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ba551cd3082c..0adb307f3298 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,6 +224,7 @@ typedef struct RISCVCPU { bool ext_u; bool ext_counters; bool ext_ifencei; + bool ext_icsr; =20 char *priv_spec; char *user_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index de67741f3648..ff988917b995 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_u= long *ret_value, { int ret; target_ulong old_value; + RISCVCPU *cpu =3D env_archcpu(env); =20 /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) @@ -803,6 +804,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_= ulong *ret_value, } #endif =20 + /* ensure the CSR extension is enabled. */ + if (!cpu->cfg.ext_icsr) + return -1; + /* check predicate */ if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { return -1; --=20 2.21.0