From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561439013; cv=none; d=zoho.com; s=zohoarc; b=albySNSzazus2IV1ZFkLF+0YdqBFH1A3QT9a01ZFgbHV4oYRhrzT0u0zgqy/Go8pMfJJsGWE5UkBheJ1oXuxkhEDrxgE1qIV+8vUDKwYtgfLDKcy9iGCsAt6k9UgRMJUvR6bbtVY27Do1ODahQ15awB+aWmcj7OGAcTcbFq1Xh4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561439013; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=AENoIXAlyqkvRxQO8lmz/W7KyqLgcOrPfURQC67xFRI=; b=op1YQs2uQHyLx5UUw9V5eJRvangA+eyBds/phYCxFtHMOZfwMVajVa7pRlCAjmb/M0ycO2sz5v5EbpXdZIbugHxEu0YnY4TSTRlPJO0pPu1VWBDRsVmrrtI8KgPykg9DVa5tGK5bCA9Sn+V7I15yBmE+xiQB0+FUCxU5rWpTKfI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561439013064903.7609535510983; Mon, 24 Jun 2019 22:03:33 -0700 (PDT) Received: from localhost ([::1]:56554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdbr-0007pF-TT for importer@patchew.org; Tue, 25 Jun 2019 01:03:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33606) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdZ8-0006gw-8R for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfdZ7-0002OL-7l for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41614) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hfdZ7-0002Mk-27 for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:21 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5FDB881F35 for ; Tue, 25 Jun 2019 05:00:14 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id E14C25C231; Tue, 25 Jun 2019 05:00:13 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:03 -0300 Message-Id: <20190625050008.12789-2-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 25 Jun 2019 05:00:19 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 1/6] i386: Add x-force-features option for testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Jiri Denemark , "Daniel P. Berrange" , "Dr. David Alan Gilbert" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a new option that can be used to disable feature flag filtering. This will allow CPU model compatibility test cases to work without host hardware dependencies. Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 6 ++++++ target/i386/cpu.c | 8 ++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index df99d70c43..25544fdaaa 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1414,6 +1414,12 @@ struct X86CPU { =20 bool check_cpuid; bool enforce_cpuid; + /* + * Force features to be enabled even if the host doesn't support them. + * This is dangerous and should be done only for testing CPUID + * compatibility. + */ + bool force_features; bool expose_kvm; bool expose_tcg; bool migratable; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f8d8f779c1..1bad957f6e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5140,8 +5140,11 @@ static int x86_cpu_filter_features(X86CPU *cpu) uint32_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); uint32_t requested_features =3D env->features[w]; - env->features[w] &=3D host_feat; - cpu->filtered_features[w] =3D requested_features & ~env->features[= w]; + uint32_t available_features =3D requested_features & host_feat; + if (!cpu->force_features) { + env->features[w] =3D available_features; + } + cpu->filtered_features[w] =3D requested_features & ~available_feat= ures; if (cpu->filtered_features[w]) { rv =3D 1; } @@ -5866,6 +5869,7 @@ static Property x86_cpu_properties[] =3D { =20 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), + DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561439175021971.2708146391246; Mon, 24 Jun 2019 22:06:15 -0700 (PDT) Received: from localhost ([::1]:56566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdem-0001TU-3g for importer@patchew.org; Tue, 25 Jun 2019 01:06:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33623) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdZA-0006jA-Db for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfdZ9-0002QW-FI for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44736) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hfdZ9-0002Po-9K for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:23 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 82499BDD1 for ; Tue, 25 Jun 2019 05:00:17 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0F4205D9D3; Tue, 25 Jun 2019 05:00:15 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:04 -0300 Message-Id: <20190625050008.12789-3-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 25 Jun 2019 05:00:17 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 2/6] i386: Remove unused host_cpudef variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Jiri Denemark , "Daniel P. Berrange" , "Dr. David Alan Gilbert" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The variable is completely unused, probably a leftover from previous code clean up. Signed-off-by: Eduardo Habkost Reviewed-by: Dr. David Alan Gilbert --- target/i386/cpu.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1bad957f6e..cf03dc786e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3133,14 +3133,8 @@ static void max_x86_cpu_initfn(Object *obj) char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; int family, model, stepping; - X86CPUDefinition host_cpudef =3D { }; - uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; - - host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx); =20 host_vendor_fms(vendor, &family, &model, &stepping); - cpu_x86_fill_model_id(model_id); =20 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abor= t); --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561439178; cv=none; d=zoho.com; s=zohoarc; b=ZT1Rfy5ub+vMk+l6eHkk6vRZWrSt6xoxqu0GZMf/2EQJIzxJxRxIyN6SaXH/5+9gMykxPPd2OAWUOLkh569sW8I4K+CTyBcwb6w3t/+eFJRXFknVJa6MsI60BMTTo5MsP9RNZfpd4hAzFNlg0ij1mzxPTM0CigPnRytA9EVW7PU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561439178; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ew2WLFIJpL6rfdmnOZpvDs8w19vUh4WYBcVdOlO5x34=; b=QglrD5A/gL7koZXhcbbj3cFx1aFNMWtdGqwrYgDtIp59X0JDw///sPFF5NQvYGHDNIhl9Y1AyknUOYfEk4MJoGqJ4kBnVm9WjHEE/FpIw30chfiRuizEI6RjjlyK2R7XrQRIiloyrR91ez2H5WsJnQrmT87gTdfRW420C6N8t+I= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561439178789384.5202511214296; Mon, 24 Jun 2019 22:06:18 -0700 (PDT) Received: from localhost ([::1]:56568 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdeq-0001hO-11 for importer@patchew.org; Tue, 25 Jun 2019 01:06:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33657) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdZF-0006xy-LE for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfdZE-0002Wi-AV for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52348) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hfdZE-0002Uv-4n for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:28 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F1E31B2DD2 for ; Tue, 25 Jun 2019 05:00:20 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0A7965C236; Tue, 25 Jun 2019 05:00:18 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:05 -0300 Message-Id: <20190625050008.12789-4-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Tue, 25 Jun 2019 05:00:21 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 3/6] qmp: Add "alias-of" field to query-cpu-definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. Berrange" , "Dr. David Alan Gilbert" , Markus Armbruster , Igor Mammedov , Jiri Denemark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Management software will be expected to resolve CPU model name aliases using the new field. Signed-off-by: Eduardo Habkost --- Cc: Eric Blake Cc: Markus Armbruster --- qapi/target.json | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/qapi/target.json b/qapi/target.json index 1d4d54b600..0197c7962c 100644 --- a/qapi/target.json +++ b/qapi/target.json @@ -475,6 +475,12 @@ # to introspect properties configurable using -cpu or -global. # (since 2.9) # +# @alias-of: Name of CPU model this model is an alias for. The target of = the +# CPU model alias may change depending on the machine type. +# Management software is supposed to translate CPU model aliases +# in the VM configuration, because aliases may stop being +# migration-safe in the future (since 4.1) +# # @unavailable-features is a list of QOM property names that # represent CPU model attributes that prevent the CPU from running. # If the QOM property is read-only, that means there's no known @@ -498,7 +504,8 @@ '*migration-safe': 'bool', 'static': 'bool', '*unavailable-features': [ 'str' ], - 'typename': 'str' }, + 'typename': 'str', + '*alias-of' : 'str' }, 'if': 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I386= ) || defined(TARGET_S390X) || defined(TARGET_MIPS)' } =20 ## --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561439307; cv=none; d=zoho.com; s=zohoarc; b=AGd0OMzjAOHy/MTypLT0vHzGPmPhK3GTgQzmtMUQ7aYgpiOYde0xU/uXGpu50mUy7fMFiu++BhKxS3cTKljtF34H5r1mvoiAi/ugc2xz+kUoQNQZTcMJjT7ha9V+cgtSiGyfa9MStd9GmHBY/JQYacXeFKnfxhNSC9/S5dQ4AtU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561439307; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=MYsIs+egVkQbO5tVJY18zTdpo5RB1zysaTvjQGu4bt0=; b=DnsjTXOL7QxdicXk5Q6w4qGgOkoIL1bG6YDg+tWKbp5lwS/oHhTDPRF8p/02FUnUwdNimIX+XMvC9Vj3EMGPbn9aUHJGq69BkMmbhhTPDqpmfSzcQflJQ3iBjiKuJP07pwTLzN37m8ic3MqAQtK5JziXMr/pBPb6D634Njs829E= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561439307922269.038021767537; Mon, 24 Jun 2019 22:08:27 -0700 (PDT) Received: from localhost ([::1]:56580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdgt-0003Zk-AU for importer@patchew.org; Tue, 25 Jun 2019 01:08:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33653) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdZF-0006x6-4c for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfdZC-0002Tc-6s for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60212) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hfdZB-0002Sg-Sv for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:26 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3005430860AA; Tue, 25 Jun 2019 05:00:25 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7A9785D756; Tue, 25 Jun 2019 05:00:22 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:06 -0300 Message-Id: <20190625050008.12789-5-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Tue, 25 Jun 2019 05:00:25 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 4/6] i386: Infrastructure for versioned CPU models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. Berrange" , "Dr. David Alan Gilbert" , Paolo Bonzini , Igor Mammedov , Jiri Denemark , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Base code for versioned CPU models. This will register a "-4.1" version of all existing CPU models, and make the unversioned CPU models be an alias for the -4.1 versions on the pc-*-4.1 machine types. On older machine types, the unversioned CPU models will keep the old behavior. This way, management software can use old machine types while resolving aliases if compatibility with older QEMU versions is required. Using "-machine none", the unversioned CPU models will be aliases to the latest CPU model version. Includes a test case to ensure that: old machine types won't report any alias to versioned CPU models; "pc-*-4.1" will return aliases to -4.1 CPU models; and "-machine none" will report aliases to some versioned CPU model. Signed-off-by: Eduardo Habkost --- Cc: Paolo Bonzini Cc: Richard Henderson --- include/hw/i386/pc.h | 3 + target/i386/cpu-qom.h | 10 +- target/i386/cpu.h | 10 ++ hw/i386/pc.c | 3 + hw/i386/pc_piix.c | 4 + hw/i386/pc_q35.c | 4 + target/i386/cpu.c | 159 +++++++++++++++++---- tests/acceptance/x86_cpu_model_versions.py | 102 +++++++++++++ 8 files changed, 263 insertions(+), 32 deletions(-) create mode 100644 tests/acceptance/x86_cpu_model_versions.py diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c54cc54a47..d2e2ed072f 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -107,6 +107,9 @@ typedef struct PCMachineClass { =20 /* Compat options: */ =20 + /* Default CPU model version. See x86_cpu_set_default_version(). */ + const char *default_cpu_version; + /* ACPI compat: */ bool has_acpi_build; bool rsdp_in_ram; diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 22f95eb3a4..1a52f02a4c 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -36,13 +36,7 @@ #define X86_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU) =20 -/** - * X86CPUDefinition: - * - * CPU model definition data that was not converted to QOM per-subclass - * property defaults yet. - */ -typedef struct X86CPUDefinition X86CPUDefinition; +typedef struct X86CPUModel X86CPUModel; =20 /** * X86CPUClass: @@ -64,7 +58,7 @@ typedef struct X86CPUClass { /* CPU definition, automatically loaded by instance_init if not NULL. * Should be eventually replaced by subclass-specific property default= s. */ - X86CPUDefinition *cpu_def; + X86CPUModel *model; =20 bool host_cpuid_required; int ordering; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 25544fdaaa..800bee3c6a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1925,6 +1925,16 @@ void apic_handle_tpr_access_report(DeviceState *d, t= arget_ulong ip, */ void x86_cpu_change_kvm_default(const char *prop, const char *value); =20 +/* + * Set default CPU model version for all CPU models + * + * If set to NULL, the old unversioned CPU models will be used by default. + * + * If non-NULL, the unversioned CPU models will be aliases to the + * corresponding version. + */ +void x86_cpu_set_default_version(const char *version); + /* Return name of 32-bit register, from a R_* constant */ const char *get_register_name_32(unsigned int reg); =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e96360b47a..d2852a77f8 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1561,6 +1561,9 @@ void pc_cpus_init(PCMachineState *pcms) const CPUArchIdList *possible_cpus; MachineState *ms =3D MACHINE(pcms); MachineClass *mc =3D MACHINE_GET_CLASS(pcms); + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(mc); + + x86_cpu_set_default_version(pcmc->default_cpu_version); =20 /* Calculates the limit to CPU APIC ID values * diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c07c4a5b38..9de86c71bd 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -430,9 +430,11 @@ static void pc_i440fx_machine_options(MachineClass *m) =20 static void pc_i440fx_4_1_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); m->alias =3D "pc"; m->is_default =3D 1; + pcmc->default_cpu_version =3D "4.1"; } =20 DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL, @@ -440,9 +442,11 @@ DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL, =20 static void pc_i440fx_4_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_4_1_machine_options(m); m->alias =3D NULL; m->is_default =3D 0; + pcmc->default_cpu_version =3D NULL; compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 57232aed6b..7755d60167 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -367,8 +367,10 @@ static void pc_q35_machine_options(MachineClass *m) =20 static void pc_q35_4_1_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_machine_options(m); m->alias =3D "q35"; + pcmc->default_cpu_version =3D "4.1"; } =20 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, @@ -376,8 +378,10 @@ DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, =20 static void pc_q35_4_0_1_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_4_1_machine_options(m); m->alias =3D NULL; + pcmc->default_cpu_version =3D NULL; /* * This is the default machine for the 4.0-stable branch. It is basica= lly * a 4.0 that doesn't use split irqchip by default. It MUST hence appl= y the diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cf03dc786e..121f568954 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1432,7 +1432,17 @@ static char *x86_cpu_class_get_model_name(X86CPUClas= s *cc) strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); } =20 -struct X86CPUDefinition { +typedef struct PropValue { + const char *prop, *value; +} PropValue; + +typedef struct X86CPUVersionDefinition { + const char *name; + PropValue *props; +} X86CPUVersionDefinition; + +/* Base definition for a CPU model */ +typedef struct X86CPUDefinition { const char *name; uint32_t level; uint32_t xlevel; @@ -1444,8 +1454,32 @@ struct X86CPUDefinition { FeatureWordArray features; const char *model_id; CPUCaches *cache_info; + /* + * Definitions for alternative versions of CPU model. + * List is terminated by item with name=3D=3DNULL. + * If NULL, base_cpu_versions will be used instead. + */ + const X86CPUVersionDefinition *versions; +} X86CPUDefinition; + +/* CPU model, which might include a specific CPU model version */ +struct X86CPUModel { + /* Base CPU definition */ + X86CPUDefinition *cpudef; + + /* + * CPU model version. If NULL, version will be chosen depending on cu= rrent + * machine. + */ + const char *version; }; =20 +static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef, + const char *version) +{ + return g_strdup_printf("%s-%s", cpudef->name, version); +} + static CPUCaches epyc_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -3010,10 +3044,6 @@ static X86CPUDefinition builtin_x86_defs[] =3D { }, }; =20 -typedef struct PropValue { - const char *prop, *value; -} PropValue; - /* KVM-specific features that are automatically added/removed * from all CPU models when KVM is enabled. */ @@ -3039,6 +3069,19 @@ static PropValue tcg_default_props[] =3D { }; =20 =20 +/* List of CPU model versions used when X86CPUDefinition::versions is NULL= */ +static const X86CPUVersionDefinition base_cpu_versions[] =3D { + { "4.1" }, + { /* end of list */ }, +}; + +static const char *default_cpu_version =3D "4.1"; + +void x86_cpu_set_default_version(const char *version) +{ + default_cpu_version =3D version; +} + void x86_cpu_change_kvm_default(const char *prop, const char *value) { PropValue *pv; @@ -3116,8 +3159,6 @@ static void max_x86_cpu_class_init(ObjectClass *oc, v= oid *data) dc->props =3D max_x86_cpu_properties; } =20 -static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **e= rrp); - static void max_x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); @@ -3771,8 +3812,8 @@ static void x86_cpu_list_entry(gpointer data, gpointe= r user_data) X86CPUClass *cc =3D X86_CPU_CLASS(oc); char *name =3D x86_cpu_class_get_model_name(cc); const char *desc =3D cc->model_description; - if (!desc && cc->cpu_def) { - desc =3D cc->cpu_def->model_id; + if (!desc && cc->model) { + desc =3D cc->model->cpudef->model_id; } =20 qemu_printf("x86 %-20s %-48s\n", name, desc); @@ -3825,6 +3866,11 @@ static void x86_cpu_definition_entry(gpointer data, = gpointer user_data) info->migration_safe =3D cc->migration_safe; info->has_migration_safe =3D true; info->q_static =3D cc->static_model; + if (cc->model && !cc->model->version && default_cpu_version) { + info->has_alias_of =3D true; + info->alias_of =3D x86_cpu_versioned_model_name(cc->model->cpudef, + default_cpu_version); + } =20 entry =3D g_malloc0(sizeof(*entry)); entry->value =3D info; @@ -3898,10 +3944,38 @@ static void x86_cpu_apply_props(X86CPU *cpu, PropVa= lue *props) } } =20 +static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefin= ition *def) +{ + return def->versions ?: base_cpu_versions; +} + +static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUDefinition *def, + const char *version) +{ + const X86CPUVersionDefinition *vdef; + + for (vdef =3D x86_cpu_def_get_versions(def); vdef->name; vdef++) { + PropValue *p; + + for (p =3D vdef->props; p && p->prop; p++) { + object_property_parse(OBJECT(cpu), p->value, p->prop, + &error_abort); + } + + if (!strcmp(vdef->name, version)) { + break; + } + } + + /* If we reached the end of the list, version string was invalid */ + assert(vdef->name); +} + /* Load data from X86CPUDefinition into a X86CPU object */ -static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **e= rrp) +static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **er= rp) { + X86CPUDefinition *def =3D model->cpudef; CPUX86State *env =3D &cpu->env; const char *vendor; char host_vendor[CPUID_VENDOR_SZ + 1]; @@ -3958,11 +4032,16 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDef= inition *def, Error **errp) =20 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp); =20 + if (model->version) { + x86_cpu_apply_version_props(cpu, def, model->version); + } else if (default_cpu_version) { + x86_cpu_apply_version_props(cpu, def, default_cpu_version); + } } =20 #ifndef CONFIG_USER_ONLY /* Return a QDict containing keys for all properties that can be included - * in static expansion of CPU models. All properties set by x86_cpu_load_d= ef() + * in static expansion of CPU models. All properties set by x86_cpu_load_m= odel() * must be included in the dictionary. */ static QDict *x86_cpu_static_props(void) @@ -4176,23 +4255,44 @@ static gchar *x86_gdb_arch_name(CPUState *cs) =20 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) { - X86CPUDefinition *cpudef =3D data; X86CPUClass *xcc =3D X86_CPU_CLASS(oc); =20 - xcc->cpu_def =3D cpudef; + xcc->model =3D data; xcc->migration_safe =3D true; } =20 -static void x86_register_cpudef_type(X86CPUDefinition *def) +static char *x86_cpu_model_type_name(X86CPUModel *model) { - char *typename =3D x86_cpu_type_name(def->name); + if (model->version) { + char *name =3D x86_cpu_versioned_model_name(model->cpudef, + model->version); + char *r =3D x86_cpu_type_name(name); + g_free(name); + return r; + } else { + return x86_cpu_type_name(model->cpudef->name); + } +} + +static void x86_register_cpu_model_type(X86CPUModel *model) +{ + char *typename =3D x86_cpu_model_type_name(model); TypeInfo ti =3D { .name =3D typename, .parent =3D TYPE_X86_CPU, .class_init =3D x86_cpu_cpudef_class_init, - .class_data =3D def, + .class_data =3D model, }; =20 + type_register(&ti); + g_free(typename); +} + +static void x86_register_cpudef_types(X86CPUDefinition *def) +{ + X86CPUModel *m; + const X86CPUVersionDefinition *vdef; + /* AMD aliases are handled at runtime based on CPUID vendor, so * they shouldn't be set on the CPU model table. */ @@ -4200,9 +4300,20 @@ static void x86_register_cpudef_type(X86CPUDefinitio= n *def) /* catch mistakes instead of silently truncating model_id when too lon= g */ assert(def->model_id && strlen(def->model_id) <=3D 48); =20 + /* Unversioned model: */ + m =3D g_new0(X86CPUModel, 1); + m->cpudef =3D def; + x86_register_cpu_model_type(m); + + /* Versioned models: */ + + for (vdef =3D x86_cpu_def_get_versions(def); vdef->name; vdef++) { + X86CPUModel *m =3D g_new0(X86CPUModel, 1); + m->cpudef =3D def; + m->version =3D vdef->name; + x86_register_cpu_model_type(m); + } =20 - type_register(&ti); - g_free(typename); } =20 #if !defined(CONFIG_USER_ONLY) @@ -4989,7 +5100,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) * involved in setting up CPUID data are: * * 1) Loading CPU model definition (X86CPUDefinition). This is - * implemented by x86_cpu_load_def() and should be completely + * implemented by x86_cpu_load_model() and should be completely * transparent, as it is done automatically by instance_init. * No code should need to look at X86CPUDefinition structs * outside instance_init. @@ -5306,7 +5417,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) =20 /* Cache information initialization */ if (!cpu->legacy_cache) { - if (!xcc->cpu_def || !xcc->cpu_def->cache_info) { + if (!xcc->model || !xcc->model->cpudef->cache_info) { char *name =3D x86_cpu_class_get_model_name(xcc); error_setg(errp, "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); @@ -5314,7 +5425,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) return; } env->cache_info_cpuid2 =3D env->cache_info_cpuid4 =3D env->cache_i= nfo_amd =3D - *xcc->cpu_def->cache_info; + *xcc->model->cpudef->cache_info; } else { /* Build legacy cache information */ env->cache_info_cpuid2.l1d_cache =3D &legacy_l1d_cache; @@ -5671,8 +5782,8 @@ static void x86_cpu_initfn(Object *obj) object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort); object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort); =20 - if (xcc->cpu_def) { - x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort); + if (xcc->model) { + x86_cpu_load_model(cpu, xcc->model, &error_abort); } } =20 @@ -6009,7 +6120,7 @@ static void x86_cpu_register_types(void) =20 type_register_static(&x86_cpu_type_info); for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { - x86_register_cpudef_type(&builtin_x86_defs[i]); + x86_register_cpudef_types(&builtin_x86_defs[i]); } type_register_static(&max_x86_cpu_type_info); type_register_static(&x86_base_cpu_type_info); diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/= x86_cpu_model_versions.py new file mode 100644 index 0000000000..c0660a552f --- /dev/null +++ b/tests/acceptance/x86_cpu_model_versions.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python +# +# Basic validation of x86 versioned CPU models and CPU model aliases +# +# Copyright (c) 2019 Red Hat Inc +# +# Author: +# Eduardo Habkost +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# + + +import avocado_qemu + +def get_cpu_prop(vm, prop): + cpu_path =3D vm.command('query-cpus')[0].get('qom_path') + return vm.command('qom-get', path=3Dcpu_path, property=3Dprop) + +class X86CPUModelAliases(avocado_qemu.Test): + """ + Validation of PC CPU model versions and CPU model aliases + + :avocado: tags=3Darch:x86_64 + """ + def test_4_0_alias(self): + """Check if pc-*-4.0 unversioned CPU model won't be an alias""" + # pc-*-4.0 won't expose non-versioned CPU models as aliases + # We do this to help management software to keep compatibility + # with older QEMU versions that didn't have the versioned CPU model + self.vm.add_args('-S') + self.vm.set_machine('pc-i440fx-4.0') + self.vm.launch() + + cpus =3D dict((m['name'], m) for m in self.vm.command('query-cpu-d= efinitions')) + + self.assertFalse(cpus['Cascadelake-Server']['static'], + 'unversioned Cascadelake-Server CPU model must no= t be static') + self.assertNotIn('alias-of', cpus['Cascadelake-Server'], + 'Cascadelake-Server must not be an alias') + + self.assertFalse(cpus['qemu64']['static'], + 'unversioned qemu64 CPU model must not be static') + self.assertNotIn('alias-of', cpus['qemu64'], + 'qemu64 must not be an alias') + self.assertNotIn('alias-of', cpus['qemu64-4.1'], + 'qemu64-4.1 must not be an alias') + + def test_4_1_alias(self): + """Check if unversioned CPU model is an alias pointing to 4.1 vers= ion""" + self.vm.add_args('-S') + self.vm.set_machine('pc-i440fx-4.1') + self.vm.launch() + + cpus =3D dict((m['name'], m) for m in self.vm.command('query-cpu-d= efinitions')) + + self.assertFalse(cpus['Cascadelake-Server']['static'], + 'unversioned Cascadelake-Server CPU model must no= t be static') + self.assertEquals(cpus['Cascadelake-Server'].get('alias-of'), 'Cas= cadelake-Server-4.1', + 'Cascadelake-Server must be an alias of Cascadel= ake-Server-4.1') + self.assertNotIn('alias-of', cpus['Cascadelake-Server-4.1'], + 'Cascadelake-Server-4.1 must not be an alias') + + self.assertFalse(cpus['qemu64']['static'], + 'unversioned qemu64 CPU model must not be static') + self.assertEquals(cpus['qemu64'].get('alias-of'), 'qemu64-4.1', + 'qemu64 must be an alias of qemu64-4.1') + self.assertNotIn('alias-of', cpus['qemu64-4.1'], + 'qemu64-4.1 must not be an alias') + + def test_none_alias(self): + """Check if unversioned CPU model is an alias pointing to 4.1 vers= ion""" + self.vm.add_args('-S') + self.vm.set_machine('none') + self.vm.launch() + + cpus =3D dict((m['name'], m) for m in self.vm.command('query-cpu-d= efinitions')) + + self.assertFalse(cpus['Cascadelake-Server']['static'], + 'unversioned Cascadelake-Server CPU model must no= t be static') + self.assertTrue(cpus['Cascadelake-Server']['alias-of'].startswith(= 'Cascadelake-Server-'), + 'Cascadelake-Server must be an alias of versione= d CPU model') + self.assertNotIn('alias-of', cpus['Cascadelake-Server-4.1'], + 'Cascadelake-Server-4.1 must not be an alias') + + self.assertFalse(cpus['qemu64']['static'], + 'unversioned qemu64 CPU model must not be static') + self.assertTrue(cpus['qemu64']['alias-of'].startswith('qemu64-'), + 'qemu64 must be an alias of versioned CPU model') + self.assertNotIn('alias-of', cpus['qemu64-4.1'], + 'qemu64-4.1 must not be an alias') --=20 2.18.0.rc1.1.g3f1ff2140 From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of redhat.com designates 209.132.183.28 as permitted sender) client-ip=209.132.183.28; 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Tue, 25 Jun 2019 05:00:34 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id x5P50TBP015005 for ; Tue, 25 Jun 2019 01:00:29 -0400 Received: by smtp.corp.redhat.com (Postfix) id 44BE45C239; Tue, 25 Jun 2019 05:00:29 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id B39DB5C231; Tue, 25 Jun 2019 05:00:26 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:07 -0300 Message-Id: <20190625050008.12789-6-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-loop: libvir-list@redhat.com Cc: libvir-list@redhat.com, Igor Mammedov , Jiri Denemark , "Dr. David Alan Gilbert" Subject: [libvirt] [PATCH 5/6] docs: Deprecate CPU model runnability guarantees X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.47]); Tue, 25 Jun 2019 05:01:12 +0000 (UTC) Content-Type: text/plain; charset="utf-8" Document that CPU model runnability guarantees won't apply to unversioned CPU models anymore. Signed-off-by: Eduardo Habkost --- Cc: libvir-list@redhat.com --- qemu-deprecated.texi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index df04f2840b..5fafb62a6d 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -243,3 +243,22 @@ Note that if you are exposing the export via /dev/nbd0= , it is easier to just export the entire image and then mount only /dev/nbd0p1 than it is to reinvoke @command{qemu-nbd -c /dev/nbd0} limited to just a subset of the image. + +@section Backwards compatibility + +@subsection Runnability guarantee of CPU models (since 4.1.0) + +Previous versions of QEMU never changed existing CPU models in +ways that introduced additional host software or hardware +requirements to the VM. This allowed management software to +safely change the machine type of an existing VM without +introducing new requirements ("runnability guarantee"). This +prevented CPU models from being updated to include CPU +vulnerability mitigations, leaving guests vulnerable in the +default configuration. + +The CPU model runnability guarantee won't apply anymore to +existing CPU models. Management software that needs runnability +guarantees must resolve the CPU model aliases using te +``alias-of'' field returned by the ``query-cpu-definitions'' QMP +command. --=20 2.18.0.rc1.1.g3f1ff2140 -- libvir-list mailing list libvir-list@redhat.com https://www.redhat.com/mailman/listinfo/libvir-list From nobody Sun Apr 28 19:42:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561439460; cv=none; d=zoho.com; s=zohoarc; b=atDNcEhxT/bDZJmFpvxgDzwAvKoexPGxoQMvIhjjd9SUPReONUghVxDgdPhE0IDxvgg6QZ3CTCgSNHHFPpmxexmhfKGHhZj8ad+UwBP227okTUToe3hItrlU/6a7BBFeRkQAv6YFX6XvM7aLM8Az3vg1y5n3tJJ7JAPQJCFKGqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561439460; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nA2iWqQfi6H2xSQZ3T18HTZEv+HvLwFILqlc/18zptw=; b=QLzDWpR5zI+61Hp1PSuPJKbi5E8QNivA/TKgGyTHkb37NIv5r6x7r+WH22cItNtptFdooYJmzwGXfOphifrtKSrE1myNScMjjIHeojDKMqwWrZ/WnS5fBWgfwweWoTnsGTrBK4Hrdr60CfcPzqqysI40ZI5sWRypYsLxVozZ9As= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561439460221841.1518310179017; Mon, 24 Jun 2019 22:11:00 -0700 (PDT) Received: from localhost ([::1]:56592 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdjM-000586-1M for importer@patchew.org; Tue, 25 Jun 2019 01:10:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33692) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfdZQ-0007BQ-Va for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfdZP-0002ki-1y for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59512) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hfdZO-0002iP-8L for qemu-devel@nongnu.org; Tue, 25 Jun 2019 01:00:38 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 61B5036899; Tue, 25 Jun 2019 05:00:31 +0000 (UTC) Received: from localhost (ovpn-116-76.gru2.redhat.com [10.97.116.76]) by smtp.corp.redhat.com (Postfix) with ESMTP id D4AB3600C7; Tue, 25 Jun 2019 05:00:30 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 02:00:08 -0300 Message-Id: <20190625050008.12789-7-ehabkost@redhat.com> In-Reply-To: <20190625050008.12789-1-ehabkost@redhat.com> References: <20190625050008.12789-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 25 Jun 2019 05:00:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 6/6] i386: Add Cascadelake-Server-4.1.1 CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. Berrange" , jingqi.liu@intel.com, Tao Xu , "Dr. David Alan Gilbert" , "Hu, Robert" , Igor Mammedov , Jiri Denemark , "Lai, Paul C" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add new version of Cascadelake-Server CPU model, setting stepping=3D5 and enabling the IA32_ARCH_CAPABILITIES MSR. The new feature will introduce a new host software requirement, breaking our CPU model runnability promises. This means we can't enable the new CPU model version by default in QEMU 4.1, because management software isn't ready yet to resolve CPU model aliases. This is why the feature is being enabled in a Cascadelake-Server-4.1.1 CPU model instead of Cascadelake-Server-4.1. Includes a test case to ensure the right combinations of machine-type + CPU model + command-line feature flags will work as expected. Signed-off-by: Eduardo Habkost --- Cc: "Hu, Robert" Cc: Tao Xu Cc: jingqi.liu@intel.com, Cc: "Lai, Paul C" --- target/i386/cpu.c | 15 +++++ tests/acceptance/x86_cpu_model_versions.py | 71 ++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 121f568954..8edae04161 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2607,6 +2607,21 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_6_EAX_ARAT, .xlevel =3D 0x80000008, .model_id =3D "Intel Xeon Processor (Cascadelake)", + .versions =3D (X86CPUVersionDefinition[]) { + /* + * 4.1 won't have arch-capabilities enabled yet, to not break + * older management software + */ + { .name =3D "4.1" }, + { .name =3D "4.1.1", + .props =3D (PropValue[]) { + { "stepping", "5" }, + { "arch-capabilities", "on" }, + { /* end of list */ }, + }, + }, + { /* end of list */ }, + } }, { .name =3D "Icelake-Client", diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/= x86_cpu_model_versions.py index c0660a552f..127239e2a1 100644 --- a/tests/acceptance/x86_cpu_model_versions.py +++ b/tests/acceptance/x86_cpu_model_versions.py @@ -49,6 +49,8 @@ class X86CPUModelAliases(avocado_qemu.Test): 'unversioned Cascadelake-Server CPU model must no= t be static') self.assertNotIn('alias-of', cpus['Cascadelake-Server'], 'Cascadelake-Server must not be an alias') + self.assertNotIn('alias-of', cpus['Cascadelake-Server-4.1'], + 'Cascadelake-Server-4.1 must not be an alias') =20 self.assertFalse(cpus['qemu64']['static'], 'unversioned qemu64 CPU model must not be static') @@ -100,3 +102,72 @@ class X86CPUModelAliases(avocado_qemu.Test): 'qemu64 must be an alias of versioned CPU model') self.assertNotIn('alias-of', cpus['qemu64-4.1'], 'qemu64-4.1 must not be an alias') + + def test_Cascadelake_arch_capabilities_result(self): + # machine-type only: + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.1') + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=3Don,chec= k=3Doff,enforce=3Doff') + vm.launch() + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.1 + Cascadelake-Server should not ha= ve arch-capabilities') + + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.0') + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=3Don,chec= k=3Doff,enforce=3Doff') + vm.launch() + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.0 + Cascadelake-Server should not ha= ve arch-capabilities') + + # command line must override machine-type if CPU model is not vers= ioned: + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.0') + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=3Don,chec= k=3Doff,enforce=3Doff,+arch-capabilities') + vm.launch() + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabili= ties should have arch-capabilities') + + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.1') + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=3Don,chec= k=3Doff,enforce=3Doff,-arch-capabilities') + vm.launch() + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabil= ities should not have arch-capabilities') + + # versioned CPU model overrides machine-type: + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.0') + vm.add_args('-cpu', 'Cascadelake-Server-4.1,x-force-features=3Don,= check=3Doff,enforce=3Doff') + vm.launch() + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.1 + Cascadelake-Server-4.1 should no= t have arch-capabilities') + + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.0') + vm.add_args('-cpu', 'Cascadelake-Server-4.1.1,x-force-features=3Do= n,check=3Doff,enforce=3Doff') + vm.launch() + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.1 + Cascadelake-Server-4.1 should ha= ve arch-capabilities') + + # command line must override machine-type and versioned CPU model: + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.0') + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=3Don,chec= k=3Doff,enforce=3Doff,+arch-capabilities') + vm.launch() + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.0 + Cascadelake-Server-4.1,+arch-cap= abilities should have arch-capabilities') + + vm =3D self.get_vm() + vm.add_args('-S') + vm.set_machine('pc-i440fx-4.1') + vm.add_args('-cpu', 'Cascadelake-Server-4.1.1,x-force-features=3Do= n,check=3Doff,enforce=3Doff,-arch-capabilities') + vm.launch() + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'), + 'pc-i440fx-4.1 + Cascadelake-Server-4.1.1,-arch-c= apabilities should not have arch-capabilities') --=20 2.18.0.rc1.1.g3f1ff2140