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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH v2] riscv: virt: Add cpu-topology DT node. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently, there is no cpu topology defined in RISC-V. Define a device tree node that clearly describes the entire topology. This saves the trouble of scanning individual cache to figure out the topology. Here is the linux kernel patch series that enables topology for RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html CPU topology after applying this patch in QEMU & above series in kernel / # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list 2 / # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id 0 / # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84d94d0c42d8..45a1edcd6c4a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -191,6 +191,7 @@ static void *create_fdt(RISCVVirtState *s, const struct= MemmapEntry *memmap, =20 for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { int cpu_phandle =3D phandle++; + int intc_phandle; nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); @@ -203,9 +204,12 @@ static void *create_fdt(RISCVVirtState *s, const struc= t MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); + intc_phandle =3D phandle++; qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); + qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -214,6 +218,20 @@ static void *create_fdt(RISCVVirtState *s, const struc= t MemmapEntry *memmap, g_free(nodename); } =20 + /* Add cpu-topology node */ + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); + for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { + char *core_nodename =3D g_strdup_printf("/cpus/cpu-map/cluster0/co= re%d", + cpu); + char *cpu_nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); + uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, cpu_nodename); + qemu_fdt_add_subnode(fdt, core_nodename); + qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); + g_free(core_nodename); + g_free(cpu_nodename); + } + cells =3D g_new0(uint32_t, s->soc.num_harts * 4); for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { nodename =3D --=20 2.21.0