From nobody Tue Feb 10 15:46:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561416235; cv=none; d=zoho.com; s=zohoarc; b=k1Og90gGA87lcFiYuFAH4aBtboQlGuq2P+d8ac/C+KaV4LlhectpZooAOopnnKTZHQ7OWE1vF7FRlq5KjReQMQwIw2CH8KYF/eeoMuH/zapeX8hNxuo+frl34p2YTSN8zxp73vYcUBPuNaOi5Wee+rOL/aenyaNTaklhrWk8OcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561416235; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=/SgTNPPsJfCxHETluQbG5NnxhDJEDStW+F5nN1fBiA4=; b=iAqCkqiQLAa2Ioq1BTV8vHnFj8HmK1lPx5PkIbKZ9CDJnMXUN+Ka9VYEZZURQo81mq3LkS/7M9mQlS43uy4vXayBNfwOYMSvNtBFKt2zQYxKhOxCJ4X0QfiAii5hxlLwRXGsNrro0fzFR/UecRW0SmgdAytVNWsuWiQuacvMxoU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561416235639265.9636913551757; Mon, 24 Jun 2019 15:43:55 -0700 (PDT) Received: from localhost ([::1]:55168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfXgj-000826-J7 for importer@patchew.org; Mon, 24 Jun 2019 18:43:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34119) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hfXSN-000493-Vt for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:29:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hfXSL-0005Md-Qf for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:28:59 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:35468) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hfXSL-0005JT-J3 for qemu-devel@nongnu.org; Mon, 24 Jun 2019 18:28:57 -0400 Received: by mail-wm1-x344.google.com with SMTP id c6so891826wml.0 for ; Mon, 24 Jun 2019 15:28:54 -0700 (PDT) Received: from x1.local (183.red-88-21-202.staticip.rima-tde.net. [88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/SgTNPPsJfCxHETluQbG5NnxhDJEDStW+F5nN1fBiA4=; b=n261ZvXHjr+N/pglJVMtesxuU17Fh2nAO+2wEwC0m/S9W0bFfNfAI1AGgfqihJBaMA 2G/lfmf8M9KuJsK0hklVa8qEPx6MSWSuCcnoZAMGmbDo5KoOfkqi9FyVKHtXZ610v5Op sLom89ZZ9/y6xvBh2zWLLxKOxoVHz0meymM3eEPoGo/44oVFLDt06hpvc8QqHL3DOT/4 ha/txKCbEsaIBTLvgx0a2aIOinL41ktlujIooEulOwSbIOyUp/q5zN4b6qDh7V5U9Efe ZYYqzSyJU3ZnZT8Lyn370mqqPC5HV1K1y9zRAkGM5Myy6/wJrV6QP6qNUjD6v7fvCcgF ra8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/SgTNPPsJfCxHETluQbG5NnxhDJEDStW+F5nN1fBiA4=; b=IpXHaBLAi+sanPw7DGXBwiLIDmMW9Bjjvx5JxKsS4rN6BtWXHCTTvKktLg97Fdtj8c gwxJF22LnsztuaNT0CfvXaxGuK6wXd4W6xIxrnVLd8wpMdaIbC8ZGUzmRgncrMasAIX2 6vgGnxMZWvWJ18wDxxFI5P9TAPkv22CRKdbbHFacF34ivBwS69ZBP/TrKoQMv1VZ7A22 JQxAR0yN9cRNX6rXSKR5odrrNGb4x9l3gXIGgBZ3Zv9FimhK7crs01ufJsAnskPCJn+4 s/1ly2Wt5bjO8Z2yp5BpffkP2fDD/s4xOfOIiA65bWRelhSO3o0jltgiY6qyKwneET+P R9Ug== X-Gm-Message-State: APjAAAXeb4GZR3OWEEKN8KfvgehESJ3IbAPOskrxjiDOXTUIUw2BqSbj I441ogtKk5ejKtJnqk1BvKX+ceFc X-Google-Smtp-Source: APXvYqxWDLhu44DmFzobLzftBpLohxi0WgtigD3Bp1eHtcAqb08ysyW1j73j/4e+C9IQPMBtZYoqPQ== X-Received: by 2002:a1c:a848:: with SMTP id r69mr16797119wme.12.1561415332999; Mon, 24 Jun 2019 15:28:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:39 +0200 Message-Id: <20190624222844.26584-6-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 05/10] hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 48 +++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 0b9fb02475..f44326f14f 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -23,6 +23,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/mips/mips.h" #include "hw/pci/pci.h" @@ -466,12 +467,20 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* SDRAM and Device Address Decode */ @@ -510,7 +519,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_DEV_B3: case GT_DEV_BOOT: /* Not implemented */ - DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2= ); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented device register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* ECC */ @@ -520,6 +532,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_ECC_CALC: case GT_ECC_ERRADDR: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* DMA Record */ @@ -543,23 +559,20 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_DMA1_CUR: case GT_DMA2_CUR: case GT_DMA3_CUR: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; =20 /* DMA Channel Control */ case GT_DMA0_CTRL: case GT_DMA1_CTRL: case GT_DMA2_CTRL: case GT_DMA3_CTRL: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; =20 /* DMA Arbiter */ case GT_DMA_ARB: /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented DMA register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* Timer/Counter */ @@ -569,7 +582,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_TC3: case GT_TC_CONTROL: /* Not implemented */ - DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; =20 /* PCI Internal */ @@ -610,6 +626,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI1_CFGADDR: case GT_PCI1_CFGDATA: /* not implemented */ + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: phb->config_reg =3D val & 0x80fffffc; @@ -666,7 +686,10 @@ static void gt64120_writel(void *opaque, hwaddr addr, break; =20 default: - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; } } @@ -940,7 +963,10 @@ static uint64_t gt64120_readl(void *opaque, =20 default: val =3D s->regs[saddr]; - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register read " + "reg:0x03%x size:%u value:0x%0*x\n", + saddr << 2, size, size << 1, val); break; } =20 --=20 2.19.1