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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 03/10] hw/mips/gt64xxx_pci: Fix 'braces' coding style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Since we'll move this code around, fix its style first: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- hw/mips/gt64xxx_pci.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index bbd719f091..cfd497960c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -257,19 +257,25 @@ static void check_reserved_space(hwaddr *start, hwadd= r *length) hwaddr begin =3D *start; hwaddr end =3D *start + *length; =20 - if (end >=3D 0x1e000000LL && end < 0x1f100000LL) + if (end >=3D 0x1e000000LL && end < 0x1f100000LL) { end =3D 0x1e000000LL; - if (begin >=3D 0x1e000000LL && begin < 0x1f100000LL) + } + if (begin >=3D 0x1e000000LL && begin < 0x1f100000LL) { begin =3D 0x1f100000LL; - if (end >=3D 0x1fc00000LL && end < 0x1fd00000LL) + } + if (end >=3D 0x1fc00000LL && end < 0x1fd00000LL) { end =3D 0x1fc00000LL; - if (begin >=3D 0x1fc00000LL && begin < 0x1fd00000LL) + } + if (begin >=3D 0x1fc00000LL && begin < 0x1fd00000LL) { begin =3D 0x1fd00000LL; + } /* XXX: This is broken when a reserved range splits the requested rang= e */ - if (end >=3D 0x1f100000LL && begin < 0x1e000000LL) + if (end >=3D 0x1f100000LL && begin < 0x1e000000LL) { end =3D 0x1e000000LL; - if (end >=3D 0x1fd00000LL && begin < 0x1fc00000LL) + } + if (end >=3D 0x1fd00000LL && begin < 0x1fc00000LL) { end =3D 0x1fc00000LL; + } =20 *start =3D begin; *length =3D end - begin; @@ -385,8 +391,9 @@ static void gt64120_writel (void *opaque, hwaddr addr, PCIHostState *phb =3D PCI_HOST_BRIDGE(s); uint32_t saddr; =20 - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val =3D bswap32(val); + } =20 saddr =3D (addr & 0xfff) >> 2; switch (saddr) { @@ -937,8 +944,9 @@ static uint64_t gt64120_readl (void *opaque, break; } =20 - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val =3D bswap32(val); + } =20 return val; } @@ -990,8 +998,9 @@ static void gt64120_pci_set_irq(void *opaque, int irq_n= um, int level) /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ pic_level =3D 0; for (i =3D 0; i < 4; i++) { - if (pic_irq =3D=3D piix4_dev->config[0x60 + i]) + if (pic_irq =3D=3D piix4_dev->config[0x60 + i]) { pic_level |=3D pci_irq_levels[i]; + } } qemu_set_irq(pic[pic_irq], pic_level); } --=20 2.19.1