From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983000; cv=none; d=zoho.com; s=zohoarc; b=WSIUpEQZi0+RIZ1I38a9+QMTQwtwt3NtODSUc3RVqhWJzbN7W2/yg2uwvPN/32iDQNwSIirDVS4zSnQ7/velMMIO0NGmFuqnU17YMStUFqcyHPba0gC/S2PWrYiwvGQwpsCUrMehhEMHIyQcYzeI6K6gJ1UNkjwf+ePwyUq8c1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560983000; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=iftj1M+WPdNGPV9QG4toD4HYvDaSg736nqNKF5gFVwo=; b=Ojp8YzxmoqPi9L/eD4LlLy5gDCYyrl1y2J139ubvOAPJFUV1icttzXrdoDH7UKa+ax4k3CA6oo9wdYnf53iR9deOFeB14JYH3jNeNV48hAFNR3X+SXHvwfzQymF7zje6OE5NjXPEtFB1hUsC2Yutfb2sehX50Q/KDYqaMuiHNw0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560983000686990.765645250206; Wed, 19 Jun 2019 15:23:20 -0700 (PDT) Received: from localhost ([::1]:42298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdiyv-0003En-66 for importer@patchew.org; Wed, 19 Jun 2019 18:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35949) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdiwp-0001ek-2b for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdiwn-0007iE-LH for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:55 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:35475) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwn-0007fN-CR for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MzR0i-1iYppW0ujA-00vQg8; Thu, 20 Jun 2019 00:19:50 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:24 +0200 Message-Id: <20190619221933.1981-2-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:NhQqWsTeW+0bMiwGym5bYPXwjtBviGB7fMaeSNfiDskP9v+uBIR zXBNyy84abGm/ReAdsHskhlu5vFGVJ5RvdqUY2HASBTJJPtF//3euJizJ6uCMkkjpgCIUNY 2HNAzRTnVKvRY2KTgCVohNSnma4Wm90Uz3+s25k5i87gW6iR4vcKs8eEG0M7Wb0+OLwQMlm sY3h6WDtAC9NsH7MkKg2g== X-UI-Out-Filterresults: notjunk:1;V03:K0:Nbd5B4q3H70=:QHw8bso+Zx9yb4HmNY+v7Y mX1wEVPcYz1GEtr3WPJ76hVF5Q+mj3LnExYyY715u5HYJ7BgP+/NShu/SXlhb0wBj7sNvB+Fe nSV9ZsWPpBf9CnpwLGoxukba3plA0JbiZGG3W3zK0GlgqnwOdGI0tJCikkQxy4LLpKh2pM3/G PJPJZ9sytZzQrD7U7cDqh3lfvirzRnUJ5Eth0XoAEOd38XQ3+MVsauaYgkR8N3Wp7709chzy6 CrLevY0htOsyL2d17Cehg06A+GQGeob97LAoocaAFEkNWrYyvgrNng97yEIwQFrj7C0ejrXXK fF0C0Bpa067pKJ7Oo6JJ5K7vNJx9/1KhcfqwFg3JbxJCxAdFqYy/VAIC1K86Sr6NZ1j+ekPlM qcX/2k3Ln3HwHQrvkJl/cKArAOJhLUaUTUsGcF1Uc/KrHIJlVoQQHToQ5VYaMjdIqMJUrO5Lg 0bZBN6LJE8WhVTOk/Gif9/D51VEH86E+fiIhqsCv3ZEfoiUQEG5j2tDToHF0QvpmN4SXztQrV I9VbiXgFd/95ip2iEFvzBADY6qi/yMj5pc7m3anL/y7ZpmPiZZTHfanBs4amX3ryyBMtqCvIS G9WZjifLTIFfDqQ30Q61GjsWY2MygVKhQMO0syyoTIG21JiCEK7Cv13WjUtBSVjY54KBo9Sxb Ru5N3e3BCMHbMtokBX9ok0+XYQxl/9lwMU2zBeMY1OO+xQkw8gaW6KFeVgKmM14WIRrUs0m+Q 8sjR3s/oVwpiJxyyVfAGK6VSPeuy+rr91/mn99Ca/3S1ggZvoUqEbvdFt3Q= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.131 Subject: [Qemu-devel] [PATCH v8 01/10] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate Quadra 800. Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/char/escc.c | 30 ++++++++++++++++++++++++------ include/hw/char/escc.h | 1 + 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 8ddbb4be4f..2748bd62c3 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -43,14 +43,21 @@ * mouse and keyboard ports don't implement all functions and they are * only asynchronous. There is no DMA. * - * Z85C30 is also used on PowerMacs. There are some small differences - * between Sparc version (sunzilog) and PowerMac (pmac): + * Z85C30 is also used on PowerMacs and m68k Macs. + * + * There are some small differences between Sparc version (sunzilog) + * and PowerMac (pmac): * Offset between control and data registers * There is some kind of lockup bug, but we can ignore it * CTS is inverted * DMA on pmac using DBDMA chip * pmac can do IRDA and faster rates, sunzilog can only do 38400 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz + * + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), + * but registers are grouped by type and not by channel: + * channel is selected by bit 0 of the address (instead of bit 1) + * and register is selected by bit 1 of the address (instead of bit 0). */ =20 /* @@ -170,6 +177,16 @@ static void handle_kbd_command(ESCCChannelState *s, in= t val); static int serial_can_receive(void *opaque); static void serial_receive_byte(ESCCChannelState *s, int ch); =20 +static int reg_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift + 1 : s->it_shift; +} + +static int chn_shift(ESCCState *s) +{ + return s->bit_swap ? s->it_shift : s->it_shift + 1; +} + static void clear_queue(void *opaque) { ESCCChannelState *s =3D opaque; @@ -434,8 +451,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, int newreg, channel; =20 val &=3D 0xff; - saddr =3D (addr >> serial->it_shift) & 1; - channel =3D (addr >> (serial->it_shift + 1)) & 1; + saddr =3D (addr >> reg_shift(serial)) & 1; + channel =3D (addr >> chn_shift(serial)) & 1; s =3D &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -545,8 +562,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, uint32_t ret; int channel; =20 - saddr =3D (addr >> serial->it_shift) & 1; - channel =3D (addr >> (serial->it_shift + 1)) & 1; + saddr =3D (addr >> reg_shift(serial)) & 1; + channel =3D (addr >> chn_shift(serial)) & 1; s =3D &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -830,6 +847,7 @@ static void escc_realize(DeviceState *dev, Error **errp) static Property escc_properties[] =3D { DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h index 42aca83611..8762f61c14 100644 --- a/include/hw/char/escc.h +++ b/include/hw/char/escc.h @@ -50,6 +50,7 @@ typedef struct ESCCState { =20 struct ESCCChannelState chn[2]; uint32_t it_shift; + bool bit_swap; MemoryRegion mmio; uint32_t disabled; uint32_t frequency; --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983347; cv=none; d=zoho.com; s=zohoarc; b=lQkQK7KqVzzVMGXkl5AWqa1vdxzHNFWnfZ7caHuZqgrZF+WZME5v2jVjy/RRQ+hRpGoyHa8X3EMFghhxHiaHQw1DUOtXAWujCdI6Mw7uv3w+X70+no5ysoU74AEb4P65WwAM9L0012/O/RMzMewIRdgN1AUf6dhmBu4ZhKVNXb4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560983347; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 19 Jun 2019 18:21:00 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:54129) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwr-0007mg-On; Wed, 19 Jun 2019 18:20:58 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mzyi6-1iZNnF1Uco-00x5N4; Thu, 20 Jun 2019 00:19:51 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:25 +0200 Message-Id: <20190619221933.1981-3-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:aOSjNeWCx1/xAQ4OwND1Esp3OaXSbqktvWnScQQ1BWOMSl8JSYI BU55POtt5KUXKFuAs5Y0XKDyH1B4dRFx5WboKHVrP2sN3jOo7C8Pp2eK2tuV1KPvfnzwsWu 9m0DFswOFvIaH8ACS/mHWCcxEV1ZhcbsjyXWsb7Wz83Y/ElSGxbQUrnksPqtH0/7NxZ/csx 7TRboumIyyJRf1G30kXfA== X-UI-Out-Filterresults: notjunk:1;V03:K0:GRxGADK+/ek=:IXToAd4lGkSoWZ6/8hctWZ pC3k2TNGxRaKgLmz8iG23oP1IcO4w7FCmLuWB2boepLXPak8teG/pUjpvZ4JnT95GJDU0Rl6k +eDPPiV/2b8dKN9UWkoLNQkQaZy3tsl1iW/gZI3V6L9wBcWJdiVrIOwgqr3KjZ2cOjQvVfuFA RdI0n7UoUGiRxnru3yoI43x05kfHPgLinjEbBlMfl6KeovThMoEiM8DbAsvW3mc8LR4K4/drc QzvY4zbwKqGYmSnfrUUz8cOnt4aPOkR36umVc3mbWqRnFOfI+7e0Hxd4Fa5Y1nvfnHG9g81Gn UXFFwW383KG4TqYFyhWux/hFQwMvnDm9o3Ge4L3Djm2AoRzp/3zrgYQkD3fpEGFawpSXx0S6U 9nvivhbwcUGvJCLPMEVIjb+jTpVaWVt24FOW2TpwJnqQ09fjUFvmTjLVB9779Xgh4N0qxgq4v YFweCtbLEu5s4Nava1htPVDgQ8siNGkBfG7cSpkqZY4BCH+8lZxDlysuHbdSjYrENozobikFb yWX0tuRiCkefrq8UZHbcaHFqHWKgth3amXO4YUJxeFpojBVuqbkY4kXiIbaXb4eQpO/y/2ews qQ6cLbu95AKYdNRA9lBi8w8hUidBf6pkL4SxDiHcXNpufoIK0SqiLhZaG7iYf3pYxAWpp3BDy 7Z60yu0P7+Ne4O5AOEg3aqMT/YlnoDqLeAPVORy513CxzSQJE8Ds1iihsKiWW0bmp4LyD6FJ7 l8flX4g+sDklsNezT3p2Mhdxz99RbEihkwrSyw== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v8 02/10] esp: add pseudo-DMA as used by Macintosh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" There is no DMA in Quadra 800, so the CPU reads/writes the data from the PDMA register (offset 0x100, ESP_PDMA in hw/m68k/q800.c) and copies them to/from the memory. There is a nice assembly loop in the kernel to do that, see linux/drivers/scsi/mac_esp.c:MAC_ESP_PDMA_LOOP(). The start of the transfer is triggered by the DREQ interrupt (see linux mac_esp_send_pdma_cmd()), the CPU polls on the IRQ flag to start the transfer after a SCSI command has been sent (in Quadra 800 it goes through the VIA2, the via2-irq line and the vIFR register) The Macintosh hardware includes hardware handshaking to prevent the CPU from reading invalid data or writing data faster than the peripheral device can accept it. This is the "blind mode", and from the doc: "Approximate maximum SCSI transfer rates within a blocks are 1.4 MB per second for blind transfers in the Macintosh II" Some references can be found in: Apple Macintosh Family Hardware Reference, ISBN 0-201-19255-1 Guide to the Macintosh Family Hardware, ISBN-0-201-52405-8 Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier --- hw/scsi/esp.c | 296 +++++++++++++++++++++++++++++++++++++----- include/hw/scsi/esp.h | 7 + 2 files changed, 274 insertions(+), 29 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 7508d035ca..edacb0bd9f 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -36,6 +36,8 @@ * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C1= 00.txt * and * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9= X.txt + * + * On Macintosh Quadra it is a NCR53C96. */ =20 static void esp_raise_irq(ESPState *s) @@ -56,6 +58,16 @@ static void esp_lower_irq(ESPState *s) } } =20 +static void esp_raise_drq(ESPState *s) +{ + qemu_irq_raise(s->irq_data); +} + +static void esp_lower_drq(ESPState *s) +{ + qemu_irq_lower(s->irq_data); +} + void esp_dma_enable(ESPState *s, int irq, int level) { if (level) { @@ -82,29 +94,11 @@ void esp_request_cancelled(SCSIRequest *req) } } =20 -static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +static int get_cmd_cb(ESPState *s) { - uint32_t dmalen; int target; =20 target =3D s->wregs[ESP_WBUSID] & BUSID_DID; - if (s->dma) { - dmalen =3D s->rregs[ESP_TCLO]; - dmalen |=3D s->rregs[ESP_TCMID] << 8; - dmalen |=3D s->rregs[ESP_TCHI] << 16; - if (dmalen > buflen) { - return 0; - } - s->dma_memory_read(s->dma_opaque, buf, dmalen); - } else { - dmalen =3D s->ti_size; - if (dmalen > TI_BUFSZ) { - return 0; - } - memcpy(buf, s->ti_buf, dmalen); - buf[0] =3D buf[2] >> 5; - } - trace_esp_get_cmd(dmalen, target); =20 s->ti_size =3D 0; s->ti_rptr =3D 0; @@ -123,8 +117,48 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uin= t8_t buflen) s->rregs[ESP_RINTR] =3D INTR_DC; s->rregs[ESP_RSEQ] =3D SEQ_0; esp_raise_irq(s); + return -1; + } + return 0; +} + +static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) +{ + int target; + uint32_t dmalen; + + target =3D s->wregs[ESP_WBUSID] & BUSID_DID; + if (s->dma) { + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen > buflen) { + return 0; + } + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, buf, dmalen); + } else { + memcpy(s->pdma_buf, buf, dmalen); + s->pdma_len =3D dmalen; + s->pdma_start =3D s->pdma_buf; + s->pdma_cur =3D s->pdma_buf; + esp_raise_drq(s); + return 0; + } + } else { + dmalen =3D s->ti_size; + if (dmalen > TI_BUFSZ) { + return 0; + } + memcpy(buf, s->ti_buf, dmalen); + buf[0] =3D buf[2] >> 5; + } + trace_esp_get_cmd(dmalen, target); + + if (get_cmd_cb(s) < 0) { return 0; } + return dmalen; } =20 @@ -163,6 +197,16 @@ static void do_cmd(ESPState *s, uint8_t *buf) do_busid_cmd(s, &buf[1], busid); } =20 +static void satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) { + do_cmd(s, s->pdma_start); + } +} + static void handle_satn(ESPState *s) { uint8_t buf[32]; @@ -172,11 +216,22 @@ static void handle_satn(ESPState *s) s->dma_cb =3D handle_satn; return; } + s->pdma_cb =3D satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) do_cmd(s, buf); } =20 +static void s_without_satn_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + if (s->pdma_cur !=3D s->pdma_start) { + do_busid_cmd(s, s->pdma_start, 0); + } +} + static void handle_s_without_atn(ESPState *s) { uint8_t buf[32]; @@ -186,18 +241,36 @@ static void handle_s_without_atn(ESPState *s) s->dma_cb =3D handle_s_without_atn; return; } + s->pdma_cb =3D s_without_satn_pdma_cb; len =3D get_cmd(s, buf, sizeof(buf)); if (len) { do_busid_cmd(s, buf, 0); } } =20 +static void satn_stop_pdma_cb(ESPState *s) +{ + if (get_cmd_cb(s) < 0) { + return; + } + s->cmdlen =3D s->pdma_cur - s->pdma_start; + if (s->cmdlen) { + trace_esp_handle_satn_stop(s->cmdlen); + s->do_cmd =3D 1; + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_CD; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); + } +} + static void handle_satn_stop(ESPState *s) { if (s->dma && !s->dma_enabled) { s->dma_cb =3D handle_satn_stop; return; } + s->pdma_cb =3D satn_stop_pdma_cb;; s->cmdlen =3D get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); if (s->cmdlen) { trace_esp_handle_satn_stop(s->cmdlen); @@ -209,16 +282,33 @@ static void handle_satn_stop(ESPState *s) } } =20 +static void write_response_pdma_cb(ESPState *s) +{ + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + esp_raise_irq(s); +} + static void write_response(ESPState *s) { trace_esp_write_response(s->status); s->ti_buf[0] =3D s->status; s->ti_buf[1] =3D 0; if (s->dma) { - s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); - s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; - s->rregs[ESP_RSEQ] =3D SEQ_CD; + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); + s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; + s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSEQ] =3D SEQ_CD; + } else { + s->pdma_len =3D 2; + s->pdma_start =3D s->ti_buf; + s->pdma_cur =3D s->ti_buf; + s->pdma_cb =3D write_response_pdma_cb; + esp_raise_drq(s); + return; + } } else { s->ti_size =3D 2; s->ti_rptr =3D 0; @@ -240,6 +330,41 @@ static void esp_dma_done(ESPState *s) esp_raise_irq(s); } =20 +static void do_dma_pdma_cb(ESPState *s) +{ + int to_device =3D (s->ti_size < 0); + int len =3D s->pdma_cur - s->pdma_start; + if (s->do_cmd) { + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); + return; + } + s->dma_left -=3D len; + s->async_buf +=3D len; + s->async_len -=3D len; + if (to_device) { + s->ti_size +=3D len; + } else { + s->ti_size -=3D len; + } + if (s->async_len =3D=3D 0) { + scsi_req_continue(s->current_req); + /* + * If there is still data to be read from the device then + * complete the DMA operation immediately. Otherwise defer + * until the scsi layer has completed. + */ + if (to_device || s->dma_left !=3D 0 || s->ti_size =3D=3D 0) { + return; + } + } + + /* Partially filled a scsi buffer. Complete immediately. */ + esp_dma_done(s); +} + static void esp_do_dma(ESPState *s) { uint32_t len; @@ -250,10 +375,27 @@ static void esp_do_dma(ESPState *s) trace_esp_do_dma(s->cmdlen, len); assert (s->cmdlen <=3D sizeof(s->cmdbuf) && len <=3D sizeof(s->cmdbuf) - s->cmdlen); - s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cur =3D &s->cmdbuf[s->cmdlen]; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } + trace_esp_handle_ti_cmd(s->cmdlen); + s->ti_size =3D 0; + s->cmdlen =3D 0; + s->do_cmd =3D 0; + do_cmd(s, s->cmdbuf); return; } if (s->async_len =3D=3D 0) { + if (s->dma_left =3D=3D 0) { + esp_dma_done(s); + } /* Defer until data is available. */ return; } @@ -262,9 +404,27 @@ static void esp_do_dma(ESPState *s) } to_device =3D (s->ti_size < 0); if (to_device) { - s->dma_memory_read(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_read) { + s->dma_memory_read(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } else { - s->dma_memory_write(s->dma_opaque, s->async_buf, len); + if (s->dma_memory_write) { + s->dma_memory_write(s->dma_opaque, s->async_buf, len); + } else { + s->pdma_len =3D len; + s->pdma_start =3D s->async_buf; + s->pdma_cur =3D s->async_buf; + s->pdma_cb =3D do_dma_pdma_cb; + esp_raise_drq(s); + return; + } } s->dma_left -=3D len; s->async_buf +=3D len; @@ -371,8 +531,7 @@ static void handle_ti(ESPState *s) s->dma_left =3D minlen; s->rregs[ESP_RSTAT] &=3D ~STAT_TC; esp_do_dma(s); - } - if (s->do_cmd) { + } else if (s->do_cmd) { trace_esp_handle_ti_cmd(s->cmdlen); s->ti_size =3D 0; s->cmdlen =3D 0; @@ -399,6 +558,7 @@ void esp_hard_reset(ESPState *s) static void esp_soft_reset(ESPState *s) { qemu_irq_lower(s->irq); + qemu_irq_lower(s->irq_data); esp_hard_reset(s); } =20 @@ -639,6 +799,80 @@ static const MemoryRegionOps sysbus_esp_mem_ops =3D { .valid.accepts =3D esp_mem_accepts, }; =20 +static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint32_t dmalen; + + dmalen =3D s->rregs[ESP_TCLO]; + dmalen |=3D s->rregs[ESP_TCMID] << 8; + dmalen |=3D s->rregs[ESP_TCHI] << 16; + if (dmalen =3D=3D 0 || s->pdma_len =3D=3D 0) { + return; + } + switch (size) { + case 1: + *s->pdma_cur++ =3D val; + s->pdma_len--; + dmalen--; + break; + case 2: + *s->pdma_cur++ =3D val >> 8; + *s->pdma_cur++ =3D val; + s->pdma_len -=3D 2; + dmalen -=3D 2; + break; + } + s->rregs[ESP_TCLO] =3D dmalen & 0xff; + s->rregs[ESP_TCMID] =3D dmalen >> 8; + s->rregs[ESP_TCHI] =3D dmalen >> 16; + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } +} + +static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, + unsigned int size) +{ + SysBusESPState *sysbus =3D opaque; + ESPState *s =3D &sysbus->esp; + uint64_t val =3D 0; + + if (s->pdma_len =3D=3D 0) { + return 0; + } + switch (size) { + case 1: + val =3D *s->pdma_cur++; + s->pdma_len--; + break; + case 2: + val =3D *s->pdma_cur++; + val =3D (val << 8) | *s->pdma_cur++; + s->pdma_len -=3D 2; + break; + } + + if (s->pdma_len =3D=3D 0 && s->pdma_cb) { + esp_lower_drq(s); + s->pdma_cb(s); + s->pdma_cb =3D NULL; + } + return val; +} + +static const MemoryRegionOps sysbus_esp_pdma_ops =3D { + .read =3D sysbus_esp_pdma_read, + .write =3D sysbus_esp_pdma_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 2, +}; + static const struct SCSIBusInfo esp_scsi_info =3D { .tcq =3D false, .max_target =3D ESP_MAX_DEVS, @@ -671,12 +905,16 @@ static void sysbus_esp_realize(DeviceState *dev, Erro= r **errp) ESPState *s =3D &sysbus->esp; =20 sysbus_init_irq(sbd, &s->irq); + sysbus_init_irq(sbd, &s->irq_data); assert(sysbus->it_shift !=3D -1); =20 s->chip_id =3D TCHI_FAS100A; memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_= ops, - sysbus, "esp", ESP_REGS << sysbus->it_shift); + sysbus, "esp-regs", ESP_REGS << sysbus->it_shift= ); sysbus_init_mmio(sbd, &sysbus->iomem); + memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_= ops, + sysbus, "esp-pdma", 2); + sysbus_init_mmio(sbd, &sysbus->pdma); =20 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); =20 diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index adab63d1c9..b19b86b27a 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -18,6 +18,7 @@ struct ESPState { uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; + qemu_irq irq_data; uint8_t chip_id; bool tchi_written; int32_t ti_size; @@ -48,6 +49,11 @@ struct ESPState { ESPDMAMemoryReadWriteFunc dma_memory_write; void *dma_opaque; void (*dma_cb)(ESPState *s); + uint8_t pdma_buf[32]; + uint32_t pdma_len; + uint8_t *pdma_start; + uint8_t *pdma_cur; + void (*pdma_cb)(ESPState *s); }; =20 #define TYPE_ESP "esp" @@ -59,6 +65,7 @@ typedef struct { /*< public >*/ =20 MemoryRegion iomem; + MemoryRegion pdma; uint32_t it_shift; ESPState esp; } SysBusESPState; --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983498; cv=none; d=zoho.com; s=zohoarc; b=nj3zrXbYIz6hUNX/jp1NWC18US52HJnv6eo/K7FTgY8SWUPo9Nm4IsCYUPbhAFduCAELMuPBkVJUQsiSsEDYEQKe8YgUn+MxryHL7TaH5V60P+DbjxOJTgBcbB2ms8+4iOnxsVSJQa1PmcLdVoaq2edw5WrY1SL/Qf91FC9llAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560983498; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 19 Jun 2019 18:21:02 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:48279) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwq-0007kw-Td; Wed, 19 Jun 2019 18:20:57 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MIMOy-1hry1d184a-00EMcK; Thu, 20 Jun 2019 00:19:53 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:26 +0200 Message-Id: <20190619221933.1981-4-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:OezYkuzxdEYCo1KHRSy3WGCmwYQBIEQd7IDEIGSHNRVjnRxAIeH r9DI/D9EDZLOjEmYMDORwBMi0EYkNiHs8zdNnLvPISZ6K4YSutrmdNbd241/TKIBDZyMwki VhpsYmH5G8ziR8L1kYxhOVMUUtPhgwRllkHlgKsU3ajYImpz2JUMaTMTN6ZIjM0kRH20KaC OpoSnQ/fMahq7JSZLO/3Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:NKO5DC2LVNo=:0/JNrXQVerKLX9yGYjQO5l kfnuxgd/r95129hCFZ5wbsubk4/tM3IajNB9y5DfhKCtoZZfDrObR5PHRIMlTYX5Yc0TYY282 Li6NXAWCCix03Y9g6rlrsHtiKo6DsdbefNvjK76IM8FzqnjXBRemUf7u9ZUjulP69m/ACa0rW 0nXssWFNKDK9rB/ZbYggtRE8ng822IaI2JN8vkI1ZZEPTWydGyx0g06kVzBrG1XFLOHHL2ztV HQPXEgHF3b2Z/GWG2r3Uco7fyte6pWCEPvmW5P2IOddZxbgler8yWJv/0mbYrgWeSLyDw7tH+ Fiiu6Ib98rv2JSqrSy51S62uXt6fIYJ0qLeeNH92H9e4d6tKbWIvsV1iONypvwZnPffBjuDtl 6j0KEzqbSQUbmjQ/zRTWT/MkiFEAbLiuuhbk6I16d/7pOlLwpNiTGL2NghpCEaQ1FWlY0bBCy 9kg+YyiMxHLYjYDNFT2K67A2oBe3Y7ZGJ7VOHouwi0OF+kxVbTsF/KdRApt082Eo+pCfpLlQ4 AgQKGeV7FlcLylLSc+HHS58FVNy2ebN5OT8uKSkPsM/pR9rq3vt/WdpNmKlGfLpEW3WUtQadr cX7Gsro6/zeeIDVYX3SJ6+xro9phmdPrr6MW9s4U/+ZjEq3Scme+cPRwN0yQKUQTUmn1dNkQm Xquhfq380u8U8kfKZhshIGag6pRXmBQ0SwkaQTdZCK0Snu1pvhGlqg0jE+byeJtVL9dElejjy D1w38SfoGViiUkElHLGRb4ML0kdq8FBAfb3aLNoxuV7pqqAorTARUgiYRLY= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v8 03/10] dp8393x: manage big endian bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This is needed by Quadra 800, this card can run on little-endian or big-endian bus. Signed-off-by: Laurent Vivier Tested-by: Herv=C3=A9 Poussineau Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 88 +++++++++++++++++++++++++++++++----------------- 1 file changed, 57 insertions(+), 31 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index bdb0b3b2c2..b014c015c6 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -150,6 +150,7 @@ typedef struct dp8393xState { =20 /* Hardware */ uint8_t it_shift; + bool big_endian; qemu_irq irq; #ifdef DEBUG_SONIC int irq_level; @@ -220,6 +221,29 @@ static uint32_t dp8393x_wt(dp8393xState *s) return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; } =20 +static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base, + int offset) +{ + uint16_t val; + + if (s->big_endian) { + val =3D be16_to_cpu(base[offset * width + width - 1]); + } else { + val =3D le16_to_cpu(base[offset * width]); + } + return val; +} + +static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int of= fset, + uint16_t val) +{ + if (s->big_endian) { + base[offset * width + width - 1] =3D cpu_to_be16(val); + } else { + base[offset * width] =3D cpu_to_le16(val); + } +} + static void dp8393x_update_irq(dp8393xState *s) { int level =3D (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; @@ -251,12 +275,12 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Fill current entry */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->cam[index][0] =3D data[1 * width] & 0xff; - s->cam[index][1] =3D data[1 * width] >> 8; - s->cam[index][2] =3D data[2 * width] & 0xff; - s->cam[index][3] =3D data[2 * width] >> 8; - s->cam[index][4] =3D data[3 * width] & 0xff; - s->cam[index][5] =3D data[3 * width] >> 8; + s->cam[index][0] =3D dp8393x_get(s, width, data, 1) & 0xff; + s->cam[index][1] =3D dp8393x_get(s, width, data, 1) >> 8; + s->cam[index][2] =3D dp8393x_get(s, width, data, 2) & 0xff; + s->cam[index][3] =3D dp8393x_get(s, width, data, 2) >> 8; + s->cam[index][4] =3D dp8393x_get(s, width, data, 3) & 0xff; + s->cam[index][5] =3D dp8393x_get(s, width, data, 3) >> 8; DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, s->cam[index][0], s->cam[index][1], s->cam[index][2], s->cam[index][3], s->cam[index][4], s->cam[index][5]); @@ -269,7 +293,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Read CAM enable */ address_space_rw(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CE] =3D data[0 * width]; + s->regs[SONIC_CE] =3D dp8393x_get(s, width, data, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); =20 /* Done */ @@ -290,10 +314,10 @@ static void dp8393x_do_read_rra(dp8393xState *s) MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); =20 /* Update SONIC registers */ - s->regs[SONIC_CRBA0] =3D data[0 * width]; - s->regs[SONIC_CRBA1] =3D data[1 * width]; - s->regs[SONIC_RBWC0] =3D data[2 * width]; - s->regs[SONIC_RBWC1] =3D data[3 * width]; + s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, data, 3); DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); @@ -408,12 +432,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) tx_len =3D 0; =20 /* Update registers */ - s->regs[SONIC_TCR] =3D data[0 * width] & 0xf000; - s->regs[SONIC_TPS] =3D data[1 * width]; - s->regs[SONIC_TFC] =3D data[2 * width]; - s->regs[SONIC_TSA0] =3D data[3 * width]; - s->regs[SONIC_TSA1] =3D data[4 * width]; - s->regs[SONIC_TFS] =3D data[5 * width]; + s->regs[SONIC_TCR] =3D dp8393x_get(s, width, data, 0) & 0xf000; + s->regs[SONIC_TPS] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFC] =3D dp8393x_get(s, width, data, 2); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 3); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 4); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 5); =20 /* Handle programmable interrupt */ if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { @@ -439,9 +463,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * wid= th, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_TSA0] =3D data[0 * width]; - s->regs[SONIC_TSA1] =3D data[1 * width]; - s->regs[SONIC_TFS] =3D data[2 * width]; + s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, data, 0); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, data, 1); + s->regs[SONIC_TFS] =3D dp8393x_get(s, width, data, 2); } } =20 @@ -468,7 +492,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) s->regs[SONIC_TCR] |=3D SONIC_TCR_PTX; =20 /* Write status */ - data[0 * width] =3D s->regs[SONIC_TCR] & 0x0fff; /* status */ + dp8393x_put(s, width, data, 0, + s->regs[SONIC_TCR] & 0x0fff); /* status */ size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_ttda(s), @@ -482,8 +507,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_CTDA] =3D data[0 * width] & ~0x1; - if (data[0 * width] & 0x1) { + s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, data, 0) & ~0x1; + if (dp8393x_get(s, width, data, 0) & 0x1) { /* EOL detected */ break; } @@ -746,7 +771,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, address =3D dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - if (data[0 * width] & 0x1) { + if (dp8393x_get(s, width, data, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; } else { @@ -790,11 +815,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, =20 /* Write status to memory */ DPRINTF("Write status at %08x\n", dp8393x_crda(s)); - data[0 * width] =3D s->regs[SONIC_RCR]; /* status */ - data[1 * width] =3D rx_len; /* byte count */ - data[2 * width] =3D s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ - data[3 * width] =3D s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ - data[4 * width] =3D s->regs[SONIC_RSC]; /* seq_no */ + dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */ + dp8393x_put(s, width, data, 1, rx_len); /* byte count */ + dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ + dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ + dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */ size =3D sizeof(uint16_t) * 5 * width; address_space_rw(&s->as, dp8393x_crda(s), MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); @@ -803,12 +828,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, size =3D sizeof(uint16_t) * width; address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * widt= h, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); - s->regs[SONIC_LLFA] =3D data[0 * width]; + s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, data, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { - data[0 * width] =3D 0; /* in_use */ + dp8393x_put(s, width, data, 0, 0); /* in_use */ address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * = width, MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; @@ -921,6 +946,7 @@ static Property dp8393x_properties[] =3D { DEFINE_NIC_PROPERTIES(dp8393xState, conf), DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), + DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983923; cv=none; d=zoho.com; s=zohoarc; b=XI51lovvNWyrfCwisrr/l+rEkHuAF0wfrJL3hDczFI5YDswjUgnBBxAq5YistFa4Bo3cGEI9sZDUWM+zlE677MfS5BHClnW5KKNGoI71l0OphKuAgb1yhB2X2q1XF+7jjE+egyfSpSTJ5Y8DlXVasC41xEZTrlHxM7SSpUQy9fQ= ARC-Message-Signature: i=1; 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Wed, 19 Jun 2019 18:38:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36168) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdix5-0001yA-LN for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdix1-00082T-QC for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:11 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:55217) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwt-0007pB-1w; Wed, 19 Jun 2019 18:20:59 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MWRi7-1i64f324Md-00Xwdj; Thu, 20 Jun 2019 00:19:55 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:27 +0200 Message-Id: <20190619221933.1981-5-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; 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David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/misc/Kconfig | 4 + hw/misc/Makefile.objs | 1 + hw/misc/mac_via.c | 667 ++++++++++++++++++++++++++++++++++++++ include/hw/misc/mac_via.h | 107 ++++++ 4 files changed, 779 insertions(+) create mode 100644 hw/misc/mac_via.c create mode 100644 include/hw/misc/mac_via.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 385e1b0cec..87312c3abb 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -117,4 +117,8 @@ config AUX bool select I2C =20 +config MAC_VIA + bool + select MOS6522 + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 77b9df9796..ef0d0d5d9b 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -75,6 +75,7 @@ obj-$(CONFIG_ARMSSE_MHU) +=3D armsse-mhu.o obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o +obj-$(CONFIG_MAC_VIA) +=3D mac_via.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o =20 diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c new file mode 100644 index 0000000000..baa87c2879 --- /dev/null +++ b/hw/misc/mac_via.c @@ -0,0 +1,667 @@ +/* + * QEMU m68k Macintosh VIA device support + * + * Copyright (c) 2011-2018 Laurent Vivier + * Copyright (c) 2018 Mark Cave-Ayland + * + * Some parts from hw/misc/macio/cuda.c + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * + * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "hw/misc/mac_via.h" +#include "hw/misc/mos6522.h" +#include "hw/input/adb.h" +#include "sysemu/sysemu.h" +#include "qapi/error.h" +#include "qemu/cutils.h" + + +/* + * VIAs: There are two in every machine, + */ + +#define VIA_SIZE (0x2000) + +/* + * Not all of these are true post MacII I think. + * CSA: probably the ones CHRP marks as 'unused' change purposes + * when the IWM becomes the SWIM. + * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html + * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0= .pdf + * + * also, http://developer.apple.com/technotes/hw/hw_09.html claims the + * following changes for IIfx: + * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. + * Also, "All of the functionality of VIA2 has been moved to other chips". + */ + +#define VIA1A_vSccWrReq 0x80 /* SCC write. (input) + * [CHRP] SCC WREQ: Reflects the state of t= he + * Wait/Request pins from the SCC. + * [Macintosh Family Hardware] + * as CHRP on SE/30,II,IIx,IIcx,IIci. + * on IIfx, "0 means an active request" + */ +#define VIA1A_vRev8 0x40 /* Revision 8 board ??? + * [CHRP] En WaitReqB: Lets the WaitReq_L + * signal from port B of the SCC appear on + * the PA7 input pin. Output. + * [Macintosh Family] On the SE/30, this + * is the bit to flip screen buffers. + * 0=3Dalternate, 1=3Dmain. + * on II,IIx,IIcx,IIci,IIfx this is a bit + * for Rev ID. 0=3DII,IIx, 1=3DIIcx,IIci,II= fx + */ +#define VIA1A_vHeadSel 0x20 /* Head select for IWM. + * [CHRP] unused. + * [Macintosh Family] "Floppy disk + * state-control line SEL" on all but IIfx + */ +#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx + * this bit enables the "Overlay" address + * map in the address decoders as it is on + * reset for mapping the ROM over the reset + * vector. 1=3Duse overlay map. + * On the IIci,IIfx it is another bit of the + * CPU ID: 0=3Dnormal IIci, 1=3DIIci with p= arity + * feature or IIfx. + * [CHRP] En WaitReqA: Lets the WaitReq_L + * signal from port A of the SCC appear + * on the PA7 input pin (CHRP). Output. + * [MkLinux] "Drive Select" + * (with 0x20 being 'disk head select') + */ +#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select: + * 1: select the external serial clock to + * drive the SCC's /RTxCA pin. + * 0: Select the 3.6864MHz clock to drive + * the SCC cell. + * [Macintosh Family] Correct on all but II= fx + */ + +/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control + * on Macs which had the PWM sound hardware. Reserved on newer models. + * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: + * bit 2: 1=3DIIci, 0=3DIIfx + * bit 1: 1 on both IIci and IIfx. + * MkLinux sez bit 0 is 'burnin flag' in this case. + * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as + * inputs, these bits will read 0. + */ +#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ +#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ + +/* Info on VIA1B is from Macintosh Family Hardware & MkLinux. + * CHRP offers no info. */ +#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with + * PWM hardware) 0=3Denabled. + * Also, on IIci w/parity, shows parity err= or + * 0=3Derror, 1=3DOK. */ +#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=3Denabled,1=3D= disabled + * On SE/30, vertical sync interrupt enable. + * 0=3Denabled. This vSync interrupt shows = up + * as a slot $E interrupt. */ +#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ +#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ +#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=3Dinterrupt (unused on I= Ifx)*/ +#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=3Denabled. */ +#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ +#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ + +/* + * VIA2 A register is the interrupt lines raised off the nubus + * slots. + * The below info is from 'Macintosh Family Hardware.' + * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 = irq.' + * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and + * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. + * Perhaps OSS uses vRAM1 and vRAM2 for ADB. + */ + +#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ +#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ= ) */ +#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ +#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ +#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ +#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ +#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ +#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ + +/* RAM size bits decoded as follows: + * bit1 bit0 size of ICs in bank A + * 0 0 256 kbit + * 0 1 1 Mbit + * 1 0 4 Mbit + * 1 1 16 Mbit + */ + +/* + * Register B has the fun stuff in it + */ + +#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by + * timer T1. + * on IIci, parity test: 0=3Dtest mode. + * [MkLinux] RBV_PARODD: 1=3Dodd,0=3Deven. */ +#define VIA2B_vSndJck 0x40 /* External sound jack status. + * 0=3Dplug is inserted. On SE/30, always 0= */ +#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ +#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ +#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush + * on II, AMU/PMMU control. + * if AMU, 0=3D24bit to 32bit translation + * if PMMU, 1=3DPMMU is accessing page tab= le. + * on SE/30 tied low. + * on IIx,IIcx,IIfx, unused. + * on IIci/RBV, cache control. 0=3Dflush cac= he. + */ +#define VIA2B_vPower 0x04 /* Power off, 0=3Dshut off power. + * on SE/30 this signal sent to PDS card. + */ +#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=3Dlocked. + * on SE/30 sent to PDS card. + */ +#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=3Ddisable cache = card + * on others, 0=3Ddisable processor's instruc= tion + * and data caches. + */ + +/* interrupt flags */ + +#define IRQ_SET 0x80 + +/* common */ + +#define VIA_IRQ_TIMER1 0x40 +#define VIA_IRQ_TIMER2 0x20 + +/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html + * Another example of a valid function that has no ROM support is the use + * of the alternate video page for page-flipping animation. Since there + * is no ROM call to flip pages, it is necessary to go play with the + * right bit in the VIA chip (6522 Versatile Interface Adapter). + * [CSA: don't know which one this is, but it's one of 'em!] + */ + +/* + * 6522 registers - see databook. + * CSA: Assignments for VIA1 confirmed from CHRP spec. + */ + +/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ +/* Note: 15 VIA regs, 8 RBV regs */ + +#define vBufB 0x0000 /* [VIA/RBV] Register B */ +#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE= ! */ +#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ +#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ +#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ +#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ +#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ +#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ +#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ +#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ +#define vSR 0x1400 /* [VIA only] Shift register. */ +#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vPCR 0x1800 /* [VIA only] Peripheral control register. */ + /* CHRP sez never ever to *write* this. + * Mac family says never to *change* t= his. + * In fact we need to initialize it once at start. + */ +#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ +#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ +#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ + +/* from linux 2.6 drivers/macintosh/via-macii.c */ + +/* Bits in ACR */ + +#define VIA1ACR_vShiftCtrl 0x1c /* Shift register control b= its */ +#define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock = */ +#define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */ + +/* Apple Macintosh Family Hardware Refenece + * Table 19-10 ADB transaction states + */ + +#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) +#define VIA1B_vADB_StateShift 4 + +#define VIA_TIMER_FREQ (783360) + +/* VIA returns time offset from Jan 1, 1904, not 1970 */ +#define RTC_OFFSET 2082844800 + + +static void via1_VBL(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + s->ifr |=3D VIA1_IRQ_VBLANK; + mdc->update_irq(s); + + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) + / 16630 * 16630); +} + +static void via1_one_second(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + s->ifr |=3D VIA1_IRQ_ONE_SECOND; + mdc->update_irq(s); + + timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + 1000) / 1000 * 1000); +} + +static void via1_irq_request(void *opaque, int irq, int level) +{ + MOS6522Q800VIA1State *v1s =3D opaque; + MOS6522State *s =3D MOS6522(v1s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + + mdc->update_irq(s); +} + +static void via2_irq_request(void *opaque, int irq, int level) +{ + MOS6522Q800VIA2State *v2s =3D opaque; + MOS6522State *s =3D MOS6522(v2s); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(s); + + if (level) { + s->ifr |=3D 1 << irq; + } else { + s->ifr &=3D ~(1 << irq); + } + + mdc->update_irq(s); +} + +static void via1_rtc_update(MacVIAState *m) +{ + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + + if (s->b & VIA1B_vRTCEnb) { + return; + } + + if (s->dirb & VIA1B_vRTCData) { + /* send bits to the RTC */ + if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) { + m->data_out <<=3D 1; + m->data_out |=3D s->b & VIA1B_vRTCData; + m->data_out_cnt++; + } + } else { + /* receive bits from the RTC */ + if ((v1s->last_b & VIA1B_vRTCClk) && + !(s->b & VIA1B_vRTCClk) && + m->data_in_cnt) { + s->b =3D (s->b & ~VIA1B_vRTCData) | + ((m->data_in >> 7) & VIA1B_vRTCData); + m->data_in <<=3D 1; + m->data_in_cnt--; + } + } + + if (m->data_out_cnt =3D=3D 8) { + m->data_out_cnt =3D 0; + + if (m->cmd =3D=3D 0) { + if (m->data_out & 0x80) { + /* this is a read command */ + uint32_t time =3D m->tick_offset + + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + NANOSECONDS_PER_SECOND); + if (m->data_out =3D=3D 0x81) { /* seconds register = 0 */ + m->data_in =3D time & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x85) { /* seconds register = 1 */ + m->data_in =3D (time >> 8) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x89) { /* seconds register = 2 */ + m->data_in =3D (time >> 16) & 0xff; + m->data_in_cnt =3D 8; + } else if (m->data_out =3D=3D 0x8d) { /* seconds register = 3 */ + m->data_in =3D (time >> 24) & 0xff; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->data_out >> 2) & 0x03; + m->data_in =3D v1s->PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->data_out >> 2) & 0x0f; + m->data_in =3D v1s->PRAM[addr]; + m->data_in_cnt =3D 8; + } else if ((m->data_out & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->cmd =3D m->data_out; + } + } else { + /* this is a write command */ + m->cmd =3D m->data_out; + } + } else { + if (m->cmd & 0x80) { + if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->data_out >> 2) & 0x1f; + + m->data_in =3D v1s->PRAM[sector * 8 + addr]; + m->data_in_cnt =3D 8; + } + } else if (!m->wprotect) { + /* this is a write command */ + if (m->alt !=3D 0) { + /* extended memory designator and sector number */ + int sector =3D m->cmd & 0x07; + int addr =3D (m->alt >> 2) & 0x1f; + + v1s->PRAM[sector * 8 + addr] =3D m->data_out; + + m->alt =3D 0; + } else if (m->cmd =3D=3D 0x01) { /* seconds register 0 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x05) { /* seconds register 1 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x09) { /* seconds register 2 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x0d) { /* seconds register 3 */ + /* FIXME */ + } else if (m->cmd =3D=3D 0x31) { + /* Test Register */ + } else if (m->cmd =3D=3D 0x35) { + /* Write Protect register */ + m->wprotect =3D m->data_out & 1; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x10 -> 0x13 */ + int addr =3D (m->cmd >> 2) & 0x03; + v1s->PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf3) =3D=3D 0xa1) { + /* PRAM address 0x00 -> 0x0f */ + int addr =3D (m->cmd >> 2) & 0x0f; + v1s->PRAM[addr] =3D m->data_out; + } else if ((m->cmd & 0xf8) =3D=3D 0xb8) { + /* extended memory designator and sector number */ + m->alt =3D m->cmd; + } + } + } + m->data_out =3D 0; + } +} + +static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned= size) +{ + MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + return mos6522_read(ms, addr, size); +} + +static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + mos6522_write(ms, addr, val, size); +} + +static const MemoryRegionOps mos6522_q800_via1_ops =3D { + .read =3D mos6522_q800_via1_read, + .write =3D mos6522_q800_via1_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned= size) +{ + MOS6522Q800VIA2State *s =3D MOS6522_Q800_VIA2(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + return mos6522_read(ms, addr, size); +} + +static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + MOS6522Q800VIA2State *s =3D MOS6522_Q800_VIA2(opaque); + MOS6522State *ms =3D MOS6522(s); + + addr =3D (addr >> 9) & 0xf; + mos6522_write(ms, addr, val, size); +} + +static const MemoryRegionOps mos6522_q800_via2_ops =3D { + .read =3D mos6522_q800_via2_read, + .write =3D mos6522_q800_via2_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void mac_via_reset(DeviceState *dev) +{ + MacVIAState *m =3D MAC_VIA(dev); + + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) + / 16630 * 16630); + + timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + 1000) / 1000 * 1000); +} + +static void mac_via_realize(DeviceState *dev, Error **errp) +{ + MacVIAState *m =3D MAC_VIA(dev); + MOS6522State *ms; + struct tm tm; + + /* Init VIAs 1 and 2 */ + sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1, + sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1); + + sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2, + sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2); + + /* Pass through mos6522 output IRQs */ + ms =3D MOS6522(&m->mos6522_via1); + object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + ms =3D MOS6522(&m->mos6522_via2); + object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), + SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort); + + /* Pass through mos6522 input IRQs */ + qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq"); + qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq"); + + /* VIA 1 */ + m->one_second_timer =3D timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_seco= nd, m); + m->VBL_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_VBL, m); + + qemu_get_timedate(&tm, 0); + m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; +} + +static void mac_via_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + MacVIAState *m =3D MAC_VIA(obj); + + /* MMIO */ + memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE); + sysbus_init_mmio(sbd, &m->mmio); + + memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops, + &m->mos6522_via1, "via1", VIA_SIZE); + memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem); + + memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops, + &m->mos6522_via2, "via2", VIA_SIZE); + memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem); + + /* ADB */ + qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus), + TYPE_ADB_BUS, DEVICE(obj), "adb.0"); +} + +static void mac_via_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mac_via_realize; + dc->reset =3D mac_via_reset; +} + +static TypeInfo mac_via_info =3D { + .name =3D TYPE_MAC_VIA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacVIAState), + .instance_init =3D mac_via_init, + .class_init =3D mac_via_class_init, +}; + +/* VIA 1 */ +static void mos6522_q800_via1_portB_write(MOS6522State *s) +{ + MOS6522Q800VIA1State *v1s =3D container_of(s, MOS6522Q800VIA1State, + parent_obj); + MacVIAState *m =3D container_of(v1s, MacVIAState, mos6522_via1); + + via1_rtc_update(m); + + v1s->last_b =3D s->b; +} + +static void mos6522_q800_via1_reset(DeviceState *dev) +{ + MOS6522State *ms =3D MOS6522(dev); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); + + mdc->parent_reset(dev); + + ms->timers[0].frequency =3D VIA_TIMER_FREQ; + ms->timers[1].frequency =3D VIA_TIMER_FREQ; + + ms->b =3D VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb; +} + +static void mos6522_q800_via1_init(Object *obj) +{ + qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq", + VIA1_IRQ_NB); +} + +static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->reset =3D mos6522_q800_via1_reset; + mdc->portB_write =3D mos6522_q800_via1_portB_write; +} + +static const TypeInfo mos6522_q800_via1_type_info =3D { + .name =3D TYPE_MOS6522_Q800_VIA1, + .parent =3D TYPE_MOS6522, + .instance_size =3D sizeof(MOS6522Q800VIA1State), + .instance_init =3D mos6522_q800_via1_init, + .class_init =3D mos6522_q800_via1_class_init, +}; + +/* VIA 2 */ +static void mos6522_q800_via2_portB_write(MOS6522State *s) +{ + if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) =3D=3D 0) { + /* shutdown */ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void mos6522_q800_via2_reset(DeviceState *dev) +{ + MOS6522State *ms =3D MOS6522(dev); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_GET_CLASS(ms); + + mdc->parent_reset(dev); + + ms->timers[0].frequency =3D VIA_TIMER_FREQ; + ms->timers[1].frequency =3D VIA_TIMER_FREQ; + + ms->dirb =3D 0; + ms->b =3D 0; +} + +static void mos6522_q800_via2_init(Object *obj) +{ + qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq", + VIA2_IRQ_NB); +} + +static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc =3D MOS6522_DEVICE_CLASS(oc); + + dc->reset =3D mos6522_q800_via2_reset; + mdc->portB_write =3D mos6522_q800_via2_portB_write; +} + +static const TypeInfo mos6522_q800_via2_type_info =3D { + .name =3D TYPE_MOS6522_Q800_VIA2, + .parent =3D TYPE_MOS6522, + .instance_size =3D sizeof(MOS6522Q800VIA2State), + .instance_init =3D mos6522_q800_via2_init, + .class_init =3D mos6522_q800_via2_class_init, +}; + +static void mac_via_register_types(void) +{ + type_register_static(&mos6522_q800_via1_type_info); + type_register_static(&mos6522_q800_via2_type_info); + type_register_static(&mac_via_info); +} + +type_init(mac_via_register_types); diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h new file mode 100644 index 0000000000..69bdecabb0 --- /dev/null +++ b/include/hw/misc/mac_via.h @@ -0,0 +1,107 @@ +/* + * + * Copyright (c) 2011-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_MISC_MAC_VIA_H +#define HW_MISC_MAC_VIA_H + +#include "exec/memory.h" +#include "hw/sysbus.h" +#include "hw/misc/mos6522.h" + + +/* VIA 1 */ +#define VIA1_IRQ_ONE_SECOND_BIT 0 +#define VIA1_IRQ_VBLANK_BIT 1 +#define VIA1_IRQ_ADB_READY_BIT 2 +#define VIA1_IRQ_ADB_DATA_BIT 3 +#define VIA1_IRQ_ADB_CLOCK_BIT 4 + +#define VIA1_IRQ_NB 8 + +#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT) +#define VIA1_IRQ_VBLANK (1 << VIA1_IRQ_VBLANK_BIT) +#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT) +#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT) +#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT) + + +#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1" +#define MOS6522_Q800_VIA1(obj) OBJECT_CHECK(MOS6522Q800VIA1State, (obj), \ + TYPE_MOS6522_Q800_VIA1) + +typedef struct MOS6522Q800VIA1State { + /*< private >*/ + MOS6522State parent_obj; + + qemu_irq irqs[VIA1_IRQ_NB]; + uint8_t last_b; + uint8_t PRAM[256]; +} MOS6522Q800VIA1State; + + +/* VIA 2 */ +#define VIA2_IRQ_SCSI_DATA_BIT 0 +#define VIA2_IRQ_SLOT_BIT 1 +#define VIA2_IRQ_UNUSED_BIT 2 +#define VIA2_IRQ_SCSI_BIT 3 +#define VIA2_IRQ_ASC_BIT 4 + +#define VIA2_IRQ_NB 8 + +#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT) +#define VIA2_IRQ_SLOT (1 << VIA2_IRQ_SLOT_BIT) +#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT) +#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT) +#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT) + +#define TYPE_MOS6522_Q800_VIA2 "mos6522-q800-via2" +#define MOS6522_Q800_VIA2(obj) OBJECT_CHECK(MOS6522Q800VIA2State, (obj), \ + TYPE_MOS6522_Q800_VIA2) + +typedef struct MOS6522Q800VIA2State { + /*< private >*/ + MOS6522State parent_obj; +} MOS6522Q800VIA2State; + + +#define TYPE_MAC_VIA "mac_via" +#define MAC_VIA(obj) OBJECT_CHECK(MacVIAState, (obj), TYPE_MAC_VIA) + +typedef struct MacVIAState { + SysBusDevice busdev; + + /* MMIO */ + MemoryRegion mmio; + MemoryRegion via1mem; + MemoryRegion via2mem; + + /* VIAs */ + MOS6522Q800VIA1State mos6522_via1; + MOS6522Q800VIA2State mos6522_via2; + + /* RTC */ + uint32_t tick_offset; + + uint8_t data_out; + int data_out_cnt; + uint8_t data_in; + uint8_t data_in_cnt; + uint8_t cmd; + int wprotect; + int alt; + + /* ADB */ + ADBBusState adb_bus; + + /* external timers */ + QEMUTimer *one_second_timer; + QEMUTimer *VBL_timer; + +} MacVIAState; + +#endif --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983347; cv=none; d=zoho.com; s=zohoarc; b=cKAm4N/18yyGQ6fisEVSkQmwkeAfaM1DWnZDAOJjwDEc108Xi6FFCZ9L5C2el/7pVXIuYBailKAcVsaxo0G3yDwsnZDOA1J4BLGDRpNqT9JMhy+w5gQZ8Ufb/zxLyG8bjgCqy62TODjXI4Pl1tdw/cvcFS8KB0sgRKDpC1QiE/Q= ARC-Message-Signature: i=1; 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Wed, 19 Jun 2019 18:28:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36069) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdiwu-0001lS-Ul for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdiwt-0007qL-A8 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:00 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:48353) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwp-0007jo-Rh; Wed, 19 Jun 2019 18:20:56 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N6sSV-1igEMN0WAJ-018Nv1; Thu, 20 Jun 2019 00:19:56 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:28 +0200 Message-Id: <20190619221933.1981-6-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:BBoTL/ECTKIHx5+KQHuigAZ+malLinV2NbOCLmG7YQVSLP8Onln IFmWfIaF4TX4SGe2M534z8+pCaOswCVXkLNRPyQdoAoXY9nnX1Gr0FxcRI3fY53R9jBPkvC iAF07KjZqkMbWuTSnMKkuCftRrAnv9rM7GYzin3sMz1AyaFtv4gNw65GD4gHNqVP2HKfHrV VK4aMVXWXx1/InnLq1KhA== X-UI-Out-Filterresults: notjunk:1;V03:K0:C+CSz9wy2tw=:zk6lLzlfSZj3H2P4TBo6a3 rzEcXsZqqTNYgop9L7gqgCcUnSjPWkUUyTrcMk8vJkG1A25oNJRp28MJYenXvMYvyYAmnrQpQ WUmOH3jh69FkSaG6kYvMIrA90k/SX7or3/lR2b7qUEVrvU+DLJohIt3HYOzSyprIupsBQqIRr WiCcpBemrss0oLzsMH6hRKzJF8bs2Q+DKyFLlwq0v3XesGFnaIXto8nQw0ih3BuVGZhkLAt14 fLW94eY3R+spOzUmo553I+3ejeKihvn2DdRFP209h4qQTif08//jaWmZ9p4ubGfrmk5zuQFfg fFWYR0MtcGKGHAGg331kXhkbQEX5qq+i2K+UDhOhtw0Um3Sf6WbE1ioobw+38bAqslAmwKFU5 ov5nQfMVRB6xgb8Rb04Im5yhtTgJKAzrPpjHHL9ho40l79/uysfH1/aIPjWUrETFb/QrJvs40 BCG4YNr6oed3qS+IFyiUAzr2k+HI0S1KLSCabB+qQ2PAXPBOOpOKd+8M4ku3NAJ518YSr61Aq FdcrIk6MeTRfeS2wHfTe7W/0yo5JDKebowS3zI+ttmzwIzHxzH4neHN/S836o2WOpleXQEi/b 7YYTbDOeEpxM7Jp0ItVV57ZKXTTU62DXWcyenkYatpQcxRPa1D2iL8MgMDrPVSROK+YLCNqK0 x6v9/OwUp8Mhgij9O/4uKu8PDKTix2gJYjQ1rhQzdhYNP8TaSgJRiK2I5fHhRG4NIa/xiwOVI cmFbK4XKciBRifni8RiwtOdY0DVMnm4czkzJ2hSlo39C8WDqfuewlnvi9pQ= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v8 05/10] hw/m68k: implement ADB bus support for via X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau Reviewed-by: Thomas Huth --- hw/misc/mac_via.c | 190 ++++++++++++++++++++++++++++++++++++++ include/hw/misc/mac_via.h | 7 ++ 2 files changed, 197 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index baa87c2879..4249632a57 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -238,10 +238,16 @@ * Table 19-10 ADB transaction states */ =20 +#define ADB_STATE_NEW 0 +#define ADB_STATE_EVEN 1 +#define ADB_STATE_ODD 2 +#define ADB_STATE_IDLE 3 + #define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2) #define VIA1B_vADB_StateShift 4 =20 #define VIA_TIMER_FREQ (783360) +#define VIA_ADB_POLL_FREQ 50 /* XXX: not real */ =20 /* VIA returns time offset from Jan 1, 1904, not 1970 */ #define RTC_OFFSET 2082844800 @@ -423,6 +429,181 @@ static void via1_rtc_update(MacVIAState *m) } } =20 +static int adb_via_poll(MacVIAState *s, int state, uint8_t *data) +{ + if (state !=3D ADB_STATE_IDLE) { + return 0; + } + + if (s->adb_data_in_size < s->adb_data_in_index) { + return 0; + } + + if (s->adb_data_out_index !=3D 0) { + return 0; + } + + s->adb_data_in_index =3D 0; + s->adb_data_out_index =3D 0; + s->adb_data_in_size =3D adb_poll(&s->adb_bus, s->adb_data_in, 0xffff); + + if (s->adb_data_in_size) { + *data =3D s->adb_data_in[s->adb_data_in_index++]; + qemu_irq_raise(s->adb_data_ready); + } + + return s->adb_data_in_size; +} + +static int adb_via_send(MacVIAState *s, int state, uint8_t data) +{ + switch (state) { + case ADB_STATE_NEW: + s->adb_data_out_index =3D 0; + break; + case ADB_STATE_EVEN: + if ((s->adb_data_out_index & 1) =3D=3D 0) { + return 0; + } + break; + case ADB_STATE_ODD: + if (s->adb_data_out_index & 1) { + return 0; + } + break; + case ADB_STATE_IDLE: + return 0; + } + + assert(s->adb_data_out_index < sizeof(s->adb_data_out) - 1); + + s->adb_data_out[s->adb_data_out_index++] =3D data; + qemu_irq_raise(s->adb_data_ready); + return 1; +} + +static int adb_via_receive(MacVIAState *s, int state, uint8_t *data) +{ + switch (state) { + case ADB_STATE_NEW: + return 0; + + case ADB_STATE_EVEN: + if (s->adb_data_in_size <=3D 0) { + qemu_irq_raise(s->adb_data_ready); + return 0; + } + + if (s->adb_data_in_index >=3D s->adb_data_in_size) { + *data =3D 0; + qemu_irq_raise(s->adb_data_ready); + return 1; + } + + if ((s->adb_data_in_index & 1) =3D=3D 0) { + return 0; + } + + break; + + case ADB_STATE_ODD: + if (s->adb_data_in_size <=3D 0) { + qemu_irq_raise(s->adb_data_ready); + return 0; + } + + if (s->adb_data_in_index >=3D s->adb_data_in_size) { + *data =3D 0; + qemu_irq_raise(s->adb_data_ready); + return 1; + } + + if (s->adb_data_in_index & 1) { + return 0; + } + + break; + + case ADB_STATE_IDLE: + if (s->adb_data_out_index =3D=3D 0) { + return 0; + } + + s->adb_data_in_size =3D adb_request(&s->adb_bus, s->adb_data_in, + s->adb_data_out, + s->adb_data_out_index); + s->adb_data_out_index =3D 0; + s->adb_data_in_index =3D 0; + if (s->adb_data_in_size < 0) { + *data =3D 0xff; + qemu_irq_raise(s->adb_data_ready); + return -1; + } + + if (s->adb_data_in_size =3D=3D 0) { + return 0; + } + + break; + } + + assert(s->adb_data_in_index < sizeof(s->adb_data_in) - 1); + + *data =3D s->adb_data_in[s->adb_data_in_index++]; + qemu_irq_raise(s->adb_data_ready); + if (*data =3D=3D 0xff || *data =3D=3D 0) { + return 0; + } + return 1; +} + +static void via1_adb_update(MacVIAState *m) +{ + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + int state; + int ret; + + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + + if (s->acr & VIA1ACR_vShiftOut) { + /* output mode */ + ret =3D adb_via_send(m, state, s->sr); + if (ret > 0) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } else { + /* input mode */ + ret =3D adb_via_receive(m, state, &s->sr); + if (ret > 0 && s->sr !=3D 0xff) { + s->b &=3D ~VIA1B_vADBInt; + } else { + s->b |=3D VIA1B_vADBInt; + } + } +} + +static void via_adb_poll(void *opaque) +{ + MacVIAState *m =3D opaque; + MOS6522Q800VIA1State *v1s =3D MOS6522_Q800_VIA1(&m->mos6522_via1); + MOS6522State *s =3D MOS6522(v1s); + int state; + + if (s->b & VIA1B_vADBInt) { + state =3D (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + if (adb_via_poll(m, state, &s->sr)) { + s->b &=3D ~VIA1B_vADBInt; + } + } + + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); +} + static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned= size) { MOS6522Q800VIA1State *s =3D MOS6522_Q800_VIA1(opaque); @@ -485,6 +666,10 @@ static void mac_via_reset(DeviceState *dev) { MacVIAState *m =3D MAC_VIA(dev); =20 + timer_mod(m->adb_poll_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ)); + timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630) / 16630 * 16630); =20 @@ -523,6 +708,10 @@ static void mac_via_realize(DeviceState *dev, Error **= errp) =20 qemu_get_timedate(&tm, 0); m->tick_offset =3D (uint32_t)mktimegm(&tm) + RTC_OFFSET; + + m->adb_poll_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, via_adb_poll, m= ); + m->adb_data_ready =3D qdev_get_gpio_in_named(dev, "via1-irq", + VIA1_IRQ_ADB_READY_BIT); } =20 static void mac_via_init(Object *obj) @@ -571,6 +760,7 @@ static void mos6522_q800_via1_portB_write(MOS6522State = *s) MacVIAState *m =3D container_of(v1s, MacVIAState, mos6522_via1); =20 via1_rtc_update(m); + via1_adb_update(m); =20 v1s->last_b =3D s->b; } diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 69bdecabb0..2181140293 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -97,6 +97,13 @@ typedef struct MacVIAState { =20 /* ADB */ ADBBusState adb_bus; + QEMUTimer *adb_poll_timer; + qemu_irq adb_data_ready; + int adb_data_in_size; + int adb_data_in_index; + int adb_data_out_index; + uint8_t adb_data_in[128]; + uint8_t adb_data_out[16]; =20 /* external timers */ QEMUTimer *one_second_timer; --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 19 Jun 2019 18:20:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MQNAv-1i032q1P3x-00MMqL; Thu, 20 Jun 2019 00:19:57 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:29 +0200 Message-Id: <20190619221933.1981-7-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:DJzWu//Mzz/9CMKkjUmi8T0DQ7iVnl/VcL1pGG7NReDS2LHHM0q q7/CoPaIgb0ZLg+FSizV31GnjpOx5eM1Izg92YHPdCqIv6dAalWd7Z7uuDg0hKYCv88oFyn CuPsBImS6o6QE7hiNTX9ITQwgKRAEs06Q4efK+Qvp6rpKeHu9uPWxFWoOBPmucPtjx0RXHs JMnDav3gknA3oNN19VkRA== X-UI-Out-Filterresults: notjunk:1;V03:K0:NoIcE+jYajc=:e9KHh88Gt64wXpy+kfLH84 gEybGQgOs0wy4dmclBysuLTFfoY3Ecjqjxw8tF5Ikqw6ybdYY/OJJ7OckQNwcLEFj+ckTnSvu T+jg4qFVsyMtVC18pacREVoI03ZvQ5CwB73v1TxcWRngJdGrTAXGQePC7xNR4L3/XUO+po3p6 bIBHvHHu45mrh+zSPEW8am1RHNSCErqF25gVbLhzbTmrqovkv+DIeYuQafVAUpqhqcj5fGjXN FsuVY0Ps2sa8zJ7205NWFaGV8vCWsAyn9P7iHsHtUL4/svjEJdPoYv8tXPSOfHTnZrWwnrjyS dYC2rnOGi3c5A40AT5MmL7N7z4nV7V/GfnSlG2GsB4srclTKp3iouGZSin9d4j+YitzysEhhY IWnZ96BLOtv3whQ0FAXcFJ6fS99ZyWANQbNkeFThNmJ3K69Qf/GqbRIO+g36YL7XglsShe8RE ilDiZhpMuUUsFqX6noImggGM4iieC8Q9LPaWQduuoVtMy0ofVn2bDCZC5xRbMGvijCA7Kzhjv 5x1LitUb8I8yc9XeZmo2lMh4RnSKdv97gEznDHqTHqEkVzKp7MQVOqyWmGstwIZmNNSeOVHky v7bN7wvbbiY0u+mX5MAjsjZNcZLuvONCGxeia/x4LZzu4o6EaBdCzinraAZJR86svnmu0wLMD nEUjpqXjpBnsmqkY2rtWL47yPflqDdEQtODvP1ghZaHLUjBOt+bS2EyGOGzsuVdy3PZg6bocv D+BdavBhnjey85XeVIytZWRGD/3oKbKZfr2g8HlcDmYz9vyHiGTsziLcP6s= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH v8 06/10] hw/m68k: add macfb video card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau Reviewed-by: Thomas Huth --- arch_init.c | 4 + hw/display/Kconfig | 3 + hw/display/Makefile.objs | 1 + hw/display/macfb.c | 419 +++++++++++++++++++++++++++++++++++++ include/hw/display/macfb.h | 43 ++++ qemu-options.hx | 2 +- vl.c | 3 +- 7 files changed, 473 insertions(+), 2 deletions(-) create mode 100644 hw/display/macfb.c create mode 100644 include/hw/display/macfb.h diff --git a/arch_init.c b/arch_init.c index 74b0708634..9e04cfb581 100644 --- a/arch_init.c +++ b/arch_init.c @@ -38,6 +38,10 @@ int graphic_width =3D 1024; int graphic_height =3D 768; int graphic_depth =3D 8; +#elif defined(TARGET_M68K) +int graphic_width =3D 800; +int graphic_height =3D 600; +int graphic_depth =3D 8; #else int graphic_width =3D 800; int graphic_height =3D 600; diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 910dccb2f7..035cd85bcf 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -130,3 +130,6 @@ config ATI_VGA default y if PCI_DEVICES depends on PCI select VGA + +config MACFB + bool diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index a64998fc7b..2a26709e9e 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -26,6 +26,7 @@ common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o common-obj-$(CONFIG_FRAMEBUFFER) +=3D framebuffer.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-vgafb.o common-obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o +common-obj-$(CONFIG_MACFB) +=3D macfb.o =20 obj-$(CONFIG_MILKYMIST_TMU2) +=3D milkymist-tmu2.o milkymist-tmu2.o-cflags :=3D $(X11_CFLAGS) $(OPENGL_CFLAGS) diff --git a/hw/display/macfb.c b/hw/display/macfb.c new file mode 100644 index 0000000000..61ba2e9e15 --- /dev/null +++ b/hw/display/macfb.c @@ -0,0 +1,419 @@ +/* + * QEMU Motorola 680x0 Macintosh Video Card Emulation + * Copyright (c) 2012-2018 Laurent Vivier + * + * some parts from QEMU G364 framebuffer Emulator. + * Copyright (c) 2007-2011 Herve Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "ui/console.h" +#include "ui/pixel_ops.h" +#include "hw/display/macfb.h" +#include "qapi/error.h" + +#define VIDEO_BASE 0x00001000 +#define DAFB_BASE 0x00800000 + +#define MACFB_PAGE_SIZE 4096 +#define MACFB_VRAM_SIZE (4 * MiB) + +#define DAFB_RESET 0x200 +#define DAFB_LUT 0x213 + + +typedef void macfb_draw_line_func(MacfbState *s, uint8_t *d, uint32_t addr, + int width); + +static inline uint8_t macfb_read_byte(MacfbState *s, uint32_t addr) +{ + return s->vram[addr & s->vram_bit_mask]; +} + +/* 1-bit color */ +static void macfb_draw_line1(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D x & 7; + int idx =3D (macfb_read_byte(s, addr) >> (7 - bit)) & 1; + r =3D g =3D b =3D ((1 - idx) << 7); + addr +=3D (bit =3D=3D 7); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 2-bit color */ +static void macfb_draw_line2(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D (x & 3); + int idx =3D (macfb_read_byte(s, addr) >> ((3 - bit) << 1)) & 3; + r =3D s->color_palette[idx * 3]; + g =3D s->color_palette[idx * 3 + 1]; + b =3D s->color_palette[idx * 3 + 2]; + addr +=3D (bit =3D=3D 3); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 4-bit color */ +static void macfb_draw_line4(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + int bit =3D x & 1; + int idx =3D (macfb_read_byte(s, addr) >> ((1 - bit) << 2)) & 15; + r =3D s->color_palette[idx * 3]; + g =3D s->color_palette[idx * 3 + 1]; + b =3D s->color_palette[idx * 3 + 2]; + addr +=3D (bit =3D=3D 1); + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 8-bit color */ +static void macfb_draw_line8(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + r =3D s->color_palette[macfb_read_byte(s, addr) * 3]; + g =3D s->color_palette[macfb_read_byte(s, addr) * 3 + 1]; + b =3D s->color_palette[macfb_read_byte(s, addr) * 3 + 2]; + addr++; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 16-bit color */ +static void macfb_draw_line16(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + uint16_t pixel; + pixel =3D (macfb_read_byte(s, addr) << 8) | macfb_read_byte(s, add= r + 1); + r =3D ((pixel >> 10) & 0x1f) << 3; + g =3D ((pixel >> 5) & 0x1f) << 3; + b =3D (pixel & 0x1f) << 3; + addr +=3D 2; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + +/* 24-bit color */ +static void macfb_draw_line24(MacfbState *s, uint8_t *d, uint32_t addr, + int width) +{ + uint8_t r, g, b; + int x; + + for (x =3D 0; x < width; x++) { + r =3D macfb_read_byte(s, addr); + g =3D macfb_read_byte(s, addr + 1); + b =3D macfb_read_byte(s, addr + 2); + addr +=3D 3; + + *(uint32_t *)d =3D rgb_to_pixel32(r, g, b); + d +=3D 4; + } +} + + +enum { + MACFB_DRAW_LINE1, + MACFB_DRAW_LINE2, + MACFB_DRAW_LINE4, + MACFB_DRAW_LINE8, + MACFB_DRAW_LINE16, + MACFB_DRAW_LINE24, + MACFB_DRAW_LINE_NB, +}; + +static macfb_draw_line_func * const + macfb_draw_line_table[MACFB_DRAW_LINE_NB] = =3D { + macfb_draw_line1, + macfb_draw_line2, + macfb_draw_line4, + macfb_draw_line8, + macfb_draw_line16, + macfb_draw_line24, +}; + +static int macfb_check_dirty(MacfbState *s, DirtyBitmapSnapshot *snap, + ram_addr_t addr, int len) +{ + return memory_region_snapshot_get_dirty(&s->mem_vram, snap, addr, len); +} + +static void macfb_draw_graphic(MacfbState *s) +{ + DisplaySurface *surface =3D qemu_console_surface(s->con); + DirtyBitmapSnapshot *snap =3D NULL; + ram_addr_t page; + uint32_t v =3D 0; + int y, ymin; + int macfb_stride =3D (s->depth * s->width + 7) / 8; + macfb_draw_line_func *macfb_draw_line; + + switch (s->depth) { + case 1: + v =3D MACFB_DRAW_LINE1; + break; + case 2: + v =3D MACFB_DRAW_LINE2; + break; + case 4: + v =3D MACFB_DRAW_LINE4; + break; + case 8: + v =3D MACFB_DRAW_LINE8; + break; + case 16: + v =3D MACFB_DRAW_LINE16; + break; + case 24: + v =3D MACFB_DRAW_LINE24; + break; + } + + macfb_draw_line =3D macfb_draw_line_table[v]; + assert(macfb_draw_line !=3D NULL); + + snap =3D memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0x0, + memory_region_size(&s->mem_vr= am), + DIRTY_MEMORY_VGA); + + ymin =3D -1; + page =3D 0; + for (y =3D 0; y < s->height; y++, page +=3D macfb_stride) { + if (macfb_check_dirty(s, snap, page, macfb_stride)) { + uint8_t *data_display; + + data_display =3D surface_data(surface) + y * surface_stride(su= rface); + macfb_draw_line(s, data_display, page, s->width); + + if (ymin < 0) { + ymin =3D y; + } + } else { + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + ymin =3D -1; + } + } + } + + if (ymin >=3D 0) { + dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin); + } + + g_free(snap); +} + +static void macfb_invalidate_display(void *opaque) +{ + MacfbState *s =3D opaque; + + memory_region_set_dirty(&s->mem_vram, 0, MACFB_VRAM_SIZE); +} + +static void macfb_update_display(void *opaque) +{ + MacfbState *s =3D opaque; + DisplaySurface *surface =3D qemu_console_surface(s->con); + + qemu_flush_coalesced_mmio_buffer(); + + if (s->width =3D=3D 0 || s->height =3D=3D 0) { + return; + } + + if (s->width !=3D surface_width(surface) || + s->height !=3D surface_height(surface)) { + qemu_console_resize(s->con, s->width, s->height); + } + + macfb_draw_graphic(s); +} + +static void macfb_reset(MacfbState *s) +{ + int i; + + s->palette_current =3D 0; + for (i =3D 0; i < 256; i++) { + s->color_palette[i * 3] =3D 255 - i; + s->color_palette[i * 3 + 1] =3D 255 - i; + s->color_palette[i * 3 + 2] =3D 255 - i; + } + memset(s->vram, 0, MACFB_VRAM_SIZE); + macfb_invalidate_display(s); +} + +static uint64_t macfb_ctrl_read(void *opaque, + hwaddr addr, + unsigned int size) +{ + return 0; +} + +static void macfb_ctrl_write(void *opaque, + hwaddr addr, + uint64_t val, + unsigned int size) +{ + MacfbState *s =3D opaque; + switch (addr) { + case DAFB_RESET: + s->palette_current =3D 0; + break; + case DAFB_LUT: + s->color_palette[s->palette_current++] =3D val; + if (s->palette_current % 3) { + macfb_invalidate_display(s); + } + break; + } +} + +static const MemoryRegionOps macfb_ctrl_ops =3D { + .read =3D macfb_ctrl_read, + .write =3D macfb_ctrl_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, +}; + +static int macfb_post_load(void *opaque, int version_id) +{ + macfb_invalidate_display(opaque); + return 0; +} + +static const VMStateDescription vmstate_macfb =3D { + .name =3D "macfb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .minimum_version_id_old =3D 1, + .post_load =3D macfb_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(color_palette, MacfbState, 256 * 3), + VMSTATE_UINT32(palette_current, MacfbState), + VMSTATE_END_OF_LIST() + } +}; + +static const GraphicHwOps macfb_ops =3D { + .invalidate =3D macfb_invalidate_display, + .gfx_update =3D macfb_update_display, +}; + +static void macfb_common_realize(DeviceState *dev, MacfbState *s, Error **= errp) +{ + DisplaySurface *surface; + + if (s->depth !=3D 1 && s->depth !=3D 2 && s->depth !=3D 4 && s->depth = !=3D 8 && + s->depth !=3D 16 && s->depth !=3D 24) { + error_setg(errp, "unknown guest depth %d", s->depth); + return; + } + + s->con =3D graphic_console_init(dev, 0, &macfb_ops, s); + surface =3D qemu_console_surface(s->con); + + if (surface_bits_per_pixel(surface) !=3D 32) { + error_setg(errp, "unknown host depth %d", + surface_bits_per_pixel(surface)); + return; + } + + memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "macfb-c= trl", + 0x1000); + + memory_region_init_ram_nomigrate(&s->mem_vram, OBJECT(s), "macfb-vram", + MACFB_VRAM_SIZE, errp); + s->vram =3D memory_region_get_ram_ptr(&s->mem_vram); + s->vram_bit_mask =3D MACFB_VRAM_SIZE - 1; + vmstate_register_ram(&s->mem_vram, dev); + memory_region_set_coalescing(&s->mem_vram); +} + +static void macfb_sysbus_realize(DeviceState *dev, Error **errp) +{ + MacfbSysBusState *s =3D MACFB(dev); + MacfbState *ms =3D &s->macfb; + + macfb_common_realize(dev, ms, errp); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_ctrl); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram); +} + +static void macfb_sysbus_reset(DeviceState *d) +{ + MacfbSysBusState *s =3D MACFB(d); + macfb_reset(&s->macfb); +} + +static Property macfb_sysbus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbSysBusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + +static void macfb_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D macfb_sysbus_realize; + dc->desc =3D "SysBus Macintosh framebuffer"; + dc->reset =3D macfb_sysbus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_sysbus_properties; +} + +static TypeInfo macfb_sysbus_info =3D { + .name =3D TYPE_MACFB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MacfbSysBusState), + .class_init =3D macfb_sysbus_class_init, +}; + +static void macfb_register_types(void) +{ + type_register_static(&macfb_sysbus_info); +} + +type_init(macfb_register_types) diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h new file mode 100644 index 0000000000..3fe2592735 --- /dev/null +++ b/include/hw/display/macfb.h @@ -0,0 +1,43 @@ +/* + * QEMU Motorola 680x0 Macintosh Video Card Emulation + * Copyright (c) 2012-2018 Laurent Vivier + * + * some parts from QEMU G364 framebuffer Emulator. + * Copyright (c) 2007-2011 Herve Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef MACFB_H +#define MACFB_H + +#include "qemu/osdep.h" +#include "exec/memory.h" +#include "ui/console.h" + +typedef struct MacfbState { + MemoryRegion mem_vram; + MemoryRegion mem_ctrl; + QemuConsole *con; + + uint8_t *vram; + uint32_t vram_bit_mask; + uint32_t palette_current; + uint8_t color_palette[256 * 3]; + uint32_t width, height; /* in pixels */ + uint8_t depth; +} MacfbState; + +#define TYPE_MACFB "sysbus-macfb" +#define MACFB(obj) \ + OBJECT_CHECK(MacfbSysBusState, (obj), TYPE_MACFB) + +typedef struct { + SysBusDevice busdev; + + MacfbState macfb; +} MacfbSysBusState; + +#endif diff --git a/qemu-options.hx b/qemu-options.hx index 0d8beb4afd..bf842c539a 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1794,7 +1794,7 @@ ETEXI =20 DEF("g", 1, QEMU_OPTION_g , "-g WxH[xDEPTH] Set the initial graphical resolution and depth\n", - QEMU_ARCH_PPC | QEMU_ARCH_SPARC) + QEMU_ARCH_PPC | QEMU_ARCH_SPARC | QEMU_ARCH_M68K) STEXI @item -g @var{width}x@var{height}[x@var{depth}] @findex -g diff --git a/vl.c b/vl.c index 99a56b5556..770a1ee435 100644 --- a/vl.c +++ b/vl.c @@ -3332,7 +3332,8 @@ int main(int argc, char **argv, char **envp) if (*p =3D=3D 'x') { p++; depth =3D strtol(p, (char **)&p, 10); - if (depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && + if (depth !=3D 1 && depth !=3D 2 && depth !=3D 4 && + depth !=3D 8 && depth !=3D 15 && depth !=3D 16= && depth !=3D 24 && depth !=3D 32) goto graphic_error; } else if (*p =3D=3D '\0') { --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983171; cv=none; d=zoho.com; s=zohoarc; b=WF6VMITn2j38jz10enFsRNtpJnpvky2Ga0MuXx0BoYs9MQI7njLNN+0xxnot+zQ7HUQnJvf8AD0fyKssppnDWxc06DjLQCl/xp5mneXho/h2Hrimq8ParR7hFvc/MCa2GlNlgAYVNHb7m4jDvnEihXe+8Gzfock+4EcKxAB9gQQ= ARC-Message-Signature: i=1; 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Wed, 19 Jun 2019 18:26:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36036) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdiwt-0001iF-Ae for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdiwr-0007mT-03 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:59 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:32981) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwm-0007eW-6t; Wed, 19 Jun 2019 18:20:52 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MHXSD-1hr94x30oj-00DX8f; Thu, 20 Jun 2019 00:19:59 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:30 +0200 Message-Id: <20190619221933.1981-8-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:Vw6GI+FmeIlaBPN8TD5i1Q0v/9m5mPNA8g+tO6Op5R4oF1tvM1N 55waqZKwPYOsaIATogMAyIivwnKoj0qqOQKIo5NKorY1lhfRv8GOMfkzG43LFianXyQ8W1q zP2Je6AF8XXiKfcZnv6j9JXvZ2n0DbOtVMsmaACkYcwMzgXgYJRvx20u7YNWl27OYWP2acg gHIqQNI4Trm+yOcmzCgFw== X-UI-Out-Filterresults: notjunk:1;V03:K0:3vnKdxv6NC0=:HvtCTNSLnRUGxgUmIJwKXZ AOn37pEEX34pW7tNA0fmMJ2CyvbxjoPxWwQiOPGctJMiJZcJ0+4QXa0cac44JfNZ7QYxRHSnq DyyMV4WzmjLpFAX2+q7Yhc04hOUtsaRTb5KJ8QhqqXDxOxF6lnqXniuYTm7Wsb4E/TGReoEEg FAqjgLe4hidNtFmhDpIhu8aN/g2YMChbTh9Xu/qaxkNWUlRvr/3ju2z3TIqai+hjtHo9Udffs EIezQ3MW3rhwrCmRCSfSA7EXBYrakIZ0nfBe/qWMFdeCtxlg6mAv3Bh4rVrATWz235GvgUuHC lEcEe7Qq/gyuRP4nnaING4+krPhr3HPnFaXVuB5mrdMP9m9Zwu4SI3b5XBn3HTwUxEdYNhmjK XJ+8S4gYD9BSXtl1//vbdlf8xlTz6umElnfkx/h7rSIx4xLSE5Rgss8KQaJBUHMur6Xev1wol e4MN4Lx4d7csCEmi9taEuKJ6MsZFpuA+rlGGGYlNlIQbV7jShfqgVSecpNuLhar63cJB0ATX+ jOg9bjaui86kE284hFRlpSR0DtvX+qChTFkq7gfL3fZAEEFRP2YA+i5NjwiYHbwSCQQEDQnig dU9ROloUG6IdaHDq17Rky+UMeupY/BFZfmj2jX8UWLMR6Vl5rthKqMiRWkNxesYoTEqRIgxZi WlZjeO2xPaU8ANZr9ZZHMyOyfCXLoCrc5yJW313U+pDJpentMieBLCL5uJDsxM8xKsIfdq3gr vsrEKTksN0rgXO2Udt4v8c3os5VzH3L0trT8LQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH v8 07/10] hw/m68k: add Nubus support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth --- hw/Kconfig | 1 + hw/Makefile.objs | 1 + hw/nubus/Kconfig | 2 + hw/nubus/Makefile.objs | 4 + hw/nubus/mac-nubus-bridge.c | 45 ++++++ hw/nubus/nubus-bridge.c | 34 +++++ hw/nubus/nubus-bus.c | 111 ++++++++++++++ hw/nubus/nubus-device.c | 215 ++++++++++++++++++++++++++++ include/hw/nubus/mac-nubus-bridge.h | 24 ++++ include/hw/nubus/nubus.h | 69 +++++++++ 10 files changed, 506 insertions(+) create mode 100644 hw/nubus/Kconfig create mode 100644 hw/nubus/Makefile.objs create mode 100644 hw/nubus/mac-nubus-bridge.c create mode 100644 hw/nubus/nubus-bridge.c create mode 100644 hw/nubus/nubus-bus.c create mode 100644 hw/nubus/nubus-device.c create mode 100644 include/hw/nubus/mac-nubus-bridge.h create mode 100644 include/hw/nubus/nubus.h diff --git a/hw/Kconfig b/hw/Kconfig index 195f541e50..c34e0aa99a 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -21,6 +21,7 @@ source isa/Kconfig source mem/Kconfig source misc/Kconfig source net/Kconfig +source nubus/Kconfig source nvram/Kconfig source pci-bridge/Kconfig source pci-host/Kconfig diff --git a/hw/Makefile.objs b/hw/Makefile.objs index d770926ba9..686808dd17 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -36,6 +36,7 @@ devices-dirs-$(CONFIG_SOFTMMU) +=3D watchdog/ devices-dirs-$(CONFIG_SOFTMMU) +=3D xen/ devices-dirs-$(CONFIG_MEM_DEVICE) +=3D mem/ devices-dirs-$(CONFIG_SOFTMMU) +=3D smbios/ +devices-dirs-$(CONFIG_NUBUS) +=3D nubus/ devices-dirs-y +=3D semihosting/ devices-dirs-y +=3D core/ common-obj-y +=3D $(devices-dirs-y) diff --git a/hw/nubus/Kconfig b/hw/nubus/Kconfig new file mode 100644 index 0000000000..8fb8b22189 --- /dev/null +++ b/hw/nubus/Kconfig @@ -0,0 +1,2 @@ +config NUBUS + bool diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs new file mode 100644 index 0000000000..135ba7878d --- /dev/null +++ b/hw/nubus/Makefile.objs @@ -0,0 +1,4 @@ +common-obj-y +=3D nubus-device.o +common-obj-y +=3D nubus-bus.o +common-obj-y +=3D nubus-bridge.o +common-obj-$(CONFIG_Q800) +=3D mac-nubus-bridge.o diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c new file mode 100644 index 0000000000..7c329300b8 --- /dev/null +++ b/hw/nubus/mac-nubus-bridge.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/mac-nubus-bridge.h" + + +static void mac_nubus_bridge_init(Object *obj) +{ + MacNubusState *s =3D MAC_NUBUS_BRIDGE(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + s->bus =3D NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, DEVICE(s), NULL)); + + sysbus_init_mmio(sbd, &s->bus->super_slot_io); + sysbus_init_mmio(sbd, &s->bus->slot_io); +} + +static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "Nubus bridge"; +} + +static const TypeInfo mac_nubus_bridge_info =3D { + .name =3D TYPE_MAC_NUBUS_BRIDGE, + .parent =3D TYPE_NUBUS_BRIDGE, + .instance_init =3D mac_nubus_bridge_init, + .instance_size =3D sizeof(MacNubusState), + .class_init =3D mac_nubus_bridge_class_init, +}; + +static void mac_nubus_bridge_register_types(void) +{ + type_register_static(&mac_nubus_bridge_info); +} + +type_init(mac_nubus_bridge_register_types) diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c new file mode 100644 index 0000000000..cd8c6a91eb --- /dev/null +++ b/hw/nubus/nubus-bridge.c @@ -0,0 +1,34 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/nubus/nubus.h" + +static void nubus_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->fw_name =3D "nubus"; +} + +static const TypeInfo nubus_bridge_info =3D { + .name =3D TYPE_NUBUS_BRIDGE, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SysBusDevice), + .class_init =3D nubus_bridge_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bridge_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c new file mode 100644 index 0000000000..942a6d5342 --- /dev/null +++ b/hw/nubus/nubus-bus.c @@ -0,0 +1,111 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" +#include "hw/sysbus.h" +#include "qapi/error.h" + + +static NubusBus *nubus_find(void) +{ + /* Returns NULL unless there is exactly one nubus device */ + return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL)); +} + +static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + + +static uint64_t nubus_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps nubus_slot_ops =3D { + .read =3D nubus_slot_read, + .write =3D nubus_slot_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr, + unsigned int size) +{ + return 0; +} + +static const MemoryRegionOps nubus_super_slot_ops =3D { + .read =3D nubus_super_slot_read, + .write =3D nubus_super_slot_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + +static void nubus_realize(BusState *bus, Error **errp) +{ + if (!nubus_find()) { + error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_= BUS); + return; + } +} + +static void nubus_init(Object *obj) +{ + NubusBus *nubus =3D NUBUS_BUS(obj); + + memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_op= s, + nubus, "nubus-super-slots", + NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE); + + memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops, + nubus, "nubus-slots", + NUBUS_SLOT_NB * NUBUS_SLOT_SIZE); + + nubus->current_slot =3D NUBUS_FIRST_SLOT; +} + +static void nubus_class_init(ObjectClass *oc, void *data) +{ + BusClass *bc =3D BUS_CLASS(oc); + + bc->realize =3D nubus_realize; +} + +static const TypeInfo nubus_bus_info =3D { + .name =3D TYPE_NUBUS_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(NubusBus), + .instance_init =3D nubus_init, + .class_init =3D nubus_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_bus_info); +} + +type_init(nubus_register_types) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c new file mode 100644 index 0000000000..01ccad9e8e --- /dev/null +++ b/hw/nubus/nubus-device.c @@ -0,0 +1,215 @@ +/* + * QEMU Macintosh Nubus + * + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "hw/nubus/nubus.h" +#include "qapi/error.h" + + +/* The Format Block Structure */ + +#define FBLOCK_DIRECTORY_OFFSET 0 +#define FBLOCK_LENGTH 4 +#define FBLOCK_CRC 8 +#define FBLOCK_REVISION_LEVEL 12 +#define FBLOCK_FORMAT 13 +#define FBLOCK_TEST_PATTERN 14 +#define FBLOCK_RESERVED 18 +#define FBLOCK_BYTE_LANES 19 + +#define FBLOCK_SIZE 20 +#define FBLOCK_PATTERN_VAL 0x5a932bc7 + +static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int = size) +{ + NubusDevice *dev =3D opaque; + uint64_t val; + +#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff) + switch (addr) { + case FBLOCK_BYTE_LANES: + val =3D dev->byte_lanes; + val |=3D (val ^ 0xf) << 4; + break; + case FBLOCK_RESERVED: + val =3D 0x00; + break; + case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3: + val =3D BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN); + break; + case FBLOCK_FORMAT: + val =3D dev->rom_format; + break; + case FBLOCK_REVISION_LEVEL: + val =3D dev->rom_rev; + break; + case FBLOCK_CRC...FBLOCK_CRC + 3: + val =3D BYTE(dev->rom_crc, addr - FBLOCK_CRC); + break; + case FBLOCK_LENGTH...FBLOCK_LENGTH + 3: + val =3D BYTE(dev->rom_length, addr - FBLOCK_LENGTH); + break; + case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3: + val =3D BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET= ); + break; + default: + val =3D 0; + break; + } + return val; +} + +static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static const MemoryRegionOps nubus_format_block_ops =3D { + .read =3D nubus_fblock_read, + .write =3D nubus_fblock_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + } +}; + +static void nubus_register_format_block(NubusDevice *dev) +{ + char *fblock_name; + + fblock_name =3D g_strdup_printf("nubus-slot-%d-format-block", + dev->slot_nb); + + hwaddr fblock_offset =3D memory_region_size(&dev->slot_mem) - FBLOCK_S= IZE; + memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops, + dev, fblock_name, FBLOCK_SIZE); + memory_region_add_subregion(&dev->slot_mem, fblock_offset, + &dev->fblock_io); + + g_free(fblock_name); +} + +static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + /* read only */ +} + +static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NubusDevice *dev =3D opaque; + + return dev->rom[addr]; +} + +static const MemoryRegionOps mac_nubus_rom_ops =3D { + .read =3D mac_nubus_rom_read, + .write =3D mac_nubus_rom_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + + +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes) +{ + hwaddr rom_offset; + char *rom_name; + + /* FIXME : really compute CRC */ + dev->rom_length =3D 0; + dev->rom_crc =3D 0; + + dev->rom_rev =3D revision; + dev->rom_format =3D format; + + dev->byte_lanes =3D byte_lanes; + dev->directory_offset =3D -size; + + /* ROM */ + + dev->rom =3D rom; + rom_name =3D g_strdup_printf("nubus-slot-%d-rom", dev->slot_nb); + memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops, + dev, rom_name, size); + memory_region_set_readonly(&dev->rom_io, true); + + rom_offset =3D memory_region_size(&dev->slot_mem) - FBLOCK_SIZE + + dev->directory_offset; + memory_region_add_subregion(&dev->slot_mem, rom_offset, &dev->rom_io); + + g_free(rom_name); +} + +static void nubus_device_realize(DeviceState *dev, Error **errp) +{ + NubusBus *nubus =3D NUBUS_BUS(qdev_get_parent_bus(DEVICE(dev))); + NubusDevice *nd =3D NUBUS_DEVICE(dev); + char *name; + hwaddr slot_offset; + + if (nubus->current_slot < NUBUS_FIRST_SLOT || + nubus->current_slot > NUBUS_LAST_SLOT) { + error_setg(errp, "Cannot register nubus card, not enough slots"); + return; + } + + nd->slot_nb =3D nubus->current_slot++; + name =3D g_strdup_printf("nubus-slot-%d", nd->slot_nb); + + if (nd->slot_nb < NUBUS_FIRST_SLOT) { + /* Super */ + slot_offset =3D (nd->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE; + + memory_region_init(&nd->slot_mem, OBJECT(dev), name, + NUBUS_SUPER_SLOT_SIZE); + memory_region_add_subregion(&nubus->super_slot_io, slot_offset, + &nd->slot_mem); + } else { + /* Normal */ + slot_offset =3D nd->slot_nb * NUBUS_SLOT_SIZE; + + memory_region_init(&nd->slot_mem, OBJECT(dev), name, NUBUS_SLOT_SI= ZE); + memory_region_add_subregion(&nubus->slot_io, slot_offset, + &nd->slot_mem); + } + + g_free(name); + nubus_register_format_block(nd); +} + +static void nubus_device_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D nubus_device_realize; + dc->bus_type =3D TYPE_NUBUS_BUS; +} + +static const TypeInfo nubus_device_type_info =3D { + .name =3D TYPE_NUBUS_DEVICE, + .parent =3D TYPE_DEVICE, + .abstract =3D true, + .instance_size =3D sizeof(NubusDevice), + .class_init =3D nubus_device_class_init, +}; + +static void nubus_register_types(void) +{ + type_register_static(&nubus_device_type_info); +} + +type_init(nubus_register_types) diff --git a/include/hw/nubus/mac-nubus-bridge.h b/include/hw/nubus/mac-nub= us-bridge.h new file mode 100644 index 0000000000..ce9c789d99 --- /dev/null +++ b/include/hw/nubus/mac-nubus-bridge.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_MAC_H +#define HW_NUBUS_MAC_H + +#include "hw/nubus/nubus.h" + +#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge" +#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \ + TYPE_MAC_NUBUS_BRIDGE) + +typedef struct MacNubusState { + SysBusDevice sysbus_dev; + + NubusBus *bus; +} MacNubusState; + +#endif diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h new file mode 100644 index 0000000000..096bafb322 --- /dev/null +++ b/include/hw/nubus/nubus.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_NUBUS_NUBUS_H +#define HW_NUBUS_NUBUS_H + +#include "hw/qdev.h" +#include "exec/address-spaces.h" + +#define NUBUS_SUPER_SLOT_SIZE 0x10000000U +#define NUBUS_SUPER_SLOT_NB 0x9 + +#define NUBUS_SLOT_SIZE 0x01000000 +#define NUBUS_SLOT_NB 0xF + +#define NUBUS_FIRST_SLOT 0x9 +#define NUBUS_LAST_SLOT 0xF + +#define TYPE_NUBUS_DEVICE "nubus-device" +#define NUBUS_DEVICE(obj) \ + OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE) + +#define TYPE_NUBUS_BUS "nubus-bus" +#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS) + +#define TYPE_NUBUS_BRIDGE "nubus-bridge" +#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRID= GE) + +typedef struct NubusBus { + BusState qbus; + + MemoryRegion super_slot_io; + MemoryRegion slot_io; + + int current_slot; +} NubusBus; + +typedef struct NubusDevice { + DeviceState qdev; + + int slot_nb; + MemoryRegion slot_mem; + + /* Format Block */ + + MemoryRegion fblock_io; + + uint32_t rom_length; + uint32_t rom_crc; + uint8_t rom_rev; + uint8_t rom_format; + uint8_t byte_lanes; + int32_t directory_offset; + + /* ROM */ + + MemoryRegion rom_io; + const uint8_t *rom; +} NubusDevice; + +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t siz= e, + int revision, int format, uint8_t byte_lanes); + +#endif --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 19 Jun 2019 15:26:22 -0700 (PDT) Received: from localhost ([::1]:42334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdj22-0006XT-Bi for importer@patchew.org; Wed, 19 Jun 2019 18:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36033) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdiwt-0001hp-2W for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdiwr-0007oJ-I4 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:58 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:55057) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwo-0007iW-NU; Wed, 19 Jun 2019 18:20:54 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MdNse-1iCmhc0YGO-00ZLPw; Thu, 20 Jun 2019 00:20:00 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:31 +0200 Message-Id: <20190619221933.1981-9-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:h0lBnGkz286V7bvmWJ5gZuoalWyxGJLRdgvCJL6C2vsCn/TDHqS k0fcJfguog0gImKHUOK0shFyCvOtT4rOxvXqfU0hy1sdk0ZCioGGTFx8jLxxlPhk85ulkZX hSgG99cF+3lVI4NdI0dccWxq35LzIljLcBt1KG6lMV6AaBUDkQtj1WNqNNCyQztEi8eZn33 SYDM4zLnLOAei1AswraDg== X-UI-Out-Filterresults: notjunk:1;V03:K0:AMA5apviTAg=:ajeo4knuuyb9O/kg5/WMmg 2rcl7SPq3HbOcR8tDob7NG5jeGHBJVBRBzChlskLT/EWXNY8P26PdrFDQh3pDU+o86/pvM+UN F6qoCe/xtlyj6ADSoFhsjUIk3El1Ni/EY+fqY9nKACx4uSKYHiCsffuN1qjXUcWGbOcFgwUIu OirOHuvIuJQuzdVBqTM6B4TD7bEJ5bjtHtI8rkXImDHe+Rr56/F4hxoFoL/Gh8IWPJs3qTEzj 20ar72m8SQQNCB7ymXJ6w3Ord7nA5FLkO4ltiNr/iPUP/KFIRy7iF34Q5sQzuhtBBjDMdHdKS gCn64FEV1M7CliQ28HEFXR6XPzn3+tGkVB64Tz8HBAyHwYSm/3gSKj7SY/HnH1XqbOJ+BfX1R 72oamyGEP2L3PLS2BcmwI27Y8aT+87FJIfIgcDxVX5fKaeggI8YGiWr3KzO3YZcoJcofGHtjH J33m96aULtX4+1aEXsl8OecCfxO9kUh1oPYHVHtQjXRIPN9BgRf9xUzeFuzFO2/5pg06GC2gI GPyWX5mzYRduNpffwzMaUh59nhxCm23Fic8xsXNHe5hI7Yc+HjOFrchlv7BvWmtcvH8yxoyf2 1LJA8rBMW0fZaZFPRFokB/vnQ6OMS5KjwTmuqTtGb44xY7DtMoCXFinhJmodWbiJO/91kiSm5 rrMNOLEMWpnHvUB6f+oFhEyH3++Et8Xzq7MW4Q4VjcgCrkjexI+wqYUrrhqEMQ/efQP7K9Ye1 ijF//PiqC6VRtJSDq668pGvz5j807nZtR/MnCdphIjhV+aPOfRw7sYhip2I= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v8 08/10] hw/m68k: add Nubus support for macfb video card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/display/Kconfig | 1 + hw/display/macfb.c | 56 ++++++++++++++++++++++++++++++++++++++ include/hw/display/macfb.h | 21 ++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 035cd85bcf..95096d3c82 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -133,3 +133,4 @@ config ATI_VGA =20 config MACFB bool + depends on NUBUS diff --git a/hw/display/macfb.c b/hw/display/macfb.c index 61ba2e9e15..458e268d86 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -15,6 +15,7 @@ #include "hw/sysbus.h" #include "ui/console.h" #include "ui/pixel_ops.h" +#include "hw/nubus/nubus.h" #include "hw/display/macfb.h" #include "qapi/error.h" =20 @@ -380,12 +381,38 @@ static void macfb_sysbus_realize(DeviceState *dev, Er= ror **errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram); } =20 +const uint8_t macfb_rom[] =3D { + 255, 0, 0, 0, +}; + +static void macfb_nubus_realize(DeviceState *dev, Error **errp) +{ + NubusDevice *nd =3D NUBUS_DEVICE(dev); + MacfbNubusState *s =3D NUBUS_MACFB(dev); + MacfbNubusDeviceClass *ndc =3D MACFB_NUBUS_GET_CLASS(dev); + MacfbState *ms =3D &s->macfb; + + ndc->parent_realize(dev, errp); + + macfb_common_realize(dev, ms, errp); + memory_region_add_subregion(&nd->slot_mem, DAFB_BASE, &ms->mem_ctrl); + memory_region_add_subregion(&nd->slot_mem, VIDEO_BASE, &ms->mem_vram); + + nubus_register_rom(nd, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf); +} + static void macfb_sysbus_reset(DeviceState *d) { MacfbSysBusState *s =3D MACFB(d); macfb_reset(&s->macfb); } =20 +static void macfb_nubus_reset(DeviceState *d) +{ + MacfbNubusState *s =3D NUBUS_MACFB(d); + macfb_reset(&s->macfb); +} + static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640), DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480), @@ -393,6 +420,13 @@ static Property macfb_sysbus_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property macfb_nubus_properties[] =3D { + DEFINE_PROP_UINT32("width", MacfbNubusState, macfb.width, 640), + DEFINE_PROP_UINT32("height", MacfbNubusState, macfb.height, 480), + DEFINE_PROP_UINT8("depth", MacfbNubusState, macfb.depth, 8), + DEFINE_PROP_END_OF_LIST(), +}; + static void macfb_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -404,6 +438,19 @@ static void macfb_sysbus_class_init(ObjectClass *klass= , void *data) dc->props =3D macfb_sysbus_properties; } =20 +static void macfb_nubus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MacfbNubusDeviceClass *ndc =3D MACFB_NUBUS_DEVICE_CLASS(klass); + + device_class_set_parent_realize(dc, macfb_nubus_realize, + &ndc->parent_realize); + dc->desc =3D "Nubus Macintosh framebuffer"; + dc->reset =3D macfb_nubus_reset; + dc->vmsd =3D &vmstate_macfb; + dc->props =3D macfb_nubus_properties; +} + static TypeInfo macfb_sysbus_info =3D { .name =3D TYPE_MACFB, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -411,9 +458,18 @@ static TypeInfo macfb_sysbus_info =3D { .class_init =3D macfb_sysbus_class_init, }; =20 +static TypeInfo macfb_nubus_info =3D { + .name =3D TYPE_NUBUS_MACFB, + .parent =3D TYPE_NUBUS_DEVICE, + .instance_size =3D sizeof(MacfbNubusState), + .class_init =3D macfb_nubus_class_init, + .class_size =3D sizeof(MacfbNubusDeviceClass), +}; + static void macfb_register_types(void) { type_register_static(&macfb_sysbus_info); + type_register_static(&macfb_nubus_info); } =20 type_init(macfb_register_types) diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h index 3fe2592735..26367ae2c4 100644 --- a/include/hw/display/macfb.h +++ b/include/hw/display/macfb.h @@ -40,4 +40,25 @@ typedef struct { MacfbState macfb; } MacfbSysBusState; =20 +#define MACFB_NUBUS_DEVICE_CLASS(class) \ + OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB) +#define MACFB_NUBUS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB) + +typedef struct MacfbNubusDeviceClass { + DeviceClass parent_class; + + DeviceRealize parent_realize; +} MacfbNubusDeviceClass; + +#define TYPE_NUBUS_MACFB "nubus-macfb" +#define NUBUS_MACFB(obj) \ + OBJECT_CHECK(MacfbNubusState, (obj), TYPE_NUBUS_MACFB) + +typedef struct { + NubusDevice busdev; + + MacfbState macfb; +} MacfbNubusState; + #endif --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983696; cv=none; d=zoho.com; s=zohoarc; b=N5OAz+7Xz/WoH70kb8E8bjGjQqPXsv3vU5qsgtgQy/FC5b/mj5nOpOIbASUhMKjkS2OKn2c5B1aQ83LmMqp6/Upo7Kj+CsHYkqKCM25u6a2vCrDljkQCJgbKjadXNkobYV8JknY+cE3F3Zt9TqPIo8FCD6zR+cb19QSnsUGDSdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 19 Jun 2019 18:34:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36165) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdix5-0001y7-L3 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdix1-00082D-OF for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:21:10 -0400 Received: from mout.kundenserver.de ([212.227.126.133]:60289) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwv-0007sD-SK; Wed, 19 Jun 2019 18:21:02 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1N7iT4-1ih3Ip1G78-014ocA; Thu, 20 Jun 2019 00:20:01 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:32 +0200 Message-Id: <20190619221933.1981-10-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:ihzSk7jLvt+l5ErI3OgJNfznFBD/DbtJBwzQUuMcgzuLJXS0TlL BKuGpMh95+QP0+V5mXDLI3DhmhdiYEeR9JBgmoP4RZE7I8hJ+dMSa1e90qOu6c8kwsJcZkf esKCwhAn96nH0zfxU+7DhhCu41BSLuHk197hyXRiYAzM+4E2pyShQNgVWgbzkiWPsSSjyAu dGgF6yzry9+PTW2y74p6g== X-UI-Out-Filterresults: notjunk:1;V03:K0:JMsojiZbMqo=:U+BQGA/maQHLiIQPBu++KW StI8Pojd0UNRVvAMGCHbYDRwkXLBKVGBJO8xu2o5fMTEEFZuozrRM4Jy5YvVpIoo/BDYzCCGs Q1HSTzsRZ61jSIbxViTtXlpXQQIlQLCFjTNxtWcI0lFnOFEXctwshqWbBcqTFVb97sv+AN7Fe G6CDxLe6z3y32u5wctHL4Y18MAUzVCEFJZfLw5VvADE1ZR6IJmpyh78XLkCiuwSG2iCoJKaz8 G6LeOvUAZx+t1U4jHrDD4WKPvQWPFP1ji/FUdw4sOxR0fCZ6bQM1Dz2yCsDl6pZeAPAAEGW3Q 6PRgQj0tZdGggwhh9xtG+YdNGE+pF+1Ji6U3xnnAIo+cMtEHvIdgTR7QutTi0M0uKUT7M6CVU bhesQL20tzlhVcPOSpapN3POU/QvWdv1xw/NyJYDeErqMDnxKm8UMbn+wJjtCCeU19BkriuxK 0Ya13JXXfg0mTCdDeE7V0A/ejCjHClSMEojN7R2oGCbgEgpTK3k/I+Fba3PMrcF/b3eCOUSmn Rp7LaNKJstvA5m9GFGOV/DwanjbVzBicJILCn6nwHIJnlNCQfsolEYjDzf1MkM+PXTv4XbK/R kxykLH0y9KfT2NUQ0yyLDS42GjUHt8s1hzUoPKV4wHB58XSpLOoT2XJGQnPIYqyLszsuO0fXM wdkRDW51VJ+q2u6gyw9TkWILIcnAqUWJxX288PRzz445FSQWEqgZZzg10OEoDLprXR4H8rp9B oGvZJ3drSriNr1gNuwk3AU0xDVfofnXo7OvYTCFsOhgLVk8QDaudffY8U08= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PATCH v8 09/10] hw/m68k: add a dummy SWIM floppy controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Herv=C3=A9 Poussineau --- hw/block/Kconfig | 3 + hw/block/Makefile.objs | 1 + hw/block/swim.c | 415 ++++++++++++++++++++++++++++++++++++++++ include/hw/block/swim.h | 76 ++++++++ 4 files changed, 495 insertions(+) create mode 100644 hw/block/swim.c create mode 100644 include/hw/block/swim.h diff --git a/hw/block/Kconfig b/hw/block/Kconfig index df96dc5dcc..2d17f481ad 100644 --- a/hw/block/Kconfig +++ b/hw/block/Kconfig @@ -37,3 +37,6 @@ config VHOST_USER_BLK # Only PCI devices are provided for now default y if VIRTIO_PCI depends on VIRTIO && VHOST_USER && LINUX + +config SWIM + bool diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs index f5f643f0cc..28c2495a00 100644 --- a/hw/block/Makefile.objs +++ b/hw/block/Makefile.objs @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XEN) +=3D xen-block.o common-obj-$(CONFIG_ECC) +=3D ecc.o common-obj-$(CONFIG_ONENAND) +=3D onenand.o common-obj-$(CONFIG_NVME_PCI) +=3D nvme.o +common-obj-$(CONFIG_SWIM) +=3D swim.o =20 obj-$(CONFIG_SH4) +=3D tc58128.o =20 diff --git a/hw/block/swim.c b/hw/block/swim.c new file mode 100644 index 0000000000..0f48e46d58 --- /dev/null +++ b/hw/block/swim.c @@ -0,0 +1,415 @@ +/* + * QEMU Macintosh floppy disk controller emulator (SWIM) + * + * Copyright (c) 2014-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "sysemu/block-backend.h" +#include "hw/sysbus.h" +#include "hw/block/block.h" +#include "hw/block/swim.h" + +/* IWM registers */ + +#define IWM_PH0L 0 +#define IWM_PH0H 1 +#define IWM_PH1L 2 +#define IWM_PH1H 3 +#define IWM_PH2L 4 +#define IWM_PH2H 5 +#define IWM_PH3L 6 +#define IWM_PH3H 7 +#define IWM_MTROFF 8 +#define IWM_MTRON 9 +#define IWM_INTDRIVE 10 +#define IWM_EXTDRIVE 11 +#define IWM_Q6L 12 +#define IWM_Q6H 13 +#define IWM_Q7L 14 +#define IWM_Q7H 15 + +/* SWIM registers */ + +#define SWIM_WRITE_DATA 0 +#define SWIM_WRITE_MARK 1 +#define SWIM_WRITE_CRC 2 +#define SWIM_WRITE_PARAMETER 3 +#define SWIM_WRITE_PHASE 4 +#define SWIM_WRITE_SETUP 5 +#define SWIM_WRITE_MODE0 6 +#define SWIM_WRITE_MODE1 7 + +#define SWIM_READ_DATA 8 +#define SWIM_READ_MARK 9 +#define SWIM_READ_ERROR 10 +#define SWIM_READ_PARAMETER 11 +#define SWIM_READ_PHASE 12 +#define SWIM_READ_SETUP 13 +#define SWIM_READ_STATUS 14 +#define SWIM_READ_HANDSHAKE 15 + +#define REG_SHIFT 9 + +#define SWIM_MODE_IWM 0 +#define SWIM_MODE_SWIM 1 + +/* bits in phase register */ + +#define SWIM_SEEK_NEGATIVE 0x074 +#define SWIM_STEP 0x071 +#define SWIM_MOTOR_ON 0x072 +#define SWIM_MOTOR_OFF 0x076 +#define SWIM_INDEX 0x073 +#define SWIM_EJECT 0x077 +#define SWIM_SETMFM 0x171 +#define SWIM_SETGCR 0x175 +#define SWIM_RELAX 0x033 +#define SWIM_LSTRB 0x008 +#define SWIM_CA_MASK 0x077 + +/* Select values for swim_select and swim_readbit */ + +#define SWIM_READ_DATA_0 0x074 +#define SWIM_TWOMEG_DRIVE 0x075 +#define SWIM_SINGLE_SIDED 0x076 +#define SWIM_DRIVE_PRESENT 0x077 +#define SWIM_DISK_IN 0x170 +#define SWIM_WRITE_PROT 0x171 +#define SWIM_TRACK_ZERO 0x172 +#define SWIM_TACHO 0x173 +#define SWIM_READ_DATA_1 0x174 +#define SWIM_MFM_MODE 0x175 +#define SWIM_SEEK_COMPLETE 0x176 +#define SWIM_ONEMEG_MEDIA 0x177 + +/* Bits in handshake register */ + +#define SWIM_MARK_BYTE 0x01 +#define SWIM_CRC_ZERO 0x02 +#define SWIM_RDDATA 0x04 +#define SWIM_SENSE 0x08 +#define SWIM_MOTEN 0x10 +#define SWIM_ERROR 0x20 +#define SWIM_DAT2BYTE 0x40 +#define SWIM_DAT1BYTE 0x80 + +/* bits in setup register */ + +#define SWIM_S_INV_WDATA 0x01 +#define SWIM_S_3_5_SELECT 0x02 +#define SWIM_S_GCR 0x04 +#define SWIM_S_FCLK_DIV2 0x08 +#define SWIM_S_ERROR_CORR 0x10 +#define SWIM_S_IBM_DRIVE 0x20 +#define SWIM_S_GCR_WRITE 0x40 +#define SWIM_S_TIMEOUT 0x80 + +/* bits in mode register */ + +#define SWIM_CLFIFO 0x01 +#define SWIM_ENBL1 0x02 +#define SWIM_ENBL2 0x04 +#define SWIM_ACTION 0x08 +#define SWIM_WRITE_MODE 0x10 +#define SWIM_HEDSEL 0x20 +#define SWIM_MOTON 0x80 + +static void swim_change_cb(void *opaque, bool load, Error **errp) +{ + FDrive *drive =3D opaque; + + if (!load) { + blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); + } else { + if (!blkconf_apply_backend_options(drive->conf, + blk_is_read_only(drive->blk), f= alse, + errp)) { + return; + } + } +} + +static const BlockDevOps swim_block_ops =3D { + .change_media_cb =3D swim_change_cb, +}; + +static Property swim_drive_properties[] =3D { + DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1), + DEFINE_BLOCK_PROPERTIES(SWIMDrive, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void swim_drive_realize(DeviceState *qdev, Error **errp) +{ + SWIMDrive *dev =3D SWIM_DRIVE(qdev); + SWIMBus *bus =3D SWIM_BUS(qdev->parent_bus); + FDrive *drive; + int ret; + + if (dev->unit =3D=3D -1) { + for (dev->unit =3D 0; dev->unit < SWIM_MAX_FD; dev->unit++) { + drive =3D &bus->ctrl->drives[dev->unit]; + if (!drive->blk) { + break; + } + } + } + + if (dev->unit >=3D SWIM_MAX_FD) { + error_setg(errp, "Can't create floppy unit %d, bus supports " + "only %d units", dev->unit, SWIM_MAX_FD); + return; + } + + drive =3D &bus->ctrl->drives[dev->unit]; + if (drive->blk) { + error_setg(errp, "Floppy unit %d is in use", dev->unit); + return; + } + + if (!dev->conf.blk) { + /* Anonymous BlockBackend for an empty drive */ + dev->conf.blk =3D blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); + ret =3D blk_attach_dev(dev->conf.blk, qdev); + assert(ret =3D=3D 0); + } + + blkconf_blocksizes(&dev->conf); + if (dev->conf.logical_block_size !=3D 512 || + dev->conf.physical_block_size !=3D 512) + { + error_setg(errp, "Physical and logical block size must " + "be 512 for floppy"); + return; + } + + /* rerror/werror aren't supported by fdc and therefore not even regist= ered + * with qdev. So set the defaults manually before they are used in + * blkconf_apply_backend_options(). */ + dev->conf.rerror =3D BLOCKDEV_ON_ERROR_AUTO; + dev->conf.werror =3D BLOCKDEV_ON_ERROR_AUTO; + + if (!blkconf_apply_backend_options(&dev->conf, + blk_is_read_only(dev->conf.blk), + false, errp)) { + return; + } + + /* 'enospc' is the default for -drive, 'report' is what blk_new() give= s us + * for empty drives. */ + if (blk_get_on_error(dev->conf.blk, 0) !=3D BLOCKDEV_ON_ERROR_ENOSPC && + blk_get_on_error(dev->conf.blk, 0) !=3D BLOCKDEV_ON_ERROR_REPORT) { + error_setg(errp, "fdc doesn't support drive option werror"); + return; + } + if (blk_get_on_error(dev->conf.blk, 1) !=3D BLOCKDEV_ON_ERROR_REPORT) { + error_setg(errp, "fdc doesn't support drive option rerror"); + return; + } + + drive->conf =3D &dev->conf; + drive->blk =3D dev->conf.blk; + drive->swimctrl =3D bus->ctrl; + + blk_set_dev_ops(drive->blk, &swim_block_ops, drive); +} + +static void swim_drive_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k =3D DEVICE_CLASS(klass); + k->realize =3D swim_drive_realize; + set_bit(DEVICE_CATEGORY_STORAGE, k->categories); + k->bus_type =3D TYPE_SWIM_BUS; + k->props =3D swim_drive_properties; + k->desc =3D "virtual SWIM drive"; +} + +static const TypeInfo swim_drive_info =3D { + .name =3D TYPE_SWIM_DRIVE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(SWIMDrive), + .class_init =3D swim_drive_class_init, +}; + +static const TypeInfo swim_bus_info =3D { + .name =3D TYPE_SWIM_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(SWIMBus), +}; + +static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + if (swimctrl->regs[IWM_Q6] && + swimctrl->regs[IWM_Q7]) { + if (swimctrl->regs[IWM_MTR]) { + /* data register */ + swimctrl->iwm_data =3D value; + } else { + /* mode register */ + swimctrl->iwm_mode =3D value; + /* detect sequence to switch from IWM mode to SWIM mode */ + switch (swimctrl->iwm_switch) { + case 0: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 1: + if (value =3D=3D 0x17) { + swimctrl->iwm_switch++; + } + break; + case 2: + if (value =3D=3D 0x57) { + swimctrl->iwm_switch++; + } + break; + case 3: + if (value =3D=3D 0x57) { + swimctrl->mode =3D SWIM_MODE_SWIM; + swimctrl->iwm_switch =3D 0; + } + break; + } + } + } +} + +static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + reg >>=3D REG_SHIFT; + + swimctrl->regs[reg >> 1] =3D reg & 1; + + return 0; +} + +static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + iwmctrl_write(opaque, reg, value, size); + return; + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_WRITE_PHASE: + swimctrl->swim_phase =3D value; + break; + case SWIM_WRITE_MODE0: + swimctrl->swim_mode &=3D ~value; + break; + case SWIM_WRITE_MODE1: + swimctrl->swim_mode |=3D value; + break; + case SWIM_WRITE_DATA: + case SWIM_WRITE_MARK: + case SWIM_WRITE_CRC: + case SWIM_WRITE_PARAMETER: + case SWIM_WRITE_SETUP: + break; + } +} + +static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) +{ + SWIMCtrl *swimctrl =3D opaque; + uint32_t value =3D 0; + + if (swimctrl->mode =3D=3D SWIM_MODE_IWM) { + return iwmctrl_read(opaque, reg, size); + } + + reg >>=3D REG_SHIFT; + + switch (reg) { + case SWIM_READ_PHASE: + value =3D swimctrl->swim_phase; + break; + case SWIM_READ_HANDSHAKE: + if (swimctrl->swim_phase =3D=3D SWIM_DRIVE_PRESENT) { + /* always answer "no drive present" */ + value =3D SWIM_SENSE; + } + break; + case SWIM_READ_DATA: + case SWIM_READ_MARK: + case SWIM_READ_ERROR: + case SWIM_READ_PARAMETER: + case SWIM_READ_SETUP: + case SWIM_READ_STATUS: + break; + } + + return value; +} + +static const MemoryRegionOps swimctrl_mem_ops =3D { + .write =3D swimctrl_write, + .read =3D swimctrl_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void sysbus_swim_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SWIM *sbs =3D SWIM(obj); + SWIMCtrl *swimctrl =3D &sbs->ctrl; + + memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimct= rl, + "swim", 0x2000); + sysbus_init_mmio(sbd, &swimctrl->iomem); +} + +static void sysbus_swim_realize(DeviceState *dev, Error **errp) +{ + SWIM *sys =3D SWIM(dev); + SWIMCtrl *swimctrl =3D &sys->ctrl; + + qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, de= v, + NULL); + swimctrl->bus.ctrl =3D swimctrl; +} + +static void sysbus_swim_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D sysbus_swim_realize; +} + +static const TypeInfo sysbus_swim_info =3D { + .name =3D TYPE_SWIM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SWIM), + .instance_init =3D sysbus_swim_init, + .class_init =3D sysbus_swim_class_init, +}; + +static void swim_register_types(void) +{ + type_register_static(&sysbus_swim_info); + type_register_static(&swim_bus_info); + type_register_static(&swim_drive_info); +} + +type_init(swim_register_types) diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h new file mode 100644 index 0000000000..e69c644995 --- /dev/null +++ b/include/hw/block/swim.h @@ -0,0 +1,76 @@ +/* + * QEMU Macintosh floppy disk controller emulator (SWIM) + * + * Copyright (c) 2014-2018 Laurent Vivier + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef SWIM_H +#define SWIM_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" + +#define SWIM_MAX_FD 2 + +typedef struct SWIMDrive SWIMDrive; +typedef struct SWIMBus SWIMBus; +typedef struct SWIMCtrl SWIMCtrl; + +#define TYPE_SWIM_DRIVE "swim-drive" +#define SWIM_DRIVE(obj) OBJECT_CHECK(SWIMDrive, (obj), TYPE_SWIM_DRIVE) + +struct SWIMDrive { + DeviceState qdev; + int32_t unit; + BlockConf conf; +}; + +#define TYPE_SWIM_BUS "swim-bus" +#define SWIM_BUS(obj) OBJECT_CHECK(SWIMBus, (obj), TYPE_SWIM_BUS) + +struct SWIMBus { + BusState bus; + struct SWIMCtrl *ctrl; +}; + +typedef struct FDrive { + SWIMCtrl *swimctrl; + BlockBackend *blk; + BlockConf *conf; +} FDrive; + +struct SWIMCtrl { + MemoryRegion iomem; + FDrive drives[SWIM_MAX_FD]; + int mode; + /* IWM mode */ + int iwm_switch; + int regs[8]; +#define IWM_PH0 0 +#define IWM_PH1 1 +#define IWM_PH2 2 +#define IWM_PH3 3 +#define IWM_MTR 4 +#define IWM_DRIVE 5 +#define IWM_Q6 6 +#define IWM_Q7 7 + uint8_t iwm_data; + uint8_t iwm_mode; + /* SWIM mode */ + uint8_t swim_phase; + uint8_t swim_mode; + SWIMBus bus; +}; + +#define TYPE_SWIM "swim" +#define SWIM(obj) OBJECT_CHECK(SWIM, (obj), TYPE_SWIM) + +typedef struct SWIM { + SysBusDevice parent_obj; + SWIMCtrl ctrl; +} SWIM; +#endif --=20 2.21.0 From nobody Wed May 15 21:05:20 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560983000; cv=none; d=zoho.com; s=zohoarc; b=fRmoIZxkMCYZbqKHGDs1JhvedPGL1q7pAiIB1IarPQh0lsOim35lAAsIhcOMlUNfRoApxyRUNehnzDE5eW1LIV9hazQLAdMQYoDImcCuXCy6Kq08nhRMwOwr99u7S8docVg/5THKH46acN+vr2q9hmyHqLJyK567LBySGEvX9FU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 19 Jun 2019 18:20:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdiwn-0007hh-6A for qemu-devel@nongnu.org; Wed, 19 Jun 2019 18:20:55 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:43695) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdiwm-0007eZ-Q8; Wed, 19 Jun 2019 18:20:53 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M5PyX-1hf5qZ36bF-001O2j; Thu, 20 Jun 2019 00:20:03 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 00:19:33 +0200 Message-Id: <20190619221933.1981-11-laurent@vivier.eu> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190619221933.1981-1-laurent@vivier.eu> References: <20190619221933.1981-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:No/fqpF9v4hDpNCLU7PHkIbyIPvUbxKVP+5PRi4Pr1T/F+cP4PA eBV1JirIyWFQ+NtCx7vUBXuFa6Y32gNaEvjaB6xc7YD0YaIDeSYAVOvt3lkaC1Iad9u5KsN tXY6bxDsXx+AG/oQTJnd7XlwzyNi8r2bPlCytyOSyOugf8CoX3RKBxeSye3EpaE2BYB81Cu MLDUNjTXCuph+hCJJiQdQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:X0uZW6F1Y6U=:PLcSX3592P8N5h1Oti21/8 TjxPripXRy2tbuPaw3JqBhcF+oK5tJyxFtBkToQvc0HoewoM7FIBkWBNoYWv+IqVB9BtsFB3N 8fu7keR1t0DRZKqKX4clEM3kL9wuCARvFF7gNPzAXK/D8Zo8kApVjxRPxnmZsDHStAGNDXScq gXVfxFps8izEgdOtq74LfyUbhBSDs/mClYSsJbLEG98nc8z9PBbyi3boL+JBx4kF/xRBioBkq JTsKNFnAWmX+iz5/8WO7guBjRWEtcZQ/MAYdf0zNCPpGzXzjznrT1OXUrdiJWF0Omq1GyfT4E vs3KYV54DZ78ow3CYGs1+FRaFrK03zLIWRgyXxig1mbM5MVyyt80x2uZ63fo83ykLUwEG4gu3 dMz0Uxrvl8q012eNn7nwY5iZwYu6hftg5ygp8DjHSWJFk7f6KMrE1DsHhW4m8NIfhata/rH5S qtqNyt5EbkxbKNP80h137XbA7qY7ThetqNUv3Msxa9B5fTyWkjm/5+y6q8m1HDO2VmCpfA3GO r+0O7IvEE1VdY7flaEB5jb5TZd7Jh5Q2qYFFvd3cGjgBLv94Ee6V1OFvG4o5ZKjNgU/+3Wz4U Kvd6DVVir8J5PmAoqDW30s3lKhswl1e4AXVb2+46K0nWl5mDB92XJOqL6fIvCbwsVjnimVKcq yFbsJe+FFwkX+x/K4JKaegbvwtIV8BvKAMr+AjkfGov1LlcR8VkzN3AoEjIjVo7eQpEZnjoZR EO6x5QDEsX87lCCglgk1NeSomkEnt+WImHyTdg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH v8 10/10] hw/m68k: define Macintosh Quadra 800 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , Laurent Vivier , "Dr . David Alan Gilbert" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Gerd Hoffmann , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Max Reitz , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" If you want to test the machine, it doesn't yet boot a MacROM, but you can boot a linux kernel from the command line. You can install your own disk using debian-installer with: ./qemu-system-m68k \ -M q800 \ -serial none -serial mon:stdio \ -m 1000M -drive file=3Dm68k.qcow2,format=3Dqcow2 \ -net nic,model=3Ddp83932,addr=3D09:00:07:12:34:57 \ -append "console=3DttyS0 vga=3Doff" \ -kernel vmlinux-4.15.0-2-m68k \ -initrd initrd.gz \ -drive file=3Ddebian-9.0-m68k-NETINST-1.iso \ -drive file=3Dm68k.qcow2,format=3Dqcow2 \ -nographic If you use a graphic adapter instead of "-nographic", you can use "-g" to s= et the size of the display (I use "-g 1600x800x24"). Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Tested-by: Thomas Huth --- MAINTAINERS | 14 ++ default-configs/m68k-softmmu.mak | 1 + hw/m68k/Kconfig | 12 + hw/m68k/Makefile.objs | 1 + hw/m68k/bootinfo.h | 114 ++++++++++ hw/m68k/q800.c | 377 +++++++++++++++++++++++++++++++ 6 files changed, 519 insertions(+) create mode 100644 hw/m68k/bootinfo.h create mode 100644 hw/m68k/q800.c diff --git a/MAINTAINERS b/MAINTAINERS index d32c5c2313..aa00525d37 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -902,6 +902,20 @@ F: hw/char/mcf_uart.c F: hw/net/mcf_fec.c F: include/hw/m68k/mcf*.h =20 +q800 +M: Laurent Vivier +S: Maintained +F: hw/block/swim.c +F: hw/m68k/bootinfo.h +F: hw/display/macfb.c +F: hw/m68k/q800.c +F: hw/misc/mac_via.c +F: hw/nubus/* +F: include/hw/block/swim.h +F: include/hw/display/macfb.h +F: include/hw/misc/mac_via.h +F: include/hw/nubus/* + MicroBlaze Machines ------------------- petalogix_s3adsp1800 diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmm= u.mak index 4049a8f2ba..0fbae017ca 100644 --- a/default-configs/m68k-softmmu.mak +++ b/default-configs/m68k-softmmu.mak @@ -6,3 +6,4 @@ CONFIG_SEMIHOSTING=3Dy # CONFIG_AN5206=3Dy CONFIG_MCF5208=3Dy +CONFIG_Q800=3Dy diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index 49ef0b3f6d..ffa8e48fd8 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -7,3 +7,15 @@ config MCF5208 bool select COLDFIRE select PTIMER + +config Q800 + bool + select FRAMEBUFFER + select ADB + select MAC_VIA + select ESCC + select ESP + select MACFB + select NUBUS + select DP8393X + select SWIM diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs index 482f8477b4..cfd13fae53 100644 --- a/hw/m68k/Makefile.objs +++ b/hw/m68k/Makefile.objs @@ -1,2 +1,3 @@ obj-$(CONFIG_AN5206) +=3D an5206.o mcf5206.o obj-$(CONFIG_MCF5208) +=3D mcf5208.o mcf_intc.o +obj-$(CONFIG_Q800) +=3D q800.o diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h new file mode 100644 index 0000000000..5f8ded2686 --- /dev/null +++ b/hw/m68k/bootinfo.h @@ -0,0 +1,114 @@ +/* + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note + * + * Bootinfo tags from linux bootinfo.h and bootinfo-mac.h: + * This is an easily parsable and extendable structure containing all + * information to be passed from the bootstrap to the kernel + * + * This structure is copied right after the kernel by the bootstrap + * routine. + */ + +#ifndef HW_M68K_BOOTINFO_H +#define HW_M68K_BOOTINFO_H +struct bi_record { + uint16_t tag; /* tag ID */ + uint16_t size; /* size of record */ + uint32_t data[0]; /* data */ +}; + +/* machine independent tags */ + +#define BI_LAST 0x0000 /* last record */ +#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ +#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ +#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ +#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ +#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ + /* (struct mem_info) */ +#define BI_RAMDISK 0x0006 /* ramdisk address and size */ + /* (struct mem_info) */ +#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ + /* (string) */ + +/* Macintosh-specific tags (all u_long) */ + +#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ +#define BI_MAC_VADDR 0x8001 /* Mac video base address */ +#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ +#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ +#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ +#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ +#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ +#define BI_MAC_BTIME 0x8007 /* Mac boot time */ +#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ +#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ +#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ +#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ + +/* Macintosh hardware profile data */ + +#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) = */ +#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ +#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ +#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ +#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ +#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi)= */ +#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ +#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi= ) */ +#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ +#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ +#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) = */ +#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ +#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ +#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE = */ +#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ +#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardwar= e */ +#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ +#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ + +#define BOOTINFO0(as, base, id) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record)); \ + base +=3D 2; \ + } while (0) + +#define BOOTINFO1(as, base, id, value) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 4); \ + base +=3D 2; \ + stl_phys(as, base, value); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFO2(as, base, id, value1, value2) \ + do { \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, sizeof(struct bi_record) + 8); \ + base +=3D 2; \ + stl_phys(as, base, value1); \ + base +=3D 4; \ + stl_phys(as, base, value2); \ + base +=3D 4; \ + } while (0) + +#define BOOTINFOSTR(as, base, id, string) \ + do { \ + int i; \ + stw_phys(as, base, id); \ + base +=3D 2; \ + stw_phys(as, base, \ + (sizeof(struct bi_record) + strlen(string) + 2) & ~1); \ + base +=3D 2; \ + for (i =3D 0; string[i]; i++) { \ + stb_phys(as, base++, string[i]); \ + } \ + stb_phys(as, base++, 0); \ + base =3D (parameters_base + 1) & ~1; \ + } while (0) +#endif diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c new file mode 100644 index 0000000000..ca37fb7d31 --- /dev/null +++ b/hw/m68k/q800.c @@ -0,0 +1,377 @@ +/* + * QEMU Motorla 680x0 Macintosh hardware System Emulator + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/sysemu.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "elf.h" +#include "hw/loader.h" +#include "ui/console.h" +#include "exec/address-spaces.h" +#include "hw/char/escc.h" +#include "hw/sysbus.h" +#include "hw/scsi/esp.h" +#include "bootinfo.h" +#include "hw/misc/mac_via.h" +#include "hw/input/adb.h" +#include "hw/nubus/mac-nubus-bridge.h" +#include "hw/display/macfb.h" +#include "hw/block/swim.h" +#include "net/net.h" +#include "qapi/error.h" +#include "sysemu/qtest.h" + +#define MACROM_ADDR 0x40000000 +#define MACROM_SIZE 0x00100000 + +#define MACROM_FILENAME "MacROM.bin" + +#define Q800_MACHINE_ID 35 +#define Q800_CPU_ID (1 << 2) +#define Q800_FPU_ID (1 << 2) +#define Q800_MMU_ID (1 << 2) + +#define MACH_MAC 3 +#define Q800_MAC_CPU_ID 2 + +#define VIA_BASE 0x50f00000 +#define SONIC_PROM_BASE 0x50f08000 +#define SONIC_BASE 0x50f0a000 +#define SCC_BASE 0x50f0c020 +#define ESP_BASE 0x50f10000 +#define ESP_PDMA 0x50f10100 +#define ASC_BASE 0x50F14000 +#define SWIM_BASE 0x50F1E000 +#define NUBUS_SUPER_SLOT_BASE 0x60000000 +#define NUBUS_SLOT_BASE 0xf0000000 + +/* the video base, whereas it a Nubus address, + * is needed by the kernel to have early display and + * thus provided by the bootloader + */ +#define VIDEO_BASE 0xf9001000 + +#define MAC_CLOCK 3686418 + +/* + * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip + * that performs a variety of functions (RAM management, clock generation,= ...). + * The GLUE chip receives interrupt requests from various devices, + * assign priority to each, and asserts one or more interrupt line to the + * CPU. + */ + +typedef struct { + M68kCPU *cpu; + uint8_t ipr; +} GLUEState; + +static void GLUE_set_irq(void *opaque, int irq, int level) +{ + GLUEState *s =3D opaque; + int i; + + if (level) { + s->ipr |=3D 1 << irq; + } else { + s->ipr &=3D ~(1 << irq); + } + + for (i =3D 7; i >=3D 0; i--) { + if ((s->ipr >> i) & 1) { + m68k_set_irq_level(s->cpu, i + 1, i + 25); + return; + } + } + m68k_set_irq_level(s->cpu, 0, 0); +} + +static void main_cpu_reset(void *opaque) +{ + M68kCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + cpu_reset(cs); + cpu->env.aregs[7] =3D ldl_phys(cs->as, 0); + cpu->env.pc =3D ldl_phys(cs->as, 4); +} + +static void q800_init(MachineState *machine) +{ + M68kCPU *cpu =3D NULL; + int linux_boot; + int32_t kernel_size; + uint64_t elf_entry; + char *filename; + int bios_size; + ram_addr_t initrd_base; + int32_t initrd_size; + MemoryRegion *rom; + MemoryRegion *ram; + ram_addr_t ram_size =3D machine->ram_size; + const char *kernel_filename =3D machine->kernel_filename; + const char *initrd_filename =3D machine->initrd_filename; + const char *kernel_cmdline =3D machine->kernel_cmdline; + hwaddr parameters_base; + CPUState *cs; + DeviceState *dev; + DeviceState *via_dev; + SysBusESPState *sysbus_esp; + ESPState *esp; + SysBusDevice *sysbus; + BusState *adb_bus; + NubusBus *nubus; + GLUEState *irq; + qemu_irq *pic; + + linux_boot =3D (kernel_filename !=3D NULL); + + /* init CPUs */ + cpu =3D M68K_CPU(cpu_create(machine->cpu_type)); + qemu_register_reset(main_cpu_reset, cpu); + + ram =3D g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abo= rt); + memory_region_add_subregion(get_system_memory(), 0, ram); + + /* IRQ Glue */ + + irq =3D g_new0(GLUEState, 1); + irq->cpu =3D cpu; + pic =3D qemu_allocate_irqs(GLUE_set_irq, irq, 8); + + /* VIA */ + + via_dev =3D qdev_create(NULL, TYPE_MAC_VIA); + qdev_init_nofail(via_dev); + sysbus =3D SYS_BUS_DEVICE(via_dev); + sysbus_mmio_map(sysbus, 0, VIA_BASE); + qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); + qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]); + + + adb_bus =3D qdev_get_child_bus(via_dev, "adb.0"); + dev =3D qdev_create(adb_bus, TYPE_ADB_KEYBOARD); + qdev_init_nofail(dev); + dev =3D qdev_create(adb_bus, TYPE_ADB_MOUSE); + qdev_init_nofail(dev); + + /* MACSONIC */ + + if (nb_nics > 1) { + error_report("q800 can only have one ethernet interface"); + exit(1); + } + + qemu_check_nic_model(&nd_table[0], "dp83932"); + + /* MacSonic driver needs an Apple MAC address + * Valid prefix are: + * 00:05:02 Apple + * 00:80:19 Dayna Communications, Inc. + * 00:A0:40 Apple + * 08:00:07 Apple + * (Q800 use the last one) + */ + nd_table[0].macaddr.a[0] =3D 0x08; + nd_table[0].macaddr.a[1] =3D 0x00; + nd_table[0].macaddr.a[2] =3D 0x07; + + dev =3D qdev_create(NULL, "dp8393x"); + qdev_set_nic_properties(dev, &nd_table[0]); + qdev_prop_set_uint8(dev, "it_shift", 2); + qdev_prop_set_bit(dev, "big_endian", true); + qdev_prop_set_ptr(dev, "dma_mr", get_system_memory()); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(sysbus, 0, SONIC_BASE); + sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); + sysbus_connect_irq(sysbus, 0, pic[2]); + + /* SCC */ + + dev =3D qdev_create(NULL, TYPE_ESCC); + qdev_prop_set_uint32(dev, "disabled", 0); + qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); + qdev_prop_set_uint32(dev, "it_shift", 1); + qdev_prop_set_bit(dev, "bit_swap", true); + qdev_prop_set_chr(dev, "chrA", serial_hd(0)); + qdev_prop_set_chr(dev, "chrB", serial_hd(1)); + qdev_prop_set_uint32(dev, "chnBtype", 0); + qdev_prop_set_uint32(dev, "chnAtype", 0); + qdev_init_nofail(dev); + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(sysbus, 0, pic[3]); + sysbus_connect_irq(sysbus, 1, pic[3]); + sysbus_mmio_map(sysbus, 0, SCC_BASE); + + /* SCSI */ + + dev =3D qdev_create(NULL, TYPE_ESP); + sysbus_esp =3D ESP_STATE(dev); + esp =3D &sysbus_esp->esp; + esp->dma_memory_read =3D NULL; + esp->dma_memory_write =3D NULL; + esp->dma_opaque =3D NULL; + sysbus_esp->it_shift =3D 4; + esp->dma_enabled =3D 1; + qdev_init_nofail(dev); + + sysbus =3D SYS_BUS_DEVICE(dev); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev, + "via2-irq", + VIA2_IRQ_SCSI_BIT= )); + sysbus_connect_irq(sysbus, 1, + qdev_get_gpio_in_named(via_dev, "via2-irq", + VIA2_IRQ_SCSI_DATA_BIT)); + sysbus_mmio_map(sysbus, 0, ESP_BASE); + sysbus_mmio_map(sysbus, 1, ESP_PDMA); + + scsi_bus_legacy_handle_cmdline(&esp->bus); + + /* SWIM floppy controller */ + + dev =3D qdev_create(NULL, TYPE_SWIM); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); + + /* NuBus */ + + dev =3D qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE); + + nubus =3D MAC_NUBUS_BRIDGE(dev)->bus; + + /* framebuffer in nubus slot #9 */ + + dev =3D qdev_create(BUS(nubus), TYPE_NUBUS_MACFB); + qdev_prop_set_uint32(dev, "width", graphic_width); + qdev_prop_set_uint32(dev, "height", graphic_height); + qdev_prop_set_uint8(dev, "depth", graphic_depth); + qdev_init_nofail(dev); + + cs =3D CPU(cpu); + if (linux_boot) { + uint64_t high; + kernel_size =3D load_elf(kernel_filename, NULL, NULL, NULL, + &elf_entry, NULL, &high, 1, + EM_68K, 0, 0); + if (kernel_size < 0) { + error_report("could not load kernel '%s'", kernel_filename); + exit(1); + } + stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ + parameters_base =3D (high + 1) & ~1; + + BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC); + BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID); + BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID); + BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID); + BOOTINFO1(cs->as, parameters_base, + BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ + BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM, + (graphic_height << 16) | graphic_width); + BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW, + (graphic_width * graphic_depth + 7) / 8); + BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE); + + if (kernel_cmdline) { + BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE, + kernel_cmdline); + } + + /* load initrd */ + if (initrd_filename) { + initrd_size =3D get_image_size(initrd_filename); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + initrd_filename); + exit(1); + } + + initrd_base =3D (ram_size - initrd_size) & TARGET_PAGE_MASK; + load_image_targphys(initrd_filename, initrd_base, + ram_size - initrd_base); + BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base, + initrd_size); + } else { + initrd_base =3D 0; + initrd_size =3D 0; + } + BOOTINFO0(cs->as, parameters_base, BI_LAST); + } else { + uint8_t *ptr; + /* allocate and load BIOS */ + rom =3D g_malloc(sizeof(*rom)); + memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE, + &error_abort); + if (bios_name =3D=3D NULL) { + bios_name =3D MACROM_FILENAME; + } + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + memory_region_set_readonly(rom, true); + memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); + + /* Load MacROM binary */ + if (filename) { + bios_size =3D load_image_targphys(filename, MACROM_ADDR, MACRO= M_SIZE); + g_free(filename); + } else { + bios_size =3D -1; + } + + /* Remove qtest_enabled() check once firmware files are in the tre= e */ + if (!qtest_enabled()) { + if (bios_size < 0 || bios_size > MACROM_SIZE) { + error_report("could not load MacROM '%s'", bios_name); + exit(1); + } + + ptr =3D rom_ptr(MACROM_ADDR, MACROM_SIZE); + stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ + stl_phys(cs->as, 4, + MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ + } + } +} + +static void q800_machine_init(MachineClass *mc) +{ + mc->desc =3D "Macintosh Quadra 800"; + mc->init =3D q800_init; + mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); + mc->max_cpus =3D 1; + mc->is_default =3D 0; + mc->block_default_type =3D IF_SCSI; +} + +DEFINE_MACHINE("q800", q800_machine_init) --=20 2.21.0