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[67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=apzfomw1VjtA9D2dSS+kh7pjyf0WWPI5EmgQzsdtCSA=; b=fsBXxwS5dG0WEWXBErwYpfFFEH6FcetgUzPrtuRHl9aM6jQbD5m9CFv6YCiAU9OdIL aUKtENARHTQhWIxh00b8O5uaO7o8GlVIDjlewrdY6loIahHlY45bntAWZEucxDBqHCVE OJji7oz8RHdoB/hW5vm3esfP7CWCGijdiUGYGR0mltXpZVK4ByGnvfHIAdl0XhblDmkL Dyhea7W/Gll6KLFVhNj6DUVTlXXUllV7zsidrDebwSB7PQUpFytpV6tr1a+mcm7kCuN/ xECVoaxa8m2QDPEva3FExA+jW85bBkkrm3nDXMECIr0pkaXspt/D3YogxKQyW8lDLeVu ek5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apzfomw1VjtA9D2dSS+kh7pjyf0WWPI5EmgQzsdtCSA=; b=hexsV6NnNlrTs82C/0aYoyq3qqNJcaeFat4+uiKS9XJyYFisNVOCy4aOQuv4RBksOW 8m/asLp2BLGCmoUYkKicSpCc+ZUhK0YP+vE17+y2uopvkKm5PLR0VEMtJGDcBg0SOFDY vxbZTBCQg9gx962QZnuAu2AMmRRGr2OwMjaTPyCI6O1BUg2TYu2VdenABAD39si8f9Yk nM0Lqi4l/9KUIMIpKsoMWEpkU/j2KMj9ZJl1cqwG4rW6rYtNwJNngfigC0ksKhR8Ym5h Mn4qDAds/ugceznAPMPTdp42NLgES/wn6XfKS/awmmtSezdUY3Popn6UHFnpV0ptnT9s i4yw== X-Gm-Message-State: APjAAAXk7Cf5VEA/DxKuN3Oo/fMhY59eMCF1ZIz0ggCnDYxiE8tOC7Ik yOcFVwwLdI3YsG9Jdy23kiHhasxr X-Google-Smtp-Source: APXvYqzZPHPMyiRFH4YJz31wYpmmDYNfEdgArRUnS9v3xeAw5g0NibNDViqxDIBzTSwfoO442lg6cg== X-Received: by 2002:a25:2e02:: with SMTP id u2mr59672832ybu.27.1560920705861; Tue, 18 Jun 2019 22:05:05 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:44 -0400 Message-Id: <20190619050447.22201-5-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 Subject: [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: add module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The risugen_x86.pm module contains most of the code specific to Intel i386 and x86_64 architectures. This commit also adds --x86_64 option, which enables emission of 64-bit (rather than 32-bit) assembly. Signed-off-by: Jan Bobek --- risugen | 6 +- risugen_x86.pm | 455 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 460 insertions(+), 1 deletion(-) create mode 100644 risugen_x86.pm diff --git a/risugen b/risugen index fe3d00e..09a702a 100755 --- a/risugen +++ b/risugen @@ -310,6 +310,7 @@ Valid options: Useful to test before support for FP is available. --sve : enable sve floating point --be : generate instructions in Big-Endian byte order (ppc64 o= nly). + --x86_64 : generate 64-bit (rather than 32-bit) x86 code. --help : print this message EOT } @@ -322,6 +323,7 @@ sub main() my $fp_enabled =3D 1; my $sve_enabled =3D 0; my $big_endian =3D 0; + my $is_x86_64 =3D 0; my ($infile, $outfile); =20 GetOptions( "help" =3D> sub { usage(); exit(0); }, @@ -338,6 +340,7 @@ sub main() }, "be" =3D> sub { $big_endian =3D 1; }, "no-fp" =3D> sub { $fp_enabled =3D 0; }, + "x86_64" =3D> sub { $is_x86_64 =3D 1; }, "sve" =3D> sub { $sve_enabled =3D 1; }, ) or return 1; # allow "--pattern re,re" and "--pattern re --pattern re" @@ -372,7 +375,8 @@ sub main() 'keys' =3D> \@insn_keys, 'arch' =3D> $full_arch[0], 'subarch' =3D> $full_arch[1] || '', - 'bigendian' =3D> $big_endian + 'bigendian' =3D> $big_endian, + 'x86_64' =3D> $is_x86_64 ); =20 write_test_code(\%params); diff --git a/risugen_x86.pm b/risugen_x86.pm new file mode 100644 index 0000000..879d6e1 --- /dev/null +++ b/risugen_x86.pm @@ -0,0 +1,455 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +##########################################################################= ##### + +# risugen_x86 -- risugen module for Intel i386/x86_64 architectures +package risugen_x86; + +use strict; +use warnings; + +use risugen_common; +use risugen_x86_asm; +use risugen_x86_emit; + +require Exporter; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw(write_test_code); + +use constant { + RISUOP_COMPARE =3D> 0, # compare registers + RISUOP_TESTEND =3D> 1, # end of test, stop + RISUOP_SETMEMBLOCK =3D> 2, # eax is address of memory block (81= 92 bytes) + RISUOP_GETMEMBLOCK =3D> 3, # add the address of memory block to= eax + RISUOP_COMPAREMEM =3D> 4, # compare memory block + + # Maximum alignment restriction permitted for a memory op. + MAXALIGN =3D> 64, + MEMBLOCK_LEN =3D> 8192, +}; + +my $periodic_reg_random =3D 1; +my $is_x86_64 =3D 0; + +sub write_risuop($) +{ + my ($op) =3D @_; + + write_insn(opcode =3D> X86OP_UD1, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> REG_EAX, + rm =3D> $op}); +} + +sub write_mov_rr($$) +{ + my ($r1, $r2) =3D @_; + + my %insn =3D (opcode =3D> X86OP_MOV, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> ($r1 & 0x7), + rm =3D> ($r2 & 0x7)}); + + $insn{rex}{w} =3D 1 if $is_x86_64; + $insn{rex}{r} =3D 1 if $r1 >=3D 8; + $insn{rex}{b} =3D 1 if $r2 >=3D 8; + + write_insn(%insn); +} + +sub write_mov_reg_imm($$) +{ + my ($reg, $imm) =3D @_; + + my %insn =3D (opcode =3D> {value =3D> 0xB8 | ($reg & 0x7), len =3D> 1}, + imm =3D> {value =3D> $imm, len =3D> $is_x86_64 ? 8 : 4}); + + $insn{rex}{w} =3D 1 if $is_x86_64; + $insn{rex}{b} =3D 1 if $reg >=3D 8; + + write_insn(%insn); +} + +sub write_random_regdata() +{ + my $reg_cnt =3D $is_x86_64 ? 16 : 8; + my $bitlen =3D $is_x86_64 ? 64 : 32; + + # initialize flags register + write_insn(opcode =3D> X86OP_XOR, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> REG_EAX, + rm =3D> REG_EAX}); + write_insn(opcode =3D> X86OP_SAHF); + + # general purpose registers + for (my $reg =3D 0; $reg < $reg_cnt; $reg++) { + if ($reg !=3D REG_ESP) { + my $imm =3D randint_constr(bitlen =3D> $bitlen, signed =3D> 1); + write_mov_reg_imm($reg, $imm); + } + } +} + +sub write_random_datablock($) +{ + my ($datalen) =3D @_; + + # Write a block of random data, $datalen bytes long, aligned + # according to MAXALIGN, and load its address into EAX/RAX. + + $datalen +=3D MAXALIGN - 1; + + # First, load current EIP/RIP into EAX/RAX. Easy to do on x86_64 + # thanks to RIP-relative addressing, but on i386 we need to play + # some well-known tricks with CALL instruction. + if ($is_x86_64) { + # 4-byte AND + 5-byte JMP + my $disp32 =3D 4 + 5 + (MAXALIGN - 1); + my $reg =3D REG_EAX; + + write_insn(rex =3D> {w =3D> 1}, + opcode =3D> X86OP_LEA, + modrm =3D> {mod =3D> MOD_INDIRECT, + reg =3D> $reg, rm =3D> REG_EBP}, + disp =3D> {value =3D> $disp32, len =3D> 4}); + + write_insn(rex =3D> {w =3D> 1}, + opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 4, rm =3D> $reg}, + imm =3D> {value =3D> ~(MAXALIGN - 1), + len =3D> 1}); + + } else { + # 1-byte POP + 3-byte ADD + 3-byte AND + 5-byte JMP + my $imm8 =3D 1 + 3 + 3 + 5 + (MAXALIGN - 1); + my $reg =3D REG_EAX; + + # displacement =3D next instruction + write_insn(opcode =3D> X86OP_CALL, + imm =3D> {value =3D> 0x00000000, len =3D> 4}); + + write_insn(opcode =3D> {value =3D> 0x58 | ($reg & 0x7), + len =3D> 1}); + + write_insn(opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 0, rm =3D> $reg}, + imm =3D> {value =3D> $imm8, len =3D> 1}); + + write_insn(opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 4, rm =3D> $reg}, + imm =3D> {value =3D> ~(MAXALIGN - 1), + len =3D> 1}); + } + + # JMP over the data blob. + write_insn(opcode =3D> X86OP_JMP, + imm =3D> {value =3D> $datalen, len =3D> 4}); + + # Generate the random data + for (my $w =3D 8; 0 < $w; $w /=3D 2) { + for (; $w <=3D $datalen; $datalen -=3D $w) { + insnv(%{rand_insn_imm(size =3D> $w)}); + } + } +} + +sub write_random_xmmdata() +{ + my $xmm_cnt =3D $is_x86_64 ? 16 : 8; + my $xmm_len =3D 16; + my $datalen =3D $xmm_cnt * $xmm_len; + + # Generate random data blob + write_random_datablock($datalen); + + # Load the random data into XMM regs. + for (my $xmm_reg =3D 0; $xmm_reg < $xmm_cnt; $xmm_reg++) { + my %insn =3D (opcode =3D> X86OP_MOVAPS, + modrm =3D> {mod =3D> MOD_INDIRECT_DISP32, + reg =3D> ($xmm_reg & 0x7), + rm =3D> REG_EAX}, + disp =3D> {value =3D> $xmm_reg * $xmm_len, + len =3D> 4}); + + $insn{rex}{r} =3D 1 if $xmm_reg >=3D 8; + + write_insn(%insn); + } +} + +sub write_memblock_setup() +{ + # Generate random data blob + write_random_datablock(MEMBLOCK_LEN); + # Pointer is in EAX/RAX; set the memblock + write_risuop(RISUOP_SETMEMBLOCK); +} + +sub write_random_register_data() +{ + write_random_xmmdata(); + write_random_regdata(); + write_risuop(RISUOP_COMPARE); +} + +sub rand_insn_imm(%) +{ + my (%args) =3D @_; + + return { + value =3D> randint_constr(bitlen =3D> ($args{size} * 8), signed = =3D> 1), + len =3D> $args{size} + }; +} + +sub rand_insn_opcode($) +{ + # Given an instruction-details array, generate an instruction + my ($rec) =3D @_; + my $insnname =3D $rec->{name}; + my $insnwidth =3D $rec->{width}; + + my $constraintfailures =3D 0; + + INSN: while(1) { + my $opcode =3D randint_constr(bitlen =3D> 32, + fixedbits =3D> $rec->{fixedbits}, + fixedbitmask =3D> $rec->{fixedbitmask}= ); + + my $constraint =3D $rec->{blocks}{"constraints"}; + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v =3D eval_with_fields($insnname, $opcode, $rec, "constrai= nts", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insn= name constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures =3D 0; + + return { + value =3D> $opcode >> (32 - $insnwidth), + len =3D> $insnwidth / 8 + }; + } +} + +sub rand_insn_modrm($$) +{ + my ($opts, $insn) =3D @_; + my $modrm; + + while (1) { + $modrm =3D rand_fill({mod =3D> {bitlen =3D> 2}, + reg =3D> {bitlen =3D> 3}, + rm =3D> {bitlen =3D> 3}}, + $opts); + + if ($modrm->{mod} !=3D MOD_DIRECT) { + # Displacement only; we cannot use this since we + # don't know absolute address of the memblock. + next if $modrm->{mod} =3D=3D MOD_INDIRECT && $modrm->{rm} =3D= =3D REG_EBP; + + if ($modrm->{rm} =3D=3D REG_ESP) { + # SIB byte present + my $sib =3D rand_fill({ss =3D> {bitlen =3D> 2}, + index =3D> {bitlen =3D> 3}, + base =3D> {bitlen =3D> 3}}, {}); + + # We cannot modify ESP/RSP during the tests + next if $sib->{base} =3D=3D REG_ESP; + + # When base and index register are the same, + # computing the correct memblock addresses and + # offsets gets way too complicated... + next if $sib->{base} =3D=3D $sib->{index}; + + # No base register + next if $modrm->{mod} =3D=3D MOD_INDIRECT && $sib->{base} = =3D=3D REG_EBP; + + $insn->{sib} =3D $sib; + } + + $insn->{disp} =3D rand_insn_imm(size =3D> 1) + if $modrm->{mod} =3D=3D MOD_INDIRECT_DISP8; + + $insn->{disp} =3D rand_insn_imm(size =3D> 4) + if $modrm->{mod} =3D=3D MOD_INDIRECT_DISP32; + } + + $insn->{modrm} =3D $modrm; + last; + } +} + +sub rand_insn_rex($$) +{ + my ($opts, $insn) =3D @_; + + $opts->{w} =3D 0 unless defined $opts->{w}; + $opts->{x} =3D 0 unless defined $opts->{x} || defined $insn->{sib}; + + my $rex =3D rand_fill({w =3D> {bitlen =3D> 1}, + r =3D> {bitlen =3D> 1}, + b =3D> {bitlen =3D> 1}, + x =3D> {bitlen =3D> 1}}, + $opts); + + $insn->{rex} =3D $rex + if $rex->{w} || $rex->{r} || $rex->{b} || $rex->{x}; +} + +sub write_mem_getoffset($$) +{ + my ($opts, $insn) =3D @_; + my $offset, my $index; + + $opts->{size} =3D 0 unless defined $opts->{size}; + $opts->{align} =3D 1 unless defined $opts->{align}; + + if (!defined $opts->{base} + && defined $insn->{modrm} + && $insn->{modrm}{mod} !=3D MOD_DIRECT) { + + $opts->{base} =3D (defined $insn->{sib} + ? $insn->{sib}{base} + : $insn->{modrm}{rm}); + + if ($insn->{modrm}{mod} =3D=3D MOD_INDIRECT && $opts->{base} =3D= =3D REG_EBP) { + delete $opts->{base}; # No base register + } else { + $opts->{base} |=3D $insn->{rex}{b} << 3 if defined $insn->{rex= }; + $opts->{base} |=3D (!$insn->{vex}{b}) << 3 if defined $insn->{= vex}; + } + } + + if (!defined $opts->{index} && defined $insn->{sib}) { + $opts->{index} =3D $insn->{sib}{index}; + $opts->{index} |=3D $insn->{rex}{x} << 3 if defined $insn->{rex}; + $opts->{index} |=3D (!$insn->{vex}{x}) << 3 if defined $insn->{vex= }; + delete $opts->{index} if $opts->{index} =3D=3D REG_ESP; # ESP mean= s "none" + } + + $opts->{ss} =3D $insn->{sib}{ss} if !defined $opts->{ss} && defined $i= nsn->{sib}; + $opts->{disp} =3D $insn->{disp} if !defined $opts->{disp} && defined $= insn->{disp}; + + $offset =3D int(rand(MEMBLOCK_LEN - $opts->{size})); + $offset &=3D ~($opts->{align} - 1); + + $offset -=3D $opts->{disp}{value} if defined $opts->{disp}; + + if (defined $opts->{index}) { + $index =3D randint_constr(bitlen =3D> 32, signed =3D> 1); + $offset -=3D $index * (1 << $opts->{ss}); + } + + if (defined $opts->{base} && defined $offset) { + write_mov_reg_imm(REG_EAX, $offset); + write_risuop(RISUOP_GETMEMBLOCK); + write_mov_rr($opts->{base}, REG_EAX); + } + if (defined $opts->{index} && defined $index) { + write_mov_reg_imm($opts->{index}, $index); + } +} + +sub gen_one_insn($) +{ + my ($rec) =3D @_; + my $insn; + + $insn->{opcode} =3D rand_insn_opcode($rec); + my $opts =3D parse_emitblock($rec, $insn); + + # Operation with a ModR/M byte can potentially use a memory + # operand + $opts->{mem} =3D {} + unless defined $opts->{mem} || !defined $opts->{modrm}; + + # If none of REX/VEX/EVEX are specified, default to REX + $opts->{rex} =3D {} + unless defined $opts->{rex} || defined $opts->{vex} || defined $op= ts->{evex}; + + # REX requires x86_64 + delete $opts->{rex} + unless $is_x86_64; + + $insn->{rep} =3D $opts->{rep} if defined $opts->{rep}; + $insn->{repne} =3D $opts->{repne} if defined $opts->{repne}; + $insn->{data16} =3D $opts->{data16} if defined $opts->{data16}; + + rand_insn_modrm($opts->{modrm}, $insn) if defined $opts->{modrm}; + + # TODO rand_insn_vex($opts->{vex}, $insn) if defined $opts->{vex}; + # TODO rand_insn_evex($opts->{evex}, $insn) if defined $opts->{evex}; + rand_insn_rex($opts->{rex}, $insn) if defined $opts->{rex}; + + $insn->{imm} =3D rand_insn_imm(%{$opts->{imm}}) if defined $opts->{imm= }; + + write_mem_getoffset($opts->{mem}, $insn); + write_insn(%{$insn}); +} + +sub write_test_code($) +{ + my ($params) =3D @_; + + my $numinsns =3D $params->{ 'numinsns' }; + my $outfile =3D $params->{ 'outfile' }; + + my %insn_details =3D %{ $params->{ 'details' } }; + my @keys =3D @{ $params->{ 'keys' } }; + + $is_x86_64 =3D $params->{ 'x86_64' }; + + open_bin($outfile); + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + write_memblock_setup(); + + # memblock setup doesn't clean its registers, so this must come afterw= ards. + write_random_register_data(); + + for my $i (1..$numinsns) { + my $insn_enc =3D $keys[int rand (@keys)]; + # my $forcecond =3D (rand() < $condprob) ? 1 : 0; + gen_one_insn($insn_details{$insn_enc}); + write_risuop(RISUOP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) =3D=3D 0) { + write_random_register_data(); + } + progress_update($i); + } + write_risuop(RISUOP_TESTEND); + progress_end(); + close_bin(); +} + +1; --=20 2.20.1