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[67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.02 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E+nG+A7eIMJ+oEMZ98jk8lnEytaL2DnbYAnCvuy+ey8=; b=tRlOOJu/44ZdoANgiGx9LaHAYE+sQ6IlK4nos+/S+iriipl1VVZAxp69FMe8N7Xsn4 skvNznWNlKeBFNjgmZFP6g+i/XWjDhm0wkHHs4HFqxcnVinR2Cme9NVt8XksfACINudD r0HNmTw+wUPeeahIjl7Jlga/mowljVStdbMjKsV0D8oRlDkLRjwgqy1fE5hCr2DZGYja 7VPMVciQ75wND2JneK95srUXFL3PsrMl3+uhsm4FYoOaFvDfQnDa3py59fuUuJhfILYc HroesAq6x61Dvej0sdMGtxAXAzJldq9D1vLhUwD9Pd+qYztGzIAcod2DsGvpYCJq3poM 2Nrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E+nG+A7eIMJ+oEMZ98jk8lnEytaL2DnbYAnCvuy+ey8=; b=hbz0Sn9B4012Pe3rCWglQ61HO9Mf5Wgu8CSVYUUWdS08YM2LUWyjy4V+htRzQaz2Iu lJmBS9Vkbj33LsXvMYmpdhE2djiSMDA0scekAo9l0dcWP30rIymuu3JS5fRgGYQeTyaj I44EZfed3v8dsS5AinqpxYE0IYpeNrEDCRSntVIiE+DyMVWgI+GZImn9np15gOGi3JgF WNsN/aylFaB0KnalEv5r1cQae0Idd6qLGmY2Ypl3UGAHNQPT5qKLVDeB0MfuQS6QH4Ql 7DajY2l7Wb3Y+UWwOqnlP0FwbwNrxfC71So6GNXhSOsro1WMwigI9e2H1LzA7X0uxn45 7ZsQ== X-Gm-Message-State: APjAAAWrS90tdIT11qY0kJWcUotVrIgUx7S+4Xx8jThrZEsVp0xTEVKo HdYW3JRxVOwvPXg5JzMh/Wy/8/Io X-Google-Smtp-Source: APXvYqxM9T5OCojbabYUp4yv5z8fLTBG83tyvLnCZ8JO27X11qtMLWxRMVStWUqA10Gyi1eIz+hBIg== X-Received: by 2002:a25:4d5:: with SMTP id 204mr21735719ybe.112.1560920703342; Tue, 18 Jun 2019 22:05:03 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:41 -0400 Message-Id: <20190619050447.22201-2-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU RFC PATCH v1 1/7] risugen_common: add insnv, randint_constr, rand_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add three common utility functions: - insnv allows emitting variable-length instructions in little-endian or big-endian byte order; it subsumes functionality of former insn16() and insn32() functions. - randint_constr allows generating random integers according to several constraints passed as arguments. - rand_fill uses randint_constr to fill a given hash with (optionally constrained) random values. Signed-off-by: Jan Bobek --- risugen_common.pm | 101 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 95 insertions(+), 6 deletions(-) diff --git a/risugen_common.pm b/risugen_common.pm index 71ee996..98b9170 100644 --- a/risugen_common.pm +++ b/risugen_common.pm @@ -23,7 +23,8 @@ BEGIN { require Exporter; =20 our @ISA =3D qw(Exporter); - our @EXPORT =3D qw(open_bin close_bin set_endian insn32 insn16 $byteco= unt + our @EXPORT =3D qw(open_bin close_bin set_endian insn32 insn16 + $bytecount insnv randint_constr rand_fill progress_start progress_update progress_end eval_with_fields is_pow_of_2 sextract ctz dump_insn_details); @@ -37,7 +38,7 @@ my $bigendian =3D 0; # (default is little endian, 0). sub set_endian { - $bigendian =3D @_; + ($bigendian) =3D @_; } =20 sub open_bin @@ -52,18 +53,106 @@ sub close_bin close(BIN) or die "can't close output file: $!"; } =20 +sub insnv(%) +{ + my (%args) =3D @_; + + # Default to big-endian order, so that the instruction bytes are + # emitted in the same order as they are written in the + # configuration file. + $args{bigendian} =3D 1 unless defined $args{bigendian}; + + while (0 < $args{len}) { + my $format; + my $len; + + if ($args{len} >=3D 8) { + $format =3D "Q"; + $len =3D 8; + } elsif ($args{len} >=3D 4) { + $format =3D "L"; + $len =3D 4; + } elsif ($args{len} >=3D 2) { + $format =3D "S"; + $len =3D 2; + } else { + $format =3D "C"; + $len =3D 1; + } + + $format .=3D ($args{bigendian} ? ">" : "<") if $len > 1; + + my $bitlen =3D 8 * $len; + my $bitmask =3D (1 << $bitlen) - 1; + my $value =3D ($args{bigendian} + ? ($args{value} >> (8 * $args{len} - $bitlen)) + : $args{value}); + + print BIN pack($format, $value & $bitmask); + $bytecount +=3D $len; + + $args{len} -=3D $len; + $args{value} >>=3D $bitlen unless $args{bigendian}; + } +} + sub insn32($) { my ($insn) =3D @_; - print BIN pack($bigendian ? "N" : "V", $insn); - $bytecount +=3D 4; + insnv(value =3D> $insn, len =3D> 4, bigendian =3D> $bigendian); } =20 sub insn16($) { my ($insn) =3D @_; - print BIN pack($bigendian ? "n" : "v", $insn); - $bytecount +=3D 2; + insnv(value =3D> $insn, len =3D> 2, bigendian =3D> $bigendian); +} + +sub randint_constr(%) +{ + my (%args) =3D @_; + my $bitlen =3D $args{bitlen}; + my $halfrange =3D 1 << ($bitlen - 1); + + while (1) { + my $value =3D int(rand(2 * $halfrange)); + $value -=3D $halfrange if defined $args{signed} && $args{signed}; + $value &=3D ~$args{fixedbitmask} if defined $args{fixedbitmask}; + $value |=3D $args{fixedbits} if defined $args{fixedbits}; + + if (defined $args{constraint}) { + if (!($args{constraint} >> 63)) { + $value =3D $args{constraint}; + } elsif ($value =3D=3D ~$args{constraint}) { + next; + } + } + + return $value; + } +} + +sub rand_fill($$) +{ + my ($target, $constraints) =3D @_; + + for (keys %{$target}) { + my %args =3D (bitlen =3D> $target->{$_}{bitlen}); + + $args{fixedbits} =3D $target->{$_}{fixedbits} + if defined $target->{$_}{fixedbits}; + $args{fixedbitmask} =3D $target->{$_}{fixedbitmask} + if defined $target->{$_}{fixedbitmask}; + $args{signed} =3D $target->{$_}{signed} + if defined $target->{$_}{signed}; + + $args{constraint} =3D $constraints->{$_} + if defined $constraints->{$_}; + + $target->{$_} =3D randint_constr(%args); + } + + return $target; } =20 # Progress bar implementation --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1560920883; cv=none; d=zoho.com; s=zohoarc; b=gdkC9HIsJKL8NC97CpyEsrqoADIK8OwQEdHKOhZSj8faxnUqqfCHxYenpKB09L62PI62iJGfN0/0dAF8uW/k+geo8dRy+S8fOq9abtuWOquxnXHQsX+Ey1L7a64b67VZHqHfutBqRSiR+TUwsGw3L3iwF/Qcdf7TxiZDmT4JGAg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560920883; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GrCB6QTzLlLkXLJ1pjbX8m/2ezWqViG2Pyz6v1pzFWQ=; b=LgIDAkJI7+9f/vgGznyF3eaueccT++dWqjQqMaBY48eKd3+I5tNmo3J9YfbrD6Q7d1cbz/miWe3yA888u13w22/9DLARKlngyKGlKSAEo2AJbzla6DRRTkyxfO7kcOAVkjXDwR4kil2nari6t91RyOFV0JqeHuO1w5dsFdCbLvg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560920883014121.5340183626588; Tue, 18 Jun 2019 22:08:03 -0700 (PDT) Received: from localhost ([::1]:35164 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSoz-0005yg-6Y for importer@patchew.org; Wed, 19 Jun 2019 01:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34413) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSmT-0003u7-96 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdSmP-0001dj-OW for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:07 -0400 Received: from mail-yb1-xb43.google.com ([2607:f8b0:4864:20::b43]:45564) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdSmO-0001cn-Ry for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:05 -0400 Received: by mail-yb1-xb43.google.com with SMTP id v104so7061827ybi.12 for ; Tue, 18 Jun 2019 22:05:04 -0700 (PDT) Received: from localhost.localdomain (67-9-99-67.biz.bhn.net. [67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.03 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GrCB6QTzLlLkXLJ1pjbX8m/2ezWqViG2Pyz6v1pzFWQ=; b=AO45s9p6s4eOYyANLVLC5l1Kz2KWIq2WNrzTPzaz9UWWN/FxCjus/wKsDBvBYIsgj8 OCqU4gw+DPdFQ8bCIr4K86nMjhv7zpY9Es3A+xr/p2hZj6X7L9xJodfPXzRiv5cKZJGQ 14ql2ekNJsb90+K/n0hQGbcecwTQIxn15QMeTbn4Ei0HFj6pXRhebCELmrX2EY2pmL0z 65dCYXkwAfjTpiU3w+WF+GrzKou6nCr26McAEfs4te9s43D/oj4Gld0mfKkhaKpfdwNc fZsn5XoXrnZtNyFCiMsERkrd2YhjH7Sr7hv5JOObA9VpYrIK1Xoy46FslEME2J7fzZeP 8FhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GrCB6QTzLlLkXLJ1pjbX8m/2ezWqViG2Pyz6v1pzFWQ=; b=iFvAQuc2I3n1cnsFhLj6Wcwt/CYa28M5EvuNbkqxTuM4srRY+qxBEE8EqdDYRzcM+w v886tVsclZ9sBAEtE1OzFBciCkXaRPGToGUUAU8dWzzqwY4svVxmkwvW/3wD37K5wA/C ORQuxPApZdRDscUxOOssQx/QRTamR7Gb4h15VTVCS1uuAViFkGiLK+cwHNOpSoQjQdvI RyJ2WnRPMDBv8d/cWDPDIFkcq+A1UcqL8ZbzK9EwqMJjDdrJsZiSLZxJmahZRFXZACf1 QxTTDsBv4Eim2FRkLjAEjcl5fzUV9qgJGWpuB/niAFpSf1Rcjxa/UgOYnH8lf5AeDNaJ He6g== X-Gm-Message-State: APjAAAW2ylXiPaJbf4AZxklop9vvX7XdICVAtn1qYRa1au3A0a/3cHuN Z6aDZm4sGnX079ATxhFs+K4DVQWJ X-Google-Smtp-Source: APXvYqyuJwV8AU6a9idVKcNd/y06SM4Cjr4P5SAyivrdgzElTVdShhTP731icKt8g8BxGnrjD5pl8g== X-Received: by 2002:a5b:2:: with SMTP id a2mr59124816ybp.244.1560920704043; Tue, 18 Jun 2019 22:05:04 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:42 -0400 Message-Id: <20190619050447.22201-3-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 Subject: [Qemu-devel] [RISU RFC PATCH v1 2/7] risugen_x86_asm: add module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The module risugen_x86_asm.pm exports several constants and the function write_insn, which work in tandem to allow emission of x86 instructions in more clear and structured manner. Signed-off-by: Jan Bobek --- risugen_x86_asm.pm | 186 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 risugen_x86_asm.pm diff --git a/risugen_x86_asm.pm b/risugen_x86_asm.pm new file mode 100644 index 0000000..b10d3e7 --- /dev/null +++ b/risugen_x86_asm.pm @@ -0,0 +1,186 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +##########################################################################= ##### + +# risugen_x86_asm -- risugen_x86's helper module for x86 assembly +package risugen_x86_asm; + +use strict; +use warnings; + +use risugen_common; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw( + write_insn + REG_EAX REG_ECX REG_EDX REG_EBX REG_ESP REG_EBP REG_ESI REG_EDI + MOD_INDIRECT MOD_INDIRECT_DISP8 MOD_INDIRECT_DISP32 MOD_DIRECT + X86PFX_DATA16 X86PFX_REPNE X86PFX_REP + X86OP_LEA X86OP_XOR X86OP_ALU_imm8 X86OP_MOV X86OP_SAHF X86OP_CALL + X86OP_JMP X86OP_UD1 X86OP_MOVAPS + ); + +use constant { + REG_EAX =3D> 0, + REG_ECX =3D> 1, + REG_EDX =3D> 2, + REG_EBX =3D> 3, + REG_ESP =3D> 4, + REG_EBP =3D> 5, + REG_ESI =3D> 6, + REG_EDI =3D> 7, + + MOD_INDIRECT =3D> 0b00, + MOD_INDIRECT_DISP8 =3D> 0b01, + MOD_INDIRECT_DISP32 =3D> 0b10, + MOD_DIRECT =3D> 0b11, + + X86PFX_DATA16 =3D> {value =3D> 0x66, len =3D> 1}, + X86PFX_REPNE =3D> {value =3D> 0xF2, len =3D> 1}, + X86PFX_REP =3D> {value =3D> 0xF3, len =3D> 1}, + + X86OP_LEA =3D> {value =3D> 0x8D, len =3D> 1}, + X86OP_XOR =3D> {value =3D> 0x33, len =3D> 1}, + X86OP_ALU_imm8 =3D> {value =3D> 0x83, len =3D> 1}, + X86OP_MOV =3D> {value =3D> 0x8B, len =3D> 1}, + X86OP_SAHF =3D> {value =3D> 0x9E, len =3D> 1}, + X86OP_CALL =3D> {value =3D> 0xE8, len =3D> 1}, + X86OP_JMP =3D> {value =3D> 0xE9, len =3D> 1}, + + X86OP_UD1 =3D> {value =3D> 0x0FB9, len =3D> 2}, + X86OP_MOVAPS =3D> {value =3D> 0x0F28, len =3D> 2}, +}; + +sub rex_encode(%) +{ + my (%args) =3D @_; + + $args{w} =3D 0 unless defined $args{w}; + $args{r} =3D 0 unless defined $args{w}; + $args{x} =3D 0 unless defined $args{w}; + $args{b} =3D 0 unless defined $args{w}; + + return (value =3D> 0x40 + | (($args{w} ? 1 : 0) << 3) + | (($args{r} ? 1 : 0) << 2) + | (($args{x} ? 1 : 0) << 1) + | ($args{b} ? 1 : 0), + len =3D> 1); +} + +sub modrm_encode(%) +{ + my (%args) =3D @_; + + die "MOD field out-of-range: $args{mod}" + unless 0 <=3D $args{mod} && $args{mod} <=3D 3; + die "REG field out-of-range: $args{reg}" + unless 0 <=3D $args{reg} && $args{reg} <=3D 7; + die "RM field out-of-range: $args{rm}" + unless 0 <=3D $args{rm} && $args{rm} <=3D 7; + + return (value =3D> + ($args{mod} << 6) + | ($args{reg} << 3) + | $args{rm}, + len =3D> 1); +} + +sub sib_encode(%) +{ + my (%args) =3D @_; + + die "SS field out-of-range: $args{ss}" + unless 0 <=3D $args{ss} && $args{ss} <=3D 3; + die "INDEX field out-of-range: $args{index}" + unless 0 <=3D $args{index} && $args{index} <=3D 7; + die "BASE field out-of-range: $args{base}" + unless 0 <=3D $args{base} && $args{base} <=3D 7; + + return (value =3D> + ($args{ss} << 6) + | ($args{index} << 3) + | $args{base}, + len =3D> 1); +} + +sub write_insn(%) +{ + my (%insn) =3D @_; + + my @tokens; + push @tokens, "EVEX" if defined $insn{evex}; + push @tokens, "VEX" if defined $insn{vex}; + push @tokens, "REP" if defined $insn{rep}; + push @tokens, "REPNE" if defined $insn{repne}; + push @tokens, "DATA16" if defined $insn{data16}; + push @tokens, "REX" if defined $insn{rex}; + push @tokens, "OP" if defined $insn{opcode}; + push @tokens, "MODRM" if defined $insn{modrm}; + push @tokens, "SIB" if defined $insn{sib}; + push @tokens, "DISP" if defined $insn{disp}; + push @tokens, "IMM" if defined $insn{imm}; + push @tokens, "END"; + + # (EVEX | VEX | ((REP | REPNE)? DATA16? REX?)) OP (MODRM SIB? DISP?)? = IMM? END + + my $token =3D shift @tokens; + if ($token eq "EVEX") { + insnv(evex_encode(%{$insn{evex}})); + $token =3D shift @tokens; + } elsif ($token eq "VEX") { + insnv(vex_encode(%{$insn{vex}})); + $token =3D shift @tokens; + } else { + if ($token eq "REP") { + insnv(%{&X86PFX_REP}); + $token =3D shift @tokens; + } elsif ($token eq "REPNE") { + insnv(%{&X86PFX_REPNE}); + $token =3D shift @tokens; + } + if ($token eq "DATA16") { + insnv(%{&X86PFX_DATA16}); + $token =3D shift @tokens; + } + if ($token eq "REX") { + insnv(rex_encode(%{$insn{rex}})); + $token =3D shift @tokens; + } + } + + die "Unexpected instruction tokens where OP expected: $token @tokens\n" + unless $token eq "OP"; + + insnv(%{$insn{opcode}}); + $token =3D shift @tokens; + + if ($token eq "MODRM") { + insnv(modrm_encode(%{$insn{modrm}})); + $token =3D shift @tokens; + + if ($token eq "SIB") { + insnv(sib_encode(%{$insn{sib}})); + $token =3D shift @tokens; + } + if ($token eq "DISP") { + insnv(%{$insn{disp}}, bigendian =3D> 0); + $token =3D shift @tokens; + } + } + if ($token eq "IMM") { + insnv(%{$insn{imm}}, bigendian =3D> 0); + $token =3D shift @tokens; + } + + die "Unexpected junk tokens at the end of instruction: $token @tokens\= n" + unless $token eq "END"; +} --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1560920873; cv=none; d=zoho.com; s=zohoarc; b=Q0GPBwg9esDwyFEEf+eeBoqN5QHHxJiVJKZ+tZZEvs0Vcqw3ta46Mpxn1oqMK4bKcfcdRCcd7qFZ2OgH/CMfF6hWx6vjy62aLNADRHQPVQalBEQSjlisTKVSj0TX1LMMw5N/c15ArA8VomJL/kiKCHUkYfNT8Z++8MfI5RqV2iQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560920873; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2AL1b+nMXBf7cujyRtXqMsJ+EqszwrRf6hdCVJcNcgk=; b=hq0FXtDtoRPvUS3w8G6dX4vhEa/1/S/vmgl8wCrK1ArW3jTl0ZqZ9sot2bhBGZ5oZMSnmwkyd3/aNvHPoB4IADVWB3swyoDDQcOsGoils6WGGTFD7wAHc0Gj/A79p6Yoi40Tw6saZgNWhcWc3A1s2Z55Jh2UBInEe6V5YWXwri8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560920873216207.00794574370946; Tue, 18 Jun 2019 22:07:53 -0700 (PDT) Received: from localhost ([::1]:35160 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSox-0005vu-R1 for importer@patchew.org; Wed, 19 Jun 2019 01:07:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34420) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSmT-0003uC-Ie for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdSmR-0001eo-Lv for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:09 -0400 Received: from mail-yb1-xb44.google.com ([2607:f8b0:4864:20::b44]:45565) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdSmP-0001dC-Ob for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:05 -0400 Received: by mail-yb1-xb44.google.com with SMTP id v104so7061841ybi.12 for ; Tue, 18 Jun 2019 22:05:05 -0700 (PDT) Received: from localhost.localdomain (67-9-99-67.biz.bhn.net. [67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2AL1b+nMXBf7cujyRtXqMsJ+EqszwrRf6hdCVJcNcgk=; b=aMb2IimZL2r6VQHh2dR+iKTXQXASyiRNX6y/XDqg2TNVsOxrjyONpkUGNZm37+cW3V Kchl5gvfDBwfDF8ZkQR0Nqiv5Mpvc7yo4OmYX+//t92yQGEjkCOeYJbjv2SiSKDnBJtA Rv/t85GnGnZfWVem42i7OxUkr/WRvjgwUFv9phAea6mMC09lLTKiTHQRdq8vETYw2xF5 Ej2JI1366Rf1zoQIzjkS+XRbvLW9yt2ncHvN0JU1p7rk9g6a7acetr3hxcB4ipEq5icB Rl49pH5zCKcc88P4ljuNyfv5p5k4Fd/cVjoEMilCHeNKv+IFl4bpTHGUVJKeqHELcccL 0dyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2AL1b+nMXBf7cujyRtXqMsJ+EqszwrRf6hdCVJcNcgk=; b=U6p/oz2Ej0QxvgtTOtL2c8CvBaF5dTpzpmLrMHHjx2Q+yJT5AN203KjsA59FZE6NUH 5MGsMGdezWZvVZIhEr1F93ph8C88V9aImxm+qr75yj6lKduynnnoO/TA8HamBE6xSi5H 5c+4L3fpB0fwyiMPhCn6LPoOxUx1WPs8w7vLcmcndkdxbzAQzsf8QCv8ou43oMkw/XSO rYtpvvRZBz9Iw4u95aXIjFU/5mhTsw07ogCwibUdeVBykj70LsoNIjIlUf+ukE00FtYl WoUP3fDiIf+JTayZOjq1/PZXkfdVQWiBinsochjLvPwbBHWBVc3+vaRAD3NdgJv/s9EA Am6Q== X-Gm-Message-State: APjAAAVuCcRGysE4/xpJaocF+W0Xg0IFyMeoGRi2UKMpQBVhrR9f8J2q p0n4gW57kwLYNkLRCS9XK0GIVq3q X-Google-Smtp-Source: APXvYqyGrJIzp0FKOlN6d7zRMGMNPeugaKgK1XCn5WVhk2jJxDCOyr1DapNBNmvQiB3/oHx2ah2T1w== X-Received: by 2002:a25:e80b:: with SMTP id k11mr4060163ybd.434.1560920704814; Tue, 18 Jun 2019 22:05:04 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:43 -0400 Message-Id: <20190619050447.22201-4-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU RFC PATCH v1 3/7] risugen_x86_emit: add module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The helper module risugen_x86_emit.pm exports a single function "parse_emitblock", which serves to capture and return instruction constraints described by "emit" blocks in an x86 configuration file. Signed-off-by: Jan Bobek --- risugen | 2 +- risugen_x86_emit.pm | 85 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 risugen_x86_emit.pm diff --git a/risugen b/risugen index e690b18..fe3d00e 100755 --- a/risugen +++ b/risugen @@ -43,7 +43,7 @@ my @pattern_re =3D (); # include pattern my @not_pattern_re =3D (); # exclude pattern =20 # Valid block names (keys in blocks hash) -my %valid_blockname =3D ( constraints =3D> 1, memory =3D> 1 ); +my %valid_blockname =3D ( constraints =3D> 1, memory =3D> 1, emit =3D> 1 ); =20 sub parse_risu_directive($$@) { diff --git a/risugen_x86_emit.pm b/risugen_x86_emit.pm new file mode 100644 index 0000000..0e3cc1c --- /dev/null +++ b/risugen_x86_emit.pm @@ -0,0 +1,85 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +##########################################################################= ##### + +# risugen_x86_emit -- risugen_x86's helper module for emit blocks +package risugen_x86_emit; + +use strict; +use warnings; + +use risugen_common; +use risugen_x86_asm; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw(parse_emitblock); + +my $emit_opts; + +sub rep(%) +{ + my (%opts) =3D @_; + $emit_opts->{rep} =3D \%opts; +} + +sub repne(%) +{ + my (%opts) =3D @_; + $emit_opts->{repne} =3D \%opts; +} + +sub data16(%) +{ + my (%opts) =3D @_; + $emit_opts->{data16} =3D \%opts; +} + +sub rex(%) +{ + my (%opts) =3D @_; + $emit_opts->{rex} =3D \%opts; +} + +sub modrm(%) +{ + my (%opts) =3D @_; + $emit_opts->{modrm} =3D \%opts; +} + +sub mem(%) +{ + my (%opts) =3D @_; + $emit_opts->{mem} =3D \%opts; +} + +sub imm(%) +{ + my (%opts) =3D @_; + $emit_opts->{imm} =3D \%opts; +} + +sub parse_emitblock($$) +{ + my ($rec, $insn) =3D @_; + my $insnname =3D $rec->{name}; + my $opcode =3D $insn->{opcode}{value}; + + $emit_opts =3D {}; + + my $emitblock =3D $rec->{blocks}{"emit"}; + if (defined $emitblock) { + eval_with_fields($insnname, $opcode, $rec, "emit", $emitblock); + } + + return $emit_opts; +} + +1; --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1560921063; cv=none; d=zoho.com; s=zohoarc; b=hhPgjsj4UO/Sb95m3d+4/b7YT5s7cupzs5AvdgC4JZ+4HP2zjG/AjzwqMeIRIFr17p7StCIiCv9+ZhTX0DtGHTmvsrLxaLgdwWki73isd+r0VYE+pT420BrPfJCmSqtmz6261KHnp0x9wdYVcuIZM8nb39s3u5VyUFUVt/ZjiAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560921063; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=apzfomw1VjtA9D2dSS+kh7pjyf0WWPI5EmgQzsdtCSA=; b=QnV6+aTgIQ5l8JuNe5UaaVa2nwEM7joy0quEdNg4aHD1wpydUp71/QdauSR8xdL5r5tRME96sOGwQqBpLMJmqAtR8u2h3Q0Oscv3XYt2rN44a6Z/xpQPCVti6iKeISebXXb2Or7klriWY9sBEz2sZNOlSTaxrprxPjiPG4jZzms= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560921063561849.2401793721124; Tue, 18 Jun 2019 22:11:03 -0700 (PDT) Received: from localhost ([::1]:35194 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSs7-0002BL-J3 for importer@patchew.org; Wed, 19 Jun 2019 01:10:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34470) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSmZ-0003zK-AJ for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdSmT-0001gG-Md for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:13 -0400 Received: from mail-yb1-xb42.google.com ([2607:f8b0:4864:20::b42]:36158) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdSmT-0001eC-8N for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:09 -0400 Received: by mail-yb1-xb42.google.com with SMTP id w6so5406838ybo.3 for ; Tue, 18 Jun 2019 22:05:06 -0700 (PDT) Received: from localhost.localdomain (67-9-99-67.biz.bhn.net. [67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=apzfomw1VjtA9D2dSS+kh7pjyf0WWPI5EmgQzsdtCSA=; b=fsBXxwS5dG0WEWXBErwYpfFFEH6FcetgUzPrtuRHl9aM6jQbD5m9CFv6YCiAU9OdIL aUKtENARHTQhWIxh00b8O5uaO7o8GlVIDjlewrdY6loIahHlY45bntAWZEucxDBqHCVE OJji7oz8RHdoB/hW5vm3esfP7CWCGijdiUGYGR0mltXpZVK4ByGnvfHIAdl0XhblDmkL Dyhea7W/Gll6KLFVhNj6DUVTlXXUllV7zsidrDebwSB7PQUpFytpV6tr1a+mcm7kCuN/ xECVoaxa8m2QDPEva3FExA+jW85bBkkrm3nDXMECIr0pkaXspt/D3YogxKQyW8lDLeVu ek5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=apzfomw1VjtA9D2dSS+kh7pjyf0WWPI5EmgQzsdtCSA=; b=hexsV6NnNlrTs82C/0aYoyq3qqNJcaeFat4+uiKS9XJyYFisNVOCy4aOQuv4RBksOW 8m/asLp2BLGCmoUYkKicSpCc+ZUhK0YP+vE17+y2uopvkKm5PLR0VEMtJGDcBg0SOFDY vxbZTBCQg9gx962QZnuAu2AMmRRGr2OwMjaTPyCI6O1BUg2TYu2VdenABAD39si8f9Yk nM0Lqi4l/9KUIMIpKsoMWEpkU/j2KMj9ZJl1cqwG4rW6rYtNwJNngfigC0ksKhR8Ym5h Mn4qDAds/ugceznAPMPTdp42NLgES/wn6XfKS/awmmtSezdUY3Popn6UHFnpV0ptnT9s i4yw== X-Gm-Message-State: APjAAAXk7Cf5VEA/DxKuN3Oo/fMhY59eMCF1ZIz0ggCnDYxiE8tOC7Ik yOcFVwwLdI3YsG9Jdy23kiHhasxr X-Google-Smtp-Source: APXvYqzZPHPMyiRFH4YJz31wYpmmDYNfEdgArRUnS9v3xeAw5g0NibNDViqxDIBzTSwfoO442lg6cg== X-Received: by 2002:a25:2e02:: with SMTP id u2mr59672832ybu.27.1560920705861; Tue, 18 Jun 2019 22:05:05 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:44 -0400 Message-Id: <20190619050447.22201-5-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 Subject: [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: add module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The risugen_x86.pm module contains most of the code specific to Intel i386 and x86_64 architectures. This commit also adds --x86_64 option, which enables emission of 64-bit (rather than 32-bit) assembly. Signed-off-by: Jan Bobek --- risugen | 6 +- risugen_x86.pm | 455 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 460 insertions(+), 1 deletion(-) create mode 100644 risugen_x86.pm diff --git a/risugen b/risugen index fe3d00e..09a702a 100755 --- a/risugen +++ b/risugen @@ -310,6 +310,7 @@ Valid options: Useful to test before support for FP is available. --sve : enable sve floating point --be : generate instructions in Big-Endian byte order (ppc64 o= nly). + --x86_64 : generate 64-bit (rather than 32-bit) x86 code. --help : print this message EOT } @@ -322,6 +323,7 @@ sub main() my $fp_enabled =3D 1; my $sve_enabled =3D 0; my $big_endian =3D 0; + my $is_x86_64 =3D 0; my ($infile, $outfile); =20 GetOptions( "help" =3D> sub { usage(); exit(0); }, @@ -338,6 +340,7 @@ sub main() }, "be" =3D> sub { $big_endian =3D 1; }, "no-fp" =3D> sub { $fp_enabled =3D 0; }, + "x86_64" =3D> sub { $is_x86_64 =3D 1; }, "sve" =3D> sub { $sve_enabled =3D 1; }, ) or return 1; # allow "--pattern re,re" and "--pattern re --pattern re" @@ -372,7 +375,8 @@ sub main() 'keys' =3D> \@insn_keys, 'arch' =3D> $full_arch[0], 'subarch' =3D> $full_arch[1] || '', - 'bigendian' =3D> $big_endian + 'bigendian' =3D> $big_endian, + 'x86_64' =3D> $is_x86_64 ); =20 write_test_code(\%params); diff --git a/risugen_x86.pm b/risugen_x86.pm new file mode 100644 index 0000000..879d6e1 --- /dev/null +++ b/risugen_x86.pm @@ -0,0 +1,455 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +##########################################################################= ##### + +# risugen_x86 -- risugen module for Intel i386/x86_64 architectures +package risugen_x86; + +use strict; +use warnings; + +use risugen_common; +use risugen_x86_asm; +use risugen_x86_emit; + +require Exporter; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw(write_test_code); + +use constant { + RISUOP_COMPARE =3D> 0, # compare registers + RISUOP_TESTEND =3D> 1, # end of test, stop + RISUOP_SETMEMBLOCK =3D> 2, # eax is address of memory block (81= 92 bytes) + RISUOP_GETMEMBLOCK =3D> 3, # add the address of memory block to= eax + RISUOP_COMPAREMEM =3D> 4, # compare memory block + + # Maximum alignment restriction permitted for a memory op. + MAXALIGN =3D> 64, + MEMBLOCK_LEN =3D> 8192, +}; + +my $periodic_reg_random =3D 1; +my $is_x86_64 =3D 0; + +sub write_risuop($) +{ + my ($op) =3D @_; + + write_insn(opcode =3D> X86OP_UD1, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> REG_EAX, + rm =3D> $op}); +} + +sub write_mov_rr($$) +{ + my ($r1, $r2) =3D @_; + + my %insn =3D (opcode =3D> X86OP_MOV, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> ($r1 & 0x7), + rm =3D> ($r2 & 0x7)}); + + $insn{rex}{w} =3D 1 if $is_x86_64; + $insn{rex}{r} =3D 1 if $r1 >=3D 8; + $insn{rex}{b} =3D 1 if $r2 >=3D 8; + + write_insn(%insn); +} + +sub write_mov_reg_imm($$) +{ + my ($reg, $imm) =3D @_; + + my %insn =3D (opcode =3D> {value =3D> 0xB8 | ($reg & 0x7), len =3D> 1}, + imm =3D> {value =3D> $imm, len =3D> $is_x86_64 ? 8 : 4}); + + $insn{rex}{w} =3D 1 if $is_x86_64; + $insn{rex}{b} =3D 1 if $reg >=3D 8; + + write_insn(%insn); +} + +sub write_random_regdata() +{ + my $reg_cnt =3D $is_x86_64 ? 16 : 8; + my $bitlen =3D $is_x86_64 ? 64 : 32; + + # initialize flags register + write_insn(opcode =3D> X86OP_XOR, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> REG_EAX, + rm =3D> REG_EAX}); + write_insn(opcode =3D> X86OP_SAHF); + + # general purpose registers + for (my $reg =3D 0; $reg < $reg_cnt; $reg++) { + if ($reg !=3D REG_ESP) { + my $imm =3D randint_constr(bitlen =3D> $bitlen, signed =3D> 1); + write_mov_reg_imm($reg, $imm); + } + } +} + +sub write_random_datablock($) +{ + my ($datalen) =3D @_; + + # Write a block of random data, $datalen bytes long, aligned + # according to MAXALIGN, and load its address into EAX/RAX. + + $datalen +=3D MAXALIGN - 1; + + # First, load current EIP/RIP into EAX/RAX. Easy to do on x86_64 + # thanks to RIP-relative addressing, but on i386 we need to play + # some well-known tricks with CALL instruction. + if ($is_x86_64) { + # 4-byte AND + 5-byte JMP + my $disp32 =3D 4 + 5 + (MAXALIGN - 1); + my $reg =3D REG_EAX; + + write_insn(rex =3D> {w =3D> 1}, + opcode =3D> X86OP_LEA, + modrm =3D> {mod =3D> MOD_INDIRECT, + reg =3D> $reg, rm =3D> REG_EBP}, + disp =3D> {value =3D> $disp32, len =3D> 4}); + + write_insn(rex =3D> {w =3D> 1}, + opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 4, rm =3D> $reg}, + imm =3D> {value =3D> ~(MAXALIGN - 1), + len =3D> 1}); + + } else { + # 1-byte POP + 3-byte ADD + 3-byte AND + 5-byte JMP + my $imm8 =3D 1 + 3 + 3 + 5 + (MAXALIGN - 1); + my $reg =3D REG_EAX; + + # displacement =3D next instruction + write_insn(opcode =3D> X86OP_CALL, + imm =3D> {value =3D> 0x00000000, len =3D> 4}); + + write_insn(opcode =3D> {value =3D> 0x58 | ($reg & 0x7), + len =3D> 1}); + + write_insn(opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 0, rm =3D> $reg}, + imm =3D> {value =3D> $imm8, len =3D> 1}); + + write_insn(opcode =3D> X86OP_ALU_imm8, + modrm =3D> {mod =3D> MOD_DIRECT, + reg =3D> 4, rm =3D> $reg}, + imm =3D> {value =3D> ~(MAXALIGN - 1), + len =3D> 1}); + } + + # JMP over the data blob. + write_insn(opcode =3D> X86OP_JMP, + imm =3D> {value =3D> $datalen, len =3D> 4}); + + # Generate the random data + for (my $w =3D 8; 0 < $w; $w /=3D 2) { + for (; $w <=3D $datalen; $datalen -=3D $w) { + insnv(%{rand_insn_imm(size =3D> $w)}); + } + } +} + +sub write_random_xmmdata() +{ + my $xmm_cnt =3D $is_x86_64 ? 16 : 8; + my $xmm_len =3D 16; + my $datalen =3D $xmm_cnt * $xmm_len; + + # Generate random data blob + write_random_datablock($datalen); + + # Load the random data into XMM regs. + for (my $xmm_reg =3D 0; $xmm_reg < $xmm_cnt; $xmm_reg++) { + my %insn =3D (opcode =3D> X86OP_MOVAPS, + modrm =3D> {mod =3D> MOD_INDIRECT_DISP32, + reg =3D> ($xmm_reg & 0x7), + rm =3D> REG_EAX}, + disp =3D> {value =3D> $xmm_reg * $xmm_len, + len =3D> 4}); + + $insn{rex}{r} =3D 1 if $xmm_reg >=3D 8; + + write_insn(%insn); + } +} + +sub write_memblock_setup() +{ + # Generate random data blob + write_random_datablock(MEMBLOCK_LEN); + # Pointer is in EAX/RAX; set the memblock + write_risuop(RISUOP_SETMEMBLOCK); +} + +sub write_random_register_data() +{ + write_random_xmmdata(); + write_random_regdata(); + write_risuop(RISUOP_COMPARE); +} + +sub rand_insn_imm(%) +{ + my (%args) =3D @_; + + return { + value =3D> randint_constr(bitlen =3D> ($args{size} * 8), signed = =3D> 1), + len =3D> $args{size} + }; +} + +sub rand_insn_opcode($) +{ + # Given an instruction-details array, generate an instruction + my ($rec) =3D @_; + my $insnname =3D $rec->{name}; + my $insnwidth =3D $rec->{width}; + + my $constraintfailures =3D 0; + + INSN: while(1) { + my $opcode =3D randint_constr(bitlen =3D> 32, + fixedbits =3D> $rec->{fixedbits}, + fixedbitmask =3D> $rec->{fixedbitmask}= ); + + my $constraint =3D $rec->{blocks}{"constraints"}; + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v =3D eval_with_fields($insnname, $opcode, $rec, "constrai= nts", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insn= name constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures =3D 0; + + return { + value =3D> $opcode >> (32 - $insnwidth), + len =3D> $insnwidth / 8 + }; + } +} + +sub rand_insn_modrm($$) +{ + my ($opts, $insn) =3D @_; + my $modrm; + + while (1) { + $modrm =3D rand_fill({mod =3D> {bitlen =3D> 2}, + reg =3D> {bitlen =3D> 3}, + rm =3D> {bitlen =3D> 3}}, + $opts); + + if ($modrm->{mod} !=3D MOD_DIRECT) { + # Displacement only; we cannot use this since we + # don't know absolute address of the memblock. + next if $modrm->{mod} =3D=3D MOD_INDIRECT && $modrm->{rm} =3D= =3D REG_EBP; + + if ($modrm->{rm} =3D=3D REG_ESP) { + # SIB byte present + my $sib =3D rand_fill({ss =3D> {bitlen =3D> 2}, + index =3D> {bitlen =3D> 3}, + base =3D> {bitlen =3D> 3}}, {}); + + # We cannot modify ESP/RSP during the tests + next if $sib->{base} =3D=3D REG_ESP; + + # When base and index register are the same, + # computing the correct memblock addresses and + # offsets gets way too complicated... + next if $sib->{base} =3D=3D $sib->{index}; + + # No base register + next if $modrm->{mod} =3D=3D MOD_INDIRECT && $sib->{base} = =3D=3D REG_EBP; + + $insn->{sib} =3D $sib; + } + + $insn->{disp} =3D rand_insn_imm(size =3D> 1) + if $modrm->{mod} =3D=3D MOD_INDIRECT_DISP8; + + $insn->{disp} =3D rand_insn_imm(size =3D> 4) + if $modrm->{mod} =3D=3D MOD_INDIRECT_DISP32; + } + + $insn->{modrm} =3D $modrm; + last; + } +} + +sub rand_insn_rex($$) +{ + my ($opts, $insn) =3D @_; + + $opts->{w} =3D 0 unless defined $opts->{w}; + $opts->{x} =3D 0 unless defined $opts->{x} || defined $insn->{sib}; + + my $rex =3D rand_fill({w =3D> {bitlen =3D> 1}, + r =3D> {bitlen =3D> 1}, + b =3D> {bitlen =3D> 1}, + x =3D> {bitlen =3D> 1}}, + $opts); + + $insn->{rex} =3D $rex + if $rex->{w} || $rex->{r} || $rex->{b} || $rex->{x}; +} + +sub write_mem_getoffset($$) +{ + my ($opts, $insn) =3D @_; + my $offset, my $index; + + $opts->{size} =3D 0 unless defined $opts->{size}; + $opts->{align} =3D 1 unless defined $opts->{align}; + + if (!defined $opts->{base} + && defined $insn->{modrm} + && $insn->{modrm}{mod} !=3D MOD_DIRECT) { + + $opts->{base} =3D (defined $insn->{sib} + ? $insn->{sib}{base} + : $insn->{modrm}{rm}); + + if ($insn->{modrm}{mod} =3D=3D MOD_INDIRECT && $opts->{base} =3D= =3D REG_EBP) { + delete $opts->{base}; # No base register + } else { + $opts->{base} |=3D $insn->{rex}{b} << 3 if defined $insn->{rex= }; + $opts->{base} |=3D (!$insn->{vex}{b}) << 3 if defined $insn->{= vex}; + } + } + + if (!defined $opts->{index} && defined $insn->{sib}) { + $opts->{index} =3D $insn->{sib}{index}; + $opts->{index} |=3D $insn->{rex}{x} << 3 if defined $insn->{rex}; + $opts->{index} |=3D (!$insn->{vex}{x}) << 3 if defined $insn->{vex= }; + delete $opts->{index} if $opts->{index} =3D=3D REG_ESP; # ESP mean= s "none" + } + + $opts->{ss} =3D $insn->{sib}{ss} if !defined $opts->{ss} && defined $i= nsn->{sib}; + $opts->{disp} =3D $insn->{disp} if !defined $opts->{disp} && defined $= insn->{disp}; + + $offset =3D int(rand(MEMBLOCK_LEN - $opts->{size})); + $offset &=3D ~($opts->{align} - 1); + + $offset -=3D $opts->{disp}{value} if defined $opts->{disp}; + + if (defined $opts->{index}) { + $index =3D randint_constr(bitlen =3D> 32, signed =3D> 1); + $offset -=3D $index * (1 << $opts->{ss}); + } + + if (defined $opts->{base} && defined $offset) { + write_mov_reg_imm(REG_EAX, $offset); + write_risuop(RISUOP_GETMEMBLOCK); + write_mov_rr($opts->{base}, REG_EAX); + } + if (defined $opts->{index} && defined $index) { + write_mov_reg_imm($opts->{index}, $index); + } +} + +sub gen_one_insn($) +{ + my ($rec) =3D @_; + my $insn; + + $insn->{opcode} =3D rand_insn_opcode($rec); + my $opts =3D parse_emitblock($rec, $insn); + + # Operation with a ModR/M byte can potentially use a memory + # operand + $opts->{mem} =3D {} + unless defined $opts->{mem} || !defined $opts->{modrm}; + + # If none of REX/VEX/EVEX are specified, default to REX + $opts->{rex} =3D {} + unless defined $opts->{rex} || defined $opts->{vex} || defined $op= ts->{evex}; + + # REX requires x86_64 + delete $opts->{rex} + unless $is_x86_64; + + $insn->{rep} =3D $opts->{rep} if defined $opts->{rep}; + $insn->{repne} =3D $opts->{repne} if defined $opts->{repne}; + $insn->{data16} =3D $opts->{data16} if defined $opts->{data16}; + + rand_insn_modrm($opts->{modrm}, $insn) if defined $opts->{modrm}; + + # TODO rand_insn_vex($opts->{vex}, $insn) if defined $opts->{vex}; + # TODO rand_insn_evex($opts->{evex}, $insn) if defined $opts->{evex}; + rand_insn_rex($opts->{rex}, $insn) if defined $opts->{rex}; + + $insn->{imm} =3D rand_insn_imm(%{$opts->{imm}}) if defined $opts->{imm= }; + + write_mem_getoffset($opts->{mem}, $insn); + write_insn(%{$insn}); +} + +sub write_test_code($) +{ + my ($params) =3D @_; + + my $numinsns =3D $params->{ 'numinsns' }; + my $outfile =3D $params->{ 'outfile' }; + + my %insn_details =3D %{ $params->{ 'details' } }; + my @keys =3D @{ $params->{ 'keys' } }; + + $is_x86_64 =3D $params->{ 'x86_64' }; + + open_bin($outfile); + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + write_memblock_setup(); + + # memblock setup doesn't clean its registers, so this must come afterw= ards. + write_random_register_data(); + + for my $i (1..$numinsns) { + my $insn_enc =3D $keys[int rand (@keys)]; + # my $forcecond =3D (rand() < $condprob) ? 1 : 0; + gen_one_insn($insn_details{$insn_enc}); + write_risuop(RISUOP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) =3D=3D 0) { + write_random_register_data(); + } + progress_update($i); + } + write_risuop(RISUOP_TESTEND); + progress_end(); + close_bin(); +} + +1; --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1560921016; cv=none; d=zoho.com; s=zohoarc; b=GiBJeJoMer3NpWSyJ5YKlyIhVunt27lShkM8m+M2ZPvb/0GcwwSLNDjHJjv8JMn+MHf1Tc2GYgEQpsyoaI8HQOzDDnG5OGc/wtEKFaIOXJhLG6XM49AePFM14w8LuPhBNIV3sSWeT4FdyYA5hKW0WR3K1HH5pOfkpsldVKWwS3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560921016; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=gemq4FQpBDazHnNNQMVsZrUQhBxsgJYn42ZIvzcwvYo=; b=L/PxgBmqe47sfz6TgP2sU5J8SGMr2SsbJ0zf9tmSYbPDvLjr4bgeB5SoqusiWEyCIjMXu8y1NyH8tkeR1T5mrQfAWcyyaQ15D50cS6aWMcaG858yXot7PiQrOFaqjnvbL3UsO/QcTHAk9dycV+SmkwqqObzh8JcZ13l2oqs3OFY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560921016808789.9797619013232; Tue, 18 Jun 2019 22:10:16 -0700 (PDT) Received: from localhost ([::1]:35184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSrJ-0000e0-SP for importer@patchew.org; Wed, 19 Jun 2019 01:10:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34448) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSmV-0003vc-EL for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdSmT-0001g8-KA for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:11 -0400 Received: from mail-yb1-xb41.google.com ([2607:f8b0:4864:20::b41]:45563) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdSmT-0001ec-6o for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:09 -0400 Received: by mail-yb1-xb41.google.com with SMTP id v104so7061871ybi.12 for ; Tue, 18 Jun 2019 22:05:07 -0700 (PDT) Received: from localhost.localdomain (67-9-99-67.biz.bhn.net. [67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gemq4FQpBDazHnNNQMVsZrUQhBxsgJYn42ZIvzcwvYo=; b=bCx5cGscHJ/NJVBK6K17fEQcOA36yWW+bwRtJTW/fNCKAo16OEJgAJ2LPdW/rqD0cP 74N+tt/MMyh75MXibMrvu+Gh/AxBpqZqK03hgPWPzatPJQEZurDx2zNnsuVEmaS7JUJL PBkGTXRfq+OiilXkzFJu/uk4jlTXuUlwWs8okYO+G+iu9jfOerYCPkpq8VncprSqMAWs 5Rj4Ie89jbpErSDC0tvEs4wJ4VRPpYEBlnbAFxeKyZBnQAlTJJU6Su7fzELryxzZ1LUu KvvNYwztN1UZrDkjUn4iVD2epP1ltnVhMKQzgHjqYQZS06iW7K96OY4Zrmm6PzV0nqds S8ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gemq4FQpBDazHnNNQMVsZrUQhBxsgJYn42ZIvzcwvYo=; b=Ipeon3tH6Hih6Z0hCjviE6oST7Pr72uR3yCcBQerUnrHSAR8K3F2012FkthZsN3ypc KOjZXfzs02rldfwRgFvsGRIxFUVtu1Vb2x/+ZLZmdQG5uGNmYRhik84unrdRBPrw1ibd IjiqogsSnszJacAeZxttOzu2qHeL8yl2l2COJfCFW17wgZ1gpgBH13dq79GdA10DepAu NWsM8MvbUWGuiJTgB3VNfFWtNBzBHoiYlWo6HULe/FTBKDJG/PUxro6Hz6j05utbsxIh UIbsKOBymLviBc4z6HTFGHLQ72YKGFClBLllRNePwtuPBophst8S1vXIKViK15r1f0rl PMhA== X-Gm-Message-State: APjAAAV8S8afV5XgOMUxiXss/bM+yOp2SYxgq4O+VBaGYrITGCVUgfbU FdQLdLsX/aH/JC8P5CbCPbwSeZmY X-Google-Smtp-Source: APXvYqwMYcgh/AXWierOd6UCwIjrXcsT6U5PPIOk2M1SRnSfKVyGgbmA8QEHE/Q+0anjyboIv1aSvQ== X-Received: by 2002:a25:20c6:: with SMTP id g189mr20010311ybg.401.1560920706938; Tue, 18 Jun 2019 22:05:06 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:45 -0400 Message-Id: <20190619050447.22201-6-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 Subject: [Qemu-devel] [RISU RFC PATCH v1 5/7] risugen: allow all byte-aligned instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Accept all instructions whose bit length is divisible by 8. Note that the maximum instruction length (as specified in the config file) is 32 bits, hence this change permits instructions which are 8 bits or 24 bits long (16-bit instructions have already been considered valid). Note that while valid x86 instructions may be up to 15 bytes long, the length constraint described above only applies to the main opcode field, which is usually only 1 or 2 bytes long. Therefore, the primary purpose of this change is to allow 1-byte x86 opcodes. Signed-off-by: Jan Bobek Reviewed-by: Richard Henderson --- risugen | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/risugen b/risugen index 09a702a..17bf98f 100755 --- a/risugen +++ b/risugen @@ -229,12 +229,11 @@ sub parse_config_file($) push @fields, [ $var, $bitpos, $bitmask ]; } } - if ($bitpos =3D=3D 16) { - # assume this is a half-width thumb instruction + if ($bitpos % 8 =3D=3D 0) { # Note that we don't fiddle with the bitmasks or positions, # which means the generated insn will be in the high halfword! - $insnwidth =3D 16; - } elsif ($bitpos !=3D 0) { + $insnwidth -=3D $bitpos; + } else { print STDERR "$file:$.: ($insn $enc) not enough bits specified= \n"; exit(1); } --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1560920875; cv=none; d=zoho.com; s=zohoarc; b=QlxcyRF6Zx2WDqriXURcyv/2egCpCenHveVDGe1vgixyi+72sRw8r573daVKHkZqPCYDxg8Gkpv2wiTgl2rjzLmJFysm+yxdEZmx50HnLiSm3/DiWm1obqr4EfKHhpKZYxJ3MuSdKhgJGKmTTMwz4S8hAMHo0OGx+26hDguqiSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560920875; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=f1TNYWO3EEifVKZE2F7vRjyCMw4wSrP5B9IQTXvCdlA=; b=jphLawsElga1/DFb5am3D2lV9GRTNTp9uwjwA6uU8sQHubdesK/ThVlwcxJv1xDVuKwkZggh0tzaqJf6JEmfWrXFEcSCnWyjlVzosQk96ZVpvIpdiEg8XdTTJRNwTz+gclAnB7vAPFTbZfjkesNAk82C51JiLpFZatUEsLjMPCA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560920875702526.2108516739938; Tue, 18 Jun 2019 22:07:55 -0700 (PDT) Received: from localhost ([::1]:35166 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSp0-00063s-Nv for importer@patchew.org; Wed, 19 Jun 2019 01:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34499) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdSmb-00041I-Bj for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdSmV-0001hA-Cl for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:17 -0400 Received: from mail-yb1-xb44.google.com ([2607:f8b0:4864:20::b44]:41245) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hdSmT-0001fG-H8 for qemu-devel@nongnu.org; Wed, 19 Jun 2019 01:05:09 -0400 Received: by mail-yb1-xb44.google.com with SMTP id d2so7077662ybh.8 for ; Tue, 18 Jun 2019 22:05:08 -0700 (PDT) Received: from localhost.localdomain (67-9-99-67.biz.bhn.net. [67.9.99.67]) by smtp.gmail.com with ESMTPSA id e12sm1714426ywe.85.2019.06.18.22.05.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 22:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f1TNYWO3EEifVKZE2F7vRjyCMw4wSrP5B9IQTXvCdlA=; b=N6y1yZHXVDiebr5MtA36UMo5CPLLyOPVRFZspXz/nxJyGdGUObWPvz38O6g57/NNz+ frpj9a2l7Vv9weUd0A9GNmrMZ7UBafGBSCw/NFOdOmX1H9xHh504+qJ+4mkjDysiPzmM l8aekkbuM7f8k5YXFS3sRwRDyvaBU+hSfI+gChm6qBfRgut6/7AU6jTZY3L+xj7mOfn9 IC5xPOso0cHK9A7TL+vd4IJSiOOjcMLt8yPtDRKFhpp4V8JjxXaqeeB5PH/H0h9ZE3r4 ZRNF8uJYQFDhk2k71rOBuUPRtAwA3m3X3GFHTy9IYoWiPC5H67zb358kusTmHYn6NVfG QFHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f1TNYWO3EEifVKZE2F7vRjyCMw4wSrP5B9IQTXvCdlA=; b=G7NuumzWBhP/e23bzYYF+RNeAKYq/SfdujKvjW1E5KKpGABifPAl3coVUA4B1JIPI8 ty2WFOMxv7t+r4zxHsCtp7Z+FZOeNNoKnGg4KhKRsY8p3l/mc6EYc4ynT27dlG1neX6D gwwAvekG6MBs7gINY0rnv8GA58Oo/Dho8g5UZX1K2Lvc+mXAcq3A3aZmWMNaJGFLUVl/ 1YewwYSAU1Wf4uZMXvl0EHyk2dIQYe+5lZ3c8bq67C+UUrdP3+eZMWk+9KURtk/68zPW xV2cmoNNCjb8gipr64VBqheLTYmPCQAzIkm8Jr7mPighhhmCZQJsd3Ag0M12yGFANvZm OZEg== X-Gm-Message-State: APjAAAUp7/krTFvbw1tJiigakAQe6lerCRKRgYfmZHBPlcnGHoG6B7xR pk4Q2g3BTO5KV8AlIlh7l7xS7ooI X-Google-Smtp-Source: APXvYqztvc6ldGU2fVCd5zeB4I0v5QQhoGYq7QkLHghaoJZgbZxpIorv0EJ/m9YDUQuUyAPmal7sHA== X-Received: by 2002:a5b:405:: with SMTP id m5mr20382836ybp.261.1560920707827; Tue, 18 Jun 2019 22:05:07 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Wed, 19 Jun 2019 01:04:46 -0400 Message-Id: <20190619050447.22201-7-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190619050447.22201-1-jan.bobek@gmail.com> References: <20190619050447.22201-1-jan.bobek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU RFC PATCH v1 6/7] x86.risu: add SSE instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add an x86 configuration file with all SSE instructions. Signed-off-by: Jan Bobek --- x86.risu | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 x86.risu diff --git a/x86.risu b/x86.risu new file mode 100644 index 0000000..cc40bbc --- /dev/null +++ b/x86.risu @@ -0,0 +1,99 @@ +##########################################################################= ##### +# Copyright (c) 2019 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Jan Bobek - initial implementation +##########################################################################= ##### + +# Input file for risugen defining x86 instructions +.mode x86 + +# SSE Data Transfer Instructions +MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size =3D> = 16); } +MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(siz= e =3D> 4); } +MOVHLPS SSE 00001111 00010010 !emit { modrm(mod =3D> MOD_DIRE= CT); } +MOVLPS SSE 00001111 0001001 d !emit { modrm(mod =3D> ~MOD_DIR= ECT); mem(size =3D> 8); } +MOVLHPS SSE 00001111 00010110 !emit { modrm(mod =3D> MOD_DIRE= CT); } +MOVHPS SSE 00001111 0001011 d !emit { modrm(mod =3D> ~MOD_DIR= ECT); mem(size =3D> 8); } +MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size =3D> = 16, align =3D> 16); } +MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod =3D> MOD_DIRE= CT, reg =3D> ~REG_ESP); } + +# SSE Packed Arithmetic Instructions +ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size= =3D> 4); } +SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size= =3D> 4); } +MULPS SSE 00001111 01011001 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size= =3D> 4); } +DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size= =3D> 4); } +RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size= =3D> 4); } +SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size= =3D> 4); } +RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size= =3D> 4); } +MINPS SSE 00001111 01011101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size= =3D> 4); } +MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size= =3D> 4); } + +# SSE Comparison Instructions +CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); imm(size =3D> 1); } +CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size= =3D> 4); imm(size =3D> 1); } +UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size =3D> 4= ); } +COMISS SSE 00001111 00101111 !emit { modrm(); mem(size =3D> 4= ); } + +# SSE Logical Instructions +ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ORPS SSE 00001111 01010110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +XORPS SSE 00001111 01010111 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } + +# SSE Shuffle and Unpack Instructions +SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); imm(size =3D> 1); } +UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } + +# SSE Conversion Instructions +CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size =3D> 8= ); } +CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size= =3D> 4); } +CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w =3D> 1); mo= drm(); mem(size =3D> 8); } +CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size =3D> 8= ); } +CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg =3D> ~R= EG_ESP); mem(size =3D> 4); } +CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w =3D> 1); mo= drm(reg =3D> ~REG_ESP); mem(size =3D> 4); } +CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size =3D> 8= ); } +CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg =3D> ~R= EG_ESP); mem(size =3D> 4); } +CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w =3D> 1); mo= drm(reg =3D> ~REG_ESP); mem(size =3D> 4); } + +# SSE MXCSR State Management Instructions +# LDMXCSR SSE 00001111 10101110 !emit { modrm(mod =3D> ~MOD_DI= RECT, reg =3D> 2); mem(size =3D> 4); } +STMXCSR SSE 00001111 10101110 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 3); mem(size =3D> 4); } + +# SSE 64-bit SIMD Integer Instructions +PAVGB SSE 00001111 11100000 !emit { modrm(); mem(size =3D> 8= ); } +PAVGW SSE 00001111 11100011 !emit { modrm(); mem(size =3D> 8= ); } +PEXTRW SSE 00001111 11000101 !emit { modrm(mod =3D> MOD_DIREC= T, reg =3D> ~REG_ESP); mem(size =3D> 8); imm(size =3D> 1); } +PINSRW SSE 00001111 11000100 !emit { modrm(); mem(size =3D> 2= ); imm(size =3D> 1); } +PMAXUB SSE 00001111 11011110 !emit { modrm(); mem(size =3D> 8= ); } +PMAXSW SSE 00001111 11101110 !emit { modrm(); mem(size =3D> 8= ); } +PMINUB SSE 00001111 11011010 !emit { modrm(); mem(size =3D> 8= ); } +PMINSW SSE 00001111 11101010 !emit { modrm(); mem(size =3D> 8= ); } +PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod =3D> MOD_DIREC= T, reg =3D> ~REG_ESP); mem(size =3D> 8); } +PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size =3D> 8= ); } +PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size =3D> 8= ); } +PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size =3D> 8= ); imm(size =3D> 1); } + +# SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions +MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod =3D> MOD_DIREC= T); mem(size =3D> 8, base =3D> REG_EDI); } +MOVNTQ SSE 00001111 11100111 !emit { modrm(mod =3D> ~MOD_DIRE= CT); mem(size =3D> 8); } +MOVNTPS SSE 00001111 00101011 !emit { modrm(mod =3D> ~MOD_DIRE= CT); mem(size =3D> 16, align =3D> 16); } +PREFETCHT0 SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 1); mem(size =3D> 1); } +PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 2); mem(size =3D> 1); } +PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 3); mem(size =3D> 1); } +PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 0); mem(size =3D> 1); } +SFENCE SSE 00001111 10101110 !emit { modrm(mod =3D> MOD_DIREC= T, reg =3D> 7); } --=20 2.20.1 From nobody Tue Nov 11 01:34:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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X-Received-From: 2607:f8b0:4864:20::c41 Subject: [Qemu-devel] [RISU RFC PATCH v1 7/7] x86.risu: add SSE2 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add all SSE2 instructions to the x86 configuration file. Signed-off-by: Jan Bobek --- x86.risu | 160 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 153 insertions(+), 7 deletions(-) diff --git a/x86.risu b/x86.risu index cc40bbc..b3e4c88 100644 --- a/x86.risu +++ b/x86.risu @@ -12,63 +12,137 @@ # Input file for risugen defining x86 instructions .mode x86 =20 -# SSE Data Transfer Instructions +# SSE/SSE2 Data Transfer Instructions MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size =3D> = 16); } +MOVUPD SSE2 00001111 0001000 d !emit { data16(); modrm(); mem(= size =3D> 16); } MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(siz= e =3D> 4); } +MOVSD SSE2 00001111 0001000 d !emit { repne(); modrm(); mem(s= ize =3D> 8); } + MOVHLPS SSE 00001111 00010010 !emit { modrm(mod =3D> MOD_DIRE= CT); } MOVLPS SSE 00001111 0001001 d !emit { modrm(mod =3D> ~MOD_DIR= ECT); mem(size =3D> 8); } +MOVLPD SSE2 00001111 0001001 d !emit { data16(); modrm(mod =3D= > ~MOD_DIRECT); mem(size =3D> 8); } + MOVLHPS SSE 00001111 00010110 !emit { modrm(mod =3D> MOD_DIRE= CT); } MOVHPS SSE 00001111 0001011 d !emit { modrm(mod =3D> ~MOD_DIR= ECT); mem(size =3D> 8); } +MOVHPD SSE2 00001111 0001011 d !emit { data16(); modrm(mod =3D= > ~MOD_DIRECT); mem(size =3D> 8); } + MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size =3D> = 16, align =3D> 16); } +MOVAPD SSE2 00001111 0010100 d !emit { data16(); modrm(); mem(= size =3D> 16, align =3D> 16); } + MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod =3D> MOD_DIRE= CT, reg =3D> ~REG_ESP); } +MOVMKSPD SSE2 00001111 01010000 !emit { data16(); modrm(mod =3D= > MOD_DIRECT, reg =3D> ~REG_ESP); } =20 -# SSE Packed Arithmetic Instructions +# SSE/SSE2 Packed Arithmetic Instructions ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ADDPD SSE2 00001111 01011000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16) } ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size= =3D> 4); } +ADDSD SSE2 00001111 01011000 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +SUBPD SSE2 00001111 01011100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size= =3D> 4); } +SUBSD SSE2 00001111 01011100 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + MULPS SSE 00001111 01011001 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MULPD SSE2 00001111 01011001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size= =3D> 4); } -DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MULSD SSE2 00001111 01011001 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + +DIVPS SSE 00001111 01011110 !emit { modrm(); modrm(); mem(si= ze =3D> 16, align =3D> 16); } +DIVPD SSE2 00001111 01011110 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size= =3D> 4); } +DIVSD SSE2 00001111 01011110 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size= =3D> 4); } + SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +SQRTPD SSE2 00001111 01010001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size= =3D> 4); } +SQRTSD SSE2 00001111 01010001 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size= =3D> 4); } + MINPS SSE 00001111 01011101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MINPD SSE2 00001111 01011101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size= =3D> 4); } +MINSD SSE2 00001111 01011101 !emit { repne(); modrm(); mem(si= ze =3D> 4); } + MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +MAXPD SSE2 00001111 01011111 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size= =3D> 4); } +MAXSD SSE2 00001111 01011111 !emit { repne(); modrm(); mem(si= ze =3D> 4); } =20 -# SSE Comparison Instructions +# SSE/SSE2 Comparison Instructions CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); imm(size =3D> 1); } +CMPPD SSE2 00001111 11000010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); imm(size =3D> 1); } CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size= =3D> 4); imm(size =3D> 1); } +CMPSD SSE2 00001111 11000010 !emit { repne(); modrm(); mem(si= ze =3D> 4); imm(size =3D> 1); } + UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size =3D> 4= ); } +UCOMISD SSE2 00001111 00101110 !emit { data16(); modrm(); mem(s= ize =3D> 4); } + COMISS SSE 00001111 00101111 !emit { modrm(); mem(size =3D> 4= ); } +COMISD SSE2 00001111 00101111 !emit { data16(); modrm(); mem(s= ize =3D> 4); } =20 -# SSE Logical Instructions +# SSE/SSE2 Logical Instructions ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ANDPD SSE2 00001111 01010100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ANDNPD SSE2 00001111 01010101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + ORPS SSE 00001111 01010110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +ORPD SSE2 00001111 01010110 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + XORPS SSE 00001111 01010111 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +XORPD SSE2 00001111 01010111 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } =20 -# SSE Shuffle and Unpack Instructions +# SSE/SSE2 Shuffle and Unpack Instructions SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); imm(size =3D> 1); } +SHUFPD SSE2 00001111 11000110 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); imm(size =3D> 1); } + UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +UNPCKLPD SSE2 00001111 00010100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +UNPCKHPD SSE2 00001111 00010101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } =20 -# SSE Conversion Instructions +# SSE/SSE2 Conversion Instructions CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size =3D> 8= ); } +CVTPI2PD SSE2 00001111 00101010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size= =3D> 4); } +CVTSI2SD SSE2 00001111 00101010 !emit { repne(); modrm(); mem(si= ze =3D> 8); } CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w =3D> 1); mo= drm(); mem(size =3D> 8); } +CVTSI2SD_64 SSE2 00001111 00101010 !emit { repne(); rex(w =3D> 1); = modrm(); mem(size =3D> 8); } + CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size =3D> 8= ); } +CVTPD2PI SSE2 00001111 00101101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg =3D> ~R= EG_ESP); mem(size =3D> 4); } +CVTSD2SI SSE2 00001111 00101101 !emit { repne(); modrm(reg =3D> = ~REG_ESP); mem(size =3D> 8); } CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w =3D> 1); mo= drm(reg =3D> ~REG_ESP); mem(size =3D> 4); } +CVTSD2SI_64 SSE2 00001111 00101101 !emit { repne(); rex(w =3D> 1); = modrm(reg =3D> ~REG_ESP); mem(size =3D> 8); } + CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size =3D> 8= ); } +CVTTPD2PI SSE2 00001111 00101100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg =3D> ~R= EG_ESP); mem(size =3D> 4); } +CVTTSD2SI SSE2 00001111 00101100 !emit { repne(); modrm(reg =3D> = ~REG_ESP); mem(size =3D> 8); } CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w =3D> 1); mo= drm(reg =3D> ~REG_ESP); mem(size =3D> 4); } +CVTTSD2SI_64 SSE2 00001111 00101100 !emit { repne(); rex(w =3D> 1); = modrm(reg =3D> ~REG_ESP); mem(size =3D> 8); } + +CVTPD2PQ SSE2 00001111 11100110 !emit { repne(); modrm(); mem(si= ze =3D> 16, align =3D> 16); } +CVTTPD2PQ SSE2 00001111 11100110 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +CVTDQ2PD SSE2 00001111 11100110 !emit { rep(); modrm(); mem(size= =3D> 8); } + +CVTPS2PD SSE2 00001111 01011010 !emit { modrm(); mem(size =3D> 8= ); } +CVTPD2PS SSE2 00001111 01011010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +CVTSS2SD SSE2 00001111 01011010 !emit { rep(); modrm(); mem(size= =3D> 4); } +CVTSD2SS SSE2 00001111 01011010 !emit { repne(); modrm(); mem(si= ze =3D> 8); } + +CVTDQ2PS SSE2 00001111 01011011 !emit { modrm(); mem(size =3D> 1= 6, align =3D> 16); } +CVTPS2DQ SSE2 00001111 01011011 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +CVTTPS2DQ SSE2 00001111 01011011 !emit { rep(); modrm(); mem(size= =3D> 16, align =3D> 16); } =20 # SSE MXCSR State Management Instructions # LDMXCSR SSE 00001111 10101110 !emit { modrm(mod =3D> ~MOD_DI= RECT, reg =3D> 2); mem(size =3D> 4); } @@ -88,6 +162,67 @@ PMULHUW SSE 00001111 11100100 !emit { modrm= (); mem(size =3D> 8); } PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size =3D> 8= ); } PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size =3D> 8= ); imm(size =3D> 1); } =20 +# SSE2 128-bit SIMD Integer Instructions +MOVDQA SSE2 00001111 011 d 1111 !emit { data16(); modrm(); mem= (size =3D> 16, align =3D> 16); } +MOVDQU SSE2 00001111 011 d 1111 !emit { rep(); modrm(); mem(si= ze =3D> 16); } +MOVQ2DQ SSE2 00001111 11010110 !emit { rep(); modrm(mod =3D> MO= D_DIRECT); } +MOVDQ2Q SSE2 00001111 11010110 !emit { repne(); modrm(mod =3D> = MOD_DIRECT); } + +PMULUDQ_64 SSE2 00001111 11110100 !emit { modrm(); mem(size =3D> 8= ); } +PMULUDQ SSE2 00001111 11110100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDB SSE2 00001111 11111100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDW SSE2 00001111 11111101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDD SSE2 00001111 11111110 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDQ SSE2 00001111 11010100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDSB SSE2 00001111 11101100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDSW SSE2 00001111 11101101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDUSB SSE2 00001111 11011100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PADDUSW SSE2 00001111 11011101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBB SSE2 00001111 11111000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBW SSE2 00001111 11111001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBD SSE2 00001111 11111010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBQ_64 SSE2 00001111 11111011 !emit { modrm(); mem(size =3D> 8= ); } +PSUBQ SSE2 00001111 11111011 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBSB SSE2 00001111 11101000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBSW SSE2 00001111 11101001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBUSB SSE2 00001111 11011000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSUBUSW SSE2 00001111 11011001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + +PSHUFLW SSE2 00001111 01110000 !emit { repne(); modrm(); mem(si= ze =3D> 16, align =3D> 16); imm(size =3D> 1); } +PSHUFHW SSE2 00001111 01110000 !emit { rep(); modrm(); mem(size= =3D> 16, align =3D> 16); imm(size =3D> 1); } +PSHUFD SSE2 00001111 01110000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); imm(size =3D> 1); } + +PSLLW SSE2 00001111 11110001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSLLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 6); imm(size =3D> 1); } +PSLLD SSE2 00001111 11110010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSLLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 6); imm(size =3D> 1); } +PSLLQ SSE2 00001111 11110011 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSLLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 6); imm(size =3D> 1); } +PSLLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 7); imm(size =3D> 1); } + +PSRAW SSE2 00001111 11100001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSRAW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 4); imm(size =3D> 1); } +PSRAD SSE2 00001111 11100010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSRAD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 4); imm(size =3D> 1); } + +PSRLW SSE2 00001111 11010001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSRLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 2); imm(size =3D> 1); } +PSRLD SSE2 00001111 11010010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSRLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 2); imm(size =3D> 1); } +PSRLQ SSE2 00001111 11010011 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PSRLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 2); imm(size =3D> 1); } +PSRLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod =3D>= MOD_DIRECT, reg =3D> 3); imm(size =3D> 1); } + +PUNPCKHBW SSE2 00001111 01101000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKHWD SSE2 00001111 01101001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKHDQ SSE2 00001111 01101010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKHQDQ SSE2 00001111 01101101 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + +PUNPCKLBW SSE2 00001111 01100000 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKLWD SSE2 00001111 01100001 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKLDQ SSE2 00001111 01100010 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } +PUNPCKLQDQ SSE2 00001111 01101100 !emit { data16(); modrm(); mem(s= ize =3D> 16, align =3D> 16); } + # SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod =3D> MOD_DIREC= T); mem(size =3D> 8, base =3D> REG_EDI); } MOVNTQ SSE 00001111 11100111 !emit { modrm(mod =3D> ~MOD_DIRE= CT); mem(size =3D> 8); } @@ -97,3 +232,14 @@ PREFETCHT1 SSE 00001111 00011000 !emit { modrm= (mod =3D> ~MOD_DIRECT, reg PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 3); mem(size =3D> 1); } PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 0); mem(size =3D> 1); } SFENCE SSE 00001111 10101110 !emit { modrm(mod =3D> MOD_DIREC= T, reg =3D> 7); } + +# SSE2 Cacheability Control, Prefetch, and Instruction Ordering Instructio= ns +CFLUSH SSE2 00001111 10101110 !emit { modrm(mod =3D> ~MOD_DIRE= CT, reg =3D> 7); mem(size =3D> 1); } +LFENCE SSE2 00001111 10101110 !emit { modrm(mod =3D> 0b11, reg= =3D> 0b101); } +MFENCE SSE2 00001111 10101110 !emit { modrm(mod =3D> 0b11, reg= =3D> 0b111); } +PAUSE SSE2 10010000 !emit { rep(); } +MASKMOVDQU SSE2 00001111 11110111 !emit { data16(); modrm(mod =3D>= MOD_DIRECT); mem(size =3D> 16, base =3D> REG_EDI); } +MOVNTPD SSE2 00001111 00101011 !emit { data16(); modrm(mod =3D>= ~MOD_DIRECT); mem(size =3D> 16, align =3D> 16); } +MOVNTDQ SSE2 00001111 11100111 !emit { data16(); modrm(mod =3D>= ~MOD_DIRECT); mem(size =3D> 16, align =3D> 16); } +MOVNTI SSE2 00001111 11000011 !emit { modrm(mod =3D> ~MOD_DIRE= CT); mem(size =3D> 4); } +MOVNTI_64 SSE2 00001111 11000011 !emit { rex(w =3D> 1); modrm(mod= =3D> ~MOD_DIRECT); mem(size =3D> 8); } --=20 2.20.1