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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t14sm8713619wrr.33.2019.06.17.10.53.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 10:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v8vwTZLuhwp+bmBixmmWp52i36uK/epxo9J3L5qAyYw=; b=qQnFthMSJo8bfP4HEGAgZBvsS1BmZaBI2he8FBMFZln/yYefl8iffG5CDe/FQCaaoz /VbmNkeZ7Q5CljJMhl+5A4Wl7KgcnpOPA6fmvxdbbHorj4vdDcrkVlPuQWCOMJfKRfQI 9CJMqwtN9y2sjTAyAf9/GH6LlNfn9pCifvGvQ15JSq2cOJj9ffzsI5T8EDAxvH905JS4 tQcsojAIxQqGO+8Elf74KN/udytwcM2zTY+cGuqCH2hg8M3VWQbGL4SRRjYI4dciXZPj wj3NAPb+aQGLs78EdDOgXQw41rS6CAwVXBo1yx1fAnI5Zb+XOeJlXXzeAV081w48sKSC tZAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v8vwTZLuhwp+bmBixmmWp52i36uK/epxo9J3L5qAyYw=; b=S+Abpxi7WLAh6fcvLfMRZRvGigo1mCyVG6XN2cCjRDfRM98kBKCxZkh5MPfpuSbxBD 1myq+COcCeD+qB933cZ32btikrvTpovI+yCvL717bBwSq7OgQgHH+/yTnJzhkly1i/Op 9RMlMuKX7p9F4YMyLUwPNIZ2njBYedP6AWc0Ehx3T9Ki9HmFoFv8eQ6WPrC5lCdzNKYi Fe4yeETM8heSKNfOrkwUX1dmSOkbMMtf6MZruKP+s3EOhIvt1hSSkQo2INzSi66zvtKZ i+pc7de6KrohoRwyk+6Gvp8rsCn0kKFIMpxP9PARcHHrMzllxRd9qQoSRKrpKfJkQ08I 2vPw== X-Gm-Message-State: APjAAAWii1pYQ0Pzonh1SnSvyw5McB7QqImCSbFvkUcaboooJxNGxmnH CrrelBoaCOfMvQKciI8h/WadIw== X-Google-Smtp-Source: APXvYqwqM6w1EFZ19R3JVc93kj/DKxukQ0NwhiM6EyRBOTehEAg9+aMsVIP9qi+b2TvlEKsDG8/HAQ== X-Received: by 2002:a5d:5302:: with SMTP id e2mr62712766wrv.347.1560794008245; Mon, 17 Jun 2019 10:53:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 18:53:16 +0100 Message-Id: <20190617175317.27557-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617175317.27557-1-peter.maydell@linaro.org> References: <20190617175317.27557-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 5/6] hw/timer/armv7m_systick: Forbid non-privileged accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Like most of the v7M memory mapped system registers, the systick registers are accessible to privileged code only and user accesses must generate a BusFault. We implement that for registers in the NVIC proper already, but missed it for systick since we implement it as a separate device. Correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/timer/armv7m_systick.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index a17317ce2fe..94640743b5d 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -75,11 +75,17 @@ static void systick_timer_tick(void *opaque) } } =20 -static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { SysTickState *s =3D opaque; uint32_t val; =20 + if (attrs.user) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + switch (addr) { case 0x0: /* SysTick Control and Status. */ val =3D s->control; @@ -121,14 +127,21 @@ static uint64_t systick_read(void *opaque, hwaddr add= r, unsigned size) } =20 trace_systick_read(addr, val, size); - return val; + *data =3D val; + return MEMTX_OK; } =20 -static void systick_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) { SysTickState *s =3D opaque; =20 + if (attrs.user) { + /* Generate BusFault for unprivileged accesses */ + return MEMTX_ERROR; + } + trace_systick_write(addr, value, size); =20 switch (addr) { @@ -172,11 +185,12 @@ static void systick_write(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", ad= dr); } + return MEMTX_OK; } =20 static const MemoryRegionOps systick_ops =3D { - .read =3D systick_read, - .write =3D systick_write, + .read_with_attrs =3D systick_read, + .write_with_attrs =3D systick_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, --=20 2.20.1