From nobody Sun Oct 5 14:30:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de ARC-Seal: i=1; a=rsa-sha256; t=1560784472; cv=none; d=zoho.com; s=zohoarc; b=IknkDz+fgFxFP0dI+vT2lvJacMJ9GE1c4tUYY6gMAzyhhXTLNCrN4J8R0QP9t3OUogEuP0LPZkiWF5NExHc5XxpVbEzf9VN4LlrlmgHZOPyyJdlXH8SyMFoR+8tAxNoBsEohCbWFFqMS++CQYRaDds5o9oKv6u2yXVymc+kjZlA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560784472; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=u2NpyhuyMq5SMtGpWpveRZeX8VLfu8jsFl2mp4I22F4=; b=bdbxz1kf+KxIBAZcZa78GBFHhoeGeyRD3p9H9yIKcm6N7D06PKPSb1xnRrHqP969CHE05VMeLsbsmHge9uJeNK/FN2jcpuHmHenez3tPEUc+xu1FS/V4aIj15S8mDAyuUPigqfv7JBylQzJQAQ3xHQaUdI5q8e7Hns8MsUC9R9s= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560784472103472.46494781420915; Mon, 17 Jun 2019 08:14:32 -0700 (PDT) Received: from localhost ([::1]:48396 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hctL1-0005Pl-Eq for importer@patchew.org; Mon, 17 Jun 2019 11:14:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47182) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcsje-0004e1-MX for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:35:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcsjc-0000XS-TZ for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:35:50 -0400 Received: from amazonia.uni-paderborn.de ([131.234.189.15]:34210) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcsjc-0000Wb-Mb for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:35:48 -0400 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1hcsja-0000IV-95; Mon, 17 Jun 2019 16:35:47 +0200 Received: from mail.uni-paderborn.de by magmaria with queue id 3427223-3; Mon, 17 Jun 2019 14:35:45 GMT X-Envelope-From: From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 16:35:31 +0200 Message-Id: <20190617143533.15013-2-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190617143533.15013-1-kbastian@mail.uni-paderborn.de> References: <20190617143533.15013-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.6.17.142717, AntiVirus-Engine: 5.63.0, AntiVirus-Data: 2019.6.4.5630002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 131.234.189.15 Subject: [Qemu-devel] [PATCH 1/3] target/tricore: Use DisasContextBase API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, david.brenken@efs-auto.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" this gets rid of the copied fields of TriCore's DisasContext and now uses the shared DisasContextBase, which is necessary for the conversion to translate_loop. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target/tricore/translate.c | 98 +++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 06c4485e55..a66a10c376 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -30,6 +30,7 @@ #include "exec/helper-gen.h" =20 #include "tricore-opcodes.h" +#include "exec/translator.h" #include "exec/log.h" =20 /* @@ -64,24 +65,14 @@ static const char *regnames_d[] =3D { }; =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc, next_pc; + DisasContextBase base; + target_ulong pc_succ_insn; uint32_t opcode; - int singlestep_enabled; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; - int bstate; } DisasContext; =20 -enum { - - BS_NONE =3D 0, - BS_STOP =3D 1, - BS_BRANCH =3D 2, - BS_EXCP =3D 3, -}; - enum { MODE_LL =3D 0, MODE_LU =3D 1, @@ -3230,12 +3221,12 @@ static inline void gen_save_pc(target_ulong pc) =20 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -3246,10 +3237,10 @@ static inline void gen_goto_tb(DisasContext *ctx, i= nt n, target_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); gen_save_pc(dest); - tcg_gen_exit_tb(ctx->tb, n); + tcg_gen_exit_tb(ctx->base.tb, n); } else { gen_save_pc(dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { /* raise exception debug */ } tcg_gen_exit_tb(NULL, 0); @@ -3261,9 +3252,9 @@ static void generate_trap(DisasContext *ctx, int clas= s, int tin) TCGv_i32 classtemp =3D tcg_const_i32(class); TCGv_i32 tintemp =3D tcg_const_i32(tin); =20 - gen_save_pc(ctx->pc); + gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); - ctx->bstate =3D BS_EXCP; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 tcg_temp_free(classtemp); tcg_temp_free(tintemp); @@ -3275,10 +3266,10 @@ static inline void gen_branch_cond(DisasContext *ct= x, TCGCond cond, TCGv r1, TCGLabel *jumpLabel =3D gen_new_label(); tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); =20 - gen_goto_tb(ctx, 1, ctx->next_pc); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); =20 gen_set_label(jumpLabel); - gen_goto_tb(ctx, 0, ctx->pc + address * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); } =20 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv = r1, @@ -3295,9 +3286,9 @@ static void gen_loop(DisasContext *ctx, int r1, int32= _t offset) =20 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); - gen_goto_tb(ctx, 1, ctx->pc + offset); + gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); gen_set_label(l1); - gen_goto_tb(ctx, 0, ctx->next_pc); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); } =20 static void gen_fcall_save_ctx(DisasContext *ctx) @@ -3306,7 +3297,7 @@ static void gen_fcall_save_ctx(DisasContext *ctx) =20 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); =20 tcg_temp_free(temp); @@ -3321,7 +3312,7 @@ static void gen_fret(DisasContext *ctx) tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 tcg_temp_free(temp); } @@ -3336,12 +3327,12 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, /* SB-format jumps */ case OPC1_16_SB_J: case OPC1_32_B_J: - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_CALL: case OPC1_16_SB_CALL: - gen_helper_1arg(call, ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_helper_1arg(call, ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_16_SB_JZ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); @@ -3433,26 +3424,26 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, break; /* B-format */ case OPC1_32_B_CALLA: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_FCALL: gen_fcall_save_ctx(ctx); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_FCALLA: gen_fcall_save_ctx(ctx); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JLA: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JL: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; /* BOL format */ case OPCM_32_BRC_EQ_NEQ: @@ -3551,7 +3542,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, gen_loop(ctx, r2, offset * 2); } else { /* OPC2_32_BRR_LOOPU */ - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); } break; case OPCM_32_BRR_JNE: @@ -3585,7 +3576,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 =20 @@ -3933,7 +3924,7 @@ static void decode_sr_system(CPUTriCoreState *env, Di= sasContext *ctx) case OPC2_16_SR_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ @@ -6557,11 +6548,11 @@ static void decode_rr_idirect(CPUTriCoreState *env,= DisasContext *ctx) tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_JLI: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_CALLI: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_FCALLI: @@ -6572,7 +6563,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, D= isasContext *ctx) generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) @@ -8382,7 +8373,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; break; case OPC2_32_SYS_RFM: if ((ctx->hflags & TRICORE_HFLAG_KUU) =3D=3D TRICORE_HFLAG_SM) { @@ -8395,7 +8386,7 @@ static void decode_sys_interrupts(CPUTriCoreState *en= v, DisasContext *ctx) gen_helper_rfm(cpu_env); gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); - ctx->bstate =3D BS_BRANCH; + ctx->base.is_jmp =3D DISAS_NORETURN; tcg_temp_free(tmp); } else { /* generate privilege trap */ @@ -8781,11 +8772,11 @@ static void decode_opc(CPUTriCoreState *env, DisasC= ontext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) =3D=3D 0) { - ctx->next_pc =3D ctx->pc + 2; + ctx->pc_succ_insn =3D ctx->base.pc_next + 2; decode_16Bit_opc(env, ctx); /* 32-Bit Instruction */ } else { - ctx->next_pc =3D ctx->pc + 4; + ctx->pc_succ_insn =3D ctx->base.pc_next + 4; decode_32Bit_opc(env, ctx); } } @@ -8798,32 +8789,31 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb, int max_insns) int num_insns =3D 0; =20 pc_start =3D tb->pc; - ctx.pc =3D pc_start; - ctx.saved_pc =3D -1; - ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; - ctx.bstate =3D BS_NONE; + ctx.base.pc_next =3D pc_start; + ctx.base.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.is_jmp =3D DISAS_NEXT; ctx.mem_idx =3D cpu_mmu_index(env, false); =20 tcg_clear_temp_count(); gen_tb_start(tb); - while (ctx.bstate =3D=3D BS_NONE) { - tcg_gen_insn_start(ctx.pc); + while (ctx.base.is_jmp =3D=3D DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; =20 - ctx.opcode =3D cpu_ldl_code(env, ctx.pc); + ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); decode_opc(env, &ctx, 0); =20 if (num_insns >=3D max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.next_pc); + gen_save_pc(ctx.pc_succ_insn); tcg_gen_exit_tb(NULL, 0); break; } - ctx.pc =3D ctx.next_pc; + ctx.base.pc_next =3D ctx.pc_succ_insn; } =20 gen_tb_end(tb, num_insns); - tb->size =3D ctx.pc - pc_start; + tb->size =3D ctx.base.pc_next - pc_start; tb->icount =3D num_insns; =20 if (tcg_check_temp_count()) { @@ -8835,7 +8825,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); qemu_log("\n"); qemu_log_unlock(); } --=20 2.22.0