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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We want to use vfp_expand_imm() in the AArch32 VFP decode; move it from the a64-only header/source file to the AArch32 one (which is always compiled even for AArch64). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190613163917.28589-2-peter.maydell@linaro.org --- target/arm/translate-a64.h | 1 - target/arm/translate.h | 7 +++++++ target/arm/translate-a64.c | 32 -------------------------------- target/arm/translate-vfp.inc.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 33 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9569bc5963d..9ab40872d85 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -39,7 +39,6 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); -uint64_t vfp_expand_imm(int size, uint8_t imm8); bool sve_access_check(DisasContext *s); =20 /* We should have at some point before trying to access an FP register diff --git a/target/arm/translate.h b/target/arm/translate.h index dc06dce7675..bc1617809da 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -237,6 +237,13 @@ static inline void gen_ss_advance(DisasContext *s) } } =20 +/* + * Given a VFP floating point constant encoded into an 8 bit immediate in = an + * instruction, expand it to the actual constant value of the specified + * size, as per the VFPExpandImm() pseudocode in the Arm ARM. + */ +uint64_t vfp_expand_imm(int size, uint8_t imm8); + /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ae739f65756..97f4164fbbc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6380,38 +6380,6 @@ static void disas_fp_3src(DisasContext *s, uint32_t = insn) } } =20 -/* The imm8 encodes the sign bit, enough bits to represent an exponent in - * the range 01....1xx to 10....0xx, and the most significant 4 bits of - * the mantissa; see VFPExpandImm() in the v8 ARM ARM. - */ -uint64_t vfp_expand_imm(int size, uint8_t imm8) -{ - uint64_t imm; - - switch (size) { - case MO_64: - imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | - extract32(imm8, 0, 6); - imm <<=3D 48; - break; - case MO_32: - imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | - (extract32(imm8, 0, 6) << 3); - imm <<=3D 16; - break; - case MO_16: - imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | - (extract32(imm8, 0, 6) << 6); - break; - default: - g_assert_not_reached(); - } - return imm; -} - /* Floating point immediate * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 * +---+---+---+-----------+------+---+------------+-------+------+------+ diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 709fc65374d..a66084f6e36 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -30,6 +30,39 @@ #include "decode-vfp.inc.c" #include "decode-vfp-uncond.inc.c" =20 +/* + * The imm8 encodes the sign bit, enough bits to represent an exponent in + * the range 01....1xx to 10....0xx, and the most significant 4 bits of + * the mantissa; see VFPExpandImm() in the v8 ARM ARM. + */ +uint64_t vfp_expand_imm(int size, uint8_t imm8) +{ + uint64_t imm; + + switch (size) { + case MO_64: + imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | + extract32(imm8, 0, 6); + imm <<=3D 48; + break; + case MO_32: + imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | + (extract32(imm8, 0, 6) << 3); + imm <<=3D 16; + break; + case MO_16: + imm =3D (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | + (extract32(imm8, 0, 6) << 6); + break; + default: + g_assert_not_reached(); + } + return imm; +} + /* * Return the offset of a 16-bit half of the specified VFP single-precision * register. If top is true, returns the top 16 bits; otherwise the bottom --=20 2.20.1