From nobody Tue Feb 10 06:43:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560689494; cv=none; d=zoho.com; s=zohoarc; b=c+PC3Cr5l6a/4DGVRVUbXlm2HlnVXWpTgUT9GGEnWQbvPXDcR45nIh9/czmzp8oLrPOz9UZIlJEZVJmv83PslitYzi4/hH0mHVEgVW8hGhOBNha1NbJeVAvA/NhQyFsRb6HUeQA39YG1aVfiHiPDX+gLBD/IeOnSy/A8MBjy23s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560689494; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=n5mu1E9aC3RmMXVG1JPjkzole2bTRDvjLLnYhu0dG8c=; b=VhbybYhGpaO58dWpyxQEgRoVmJBRbirOC4++5cUKHL6AGKuaNNrDWiHre0wAqYZF1ctv6JdKsMG38xSu4lQWeF+LuvHXoNeUjSWDO20fMXWd1Pnv78e+b3wT1U40npjJ4W8SCmAUvbLQSn+6v7Er0Q9U3f3hEEQKd0Tp+bP+7Lc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560689494700842.3270076707133; Sun, 16 Jun 2019 05:51:34 -0700 (PDT) Received: from localhost ([::1]:39536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcUdB-0004yE-AS for importer@patchew.org; Sun, 16 Jun 2019 08:51:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42353) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcUQJ-000423-9A for qemu-devel@nongnu.org; Sun, 16 Jun 2019 08:38:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcUQG-000675-T2 for qemu-devel@nongnu.org; Sun, 16 Jun 2019 08:38:15 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:46402 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcUQG-000661-L9; Sun, 16 Jun 2019 08:38:12 -0400 Received: from host86-173-229-95.range86-173.btcentralplus.com ([86.173.229.95] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hcUQ2-0001jp-JY; Sun, 16 Jun 2019 13:37:59 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 16 Jun 2019 13:37:44 +0100 Message-Id: <20190616123751.781-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190616123751.781-1-mark.cave-ayland@ilande.co.uk> References: <20190616123751.781-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.173.229.95 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v3 08/15] target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based upon xA and xB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 15 ++++++--------- target/ppc/helper.h | 12 ++++++------ target/ppc/translate/vsx-impl.inc.c | 30 ++++++++++++++++++++++++------ 3 files changed, 36 insertions(+), 21 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 44dff1b459..902d63b139 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2179,10 +2179,9 @@ VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0) * nbits - number of fraction bits */ #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ int i; \ int fe_flag =3D 0; \ int fg_flag =3D 0; \ @@ -2431,10 +2430,9 @@ VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1) VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1) VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0) =20 -void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode) +void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; int64_t exp_a, exp_b; uint32_t cc; =20 @@ -2492,10 +2490,9 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t op= code) } =20 #define VSX_SCALAR_CMP(op, ordered) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ uint32_t cc =3D 0; = \ bool vxsnan_flag =3D false, vxvc_flag =3D false; = \ \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f56476ec41..0ab1ef2aee 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -375,7 +375,7 @@ DEF_HELPER_2(xsdivqp, void, env, i32) DEF_HELPER_3(xsredp, void, env, vsr, vsr) DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) -DEF_HELPER_2(xstdivdp, void, env, i32) +DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xstsqrtdp, void, env, i32) DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) @@ -389,10 +389,10 @@ DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xscmpexpdp, void, env, i32) +DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscmpexpqp, void, env, i32) -DEF_HELPER_2(xscmpodp, void, env, i32) -DEF_HELPER_2(xscmpudp, void, env, i32) +DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscmpudp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscmpoqp, void, env, i32) DEF_HELPER_2(xscmpuqp, void, env, i32) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) @@ -460,7 +460,7 @@ DEF_HELPER_4(xvdivdp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xvredp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) -DEF_HELPER_2(xvtdivdp, void, env, i32) +DEF_HELPER_4(xvtdivdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xvtsqrtdp, void, env, i32) DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) @@ -498,7 +498,7 @@ DEF_HELPER_4(xvdivsp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xvresp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) -DEF_HELPER_2(xvtdivsp, void, env, i32) +DEF_HELPER_4(xvtdivsp, void, env, i32, vsr, vsr) DEF_HELPER_2(xvtsqrtsp, void, env, i32) DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 36fb740f6a..9b4603ac33 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1061,6 +1061,24 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + gen_helper_##name(cpu_env, opc, xa, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1089,7 +1107,7 @@ GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) @@ -1103,10 +1121,10 @@ GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_IS= A300) GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) @@ -1174,7 +1192,7 @@ GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) @@ -1208,7 +1226,7 @@ GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) --=20 2.11.0