From nobody Tue Feb 10 13:37:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560689133; cv=none; d=zoho.com; s=zohoarc; b=RTnCgKeZsLcRJptMyBJ8phJvYf+8xecXYush8reb69T1pLwLsSgtHoo/swcWAZxwjk0Nhcwnhe3D3Zgpyk4jJeafUxvlrNQTzTs0WkGF2Mmi/T2yqorDrKLHnSeNPiqGayLl4UFq4wJc5BM4DxgcoI8zKFXi8HlZzTjrVPqcarE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560689133; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=PPetG5bt6D4kqZhRnrxnCT8trgyyXV3w+qvqgJXE9sY=; b=LNuFsGpL6z4J0PZrhYSME8f99Jq3fNnbZN4A4f9OVXNv0MRMrPLX2T2gK6Td2XRwJlSEs8GzcN3tou4fC+dsbtqKasROJ5688uSy+Dy5xGQsHU3lZctm3WqLslumVU0EPDZPbHX/jVTQsI41ejz7CA+hick7qoV/QU4kuXJmWew= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560689133438357.96267343619957; Sun, 16 Jun 2019 05:45:33 -0700 (PDT) Received: from localhost ([::1]:39500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcUXM-0001EV-Fe for importer@patchew.org; Sun, 16 Jun 2019 08:45:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42282) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcUQG-0003xQ-7t for qemu-devel@nongnu.org; Sun, 16 Jun 2019 08:38:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcUQE-00064Q-TC for qemu-devel@nongnu.org; Sun, 16 Jun 2019 08:38:12 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:46386 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcUQE-00063Z-Kq; Sun, 16 Jun 2019 08:38:10 -0400 Received: from host86-173-229-95.range86-173.btcentralplus.com ([86.173.229.95] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hcUPz-0001jp-Ih; Sun, 16 Jun 2019 13:37:57 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 16 Jun 2019 13:37:42 +0100 Message-Id: <20190616123751.781-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190616123751.781-1-mark.cave-ayland@ilande.co.uk> References: <20190616123751.781-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.173.229.95 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v3 06/15] target/ppc: introduce separate generator and helper for xscvqpdp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new generator and helper function which perform the decode based upon xT and xB at translation time. The xscvqpdp helper is the only 2 parameter xT/xB implementation that requi= res the opcode to be passed as an additional parameter, so handling this separa= tely allows us to optimise the conversion in the next commit. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 5 ++--- target/ppc/helper.h | 2 +- target/ppc/translate/vsx-impl.inc.c | 18 +++++++++++++++++- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 012dfdac3e..230ee2f072 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2899,10 +2899,9 @@ VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, V= srH(2 * i + 1), VsrW(i), 0) * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be * added to this later. */ -void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode) +void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; ppc_vsr_t t =3D { }; float_status tstat; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f6a97cedc6..5d15166988 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -405,7 +405,7 @@ DEF_HELPER_2(xscvdphp, void, env, i32) DEF_HELPER_2(xscvdpqp, void, env, i32) DEF_HELPER_2(xscvdpsp, void, env, i32) DEF_HELPER_2(xscvdpspn, i64, env, i64) -DEF_HELPER_2(xscvqpdp, void, env, i32) +DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscvqpsdz, void, env, i32) DEF_HELPER_2(xscvqpswz, void, env, i32) DEF_HELPER_2(xscvqpudz, void, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index b24be00ccf..ffbe3b0fac 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -999,6 +999,23 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) =20 +static void gen_xscvqpdp(DisasContext *ctx) +{ + TCGv_i32 opc; + TCGv_ptr xt, xb; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + opc =3D tcg_const_i32(ctx->opcode); + xt =3D gen_vsr_ptr(xT(ctx->opcode)); + xb =3D gen_vsr_ptr(xB(ctx->opcode)); + gen_helper_xscvqpdp(cpu_env, opc, xt, xb); + tcg_temp_free_i32(opc); + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xb); +} + #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) = \ static void gen_##name(DisasContext *ctx) = \ { = \ @@ -1087,7 +1104,6 @@ GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA= 300) GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) --=20 2.11.0