From nobody Sat Feb 7 06:20:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1560614398; cv=none; d=zoho.com; s=zohoarc; b=G8Apa2vn0LHSjOb+j1K0P8WV+z5C9b5SJnuK5Iv+qg3HZ8QjxGQ8LZj2Vvu3QSkBz1lqxAz96clLbx55A/VyPgXfBo3CCy8JBpMZpQ7RybBzxj9kpjFLaa+XbSt3J72eqm1MR8RXRPoV/YbLm1txc8mdNf2kO2f0j97bvsCZUnM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560614398; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Z/e/F6G4j21zshpMn8XxaXv7ByRqcMN0ZCNn7LP/XPc=; b=GTEjUUvc8NYUvpPHIHzZLq2VbbBDcHMQUbnd0Jno7pH8sdlxNRDkxeXhxz8tgu8lcCt6bDiZLzBCYuEhoCAMY0Vdos5do7rLapEj38dQwj8OHyc+r+1wC7zUXkUXwcHgPf4pNZdyYMmsBXzcUMdOwMbkBT9FgxM6icMzsg62rC8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560614398023326.16660707150754; Sat, 15 Jun 2019 08:59:58 -0700 (PDT) Received: from localhost ([::1]:32998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcB5u-0001Y0-QU for importer@patchew.org; Sat, 15 Jun 2019 11:59:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35709) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcAqr-0003v4-Ib for qemu-devel@nongnu.org; Sat, 15 Jun 2019 11:44:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcAqp-0000GP-AW for qemu-devel@nongnu.org; Sat, 15 Jun 2019 11:44:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35456) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hcAqj-0008HD-9m; Sat, 15 Jun 2019 11:44:15 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E6B953082E1F; Sat, 15 Jun 2019 15:44:10 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-41.brq.redhat.com [10.40.204.41]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A8378106F752; Sat, 15 Jun 2019 15:44:09 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 15 Jun 2019 17:43:36 +0200 Message-Id: <20190615154352.26824-8-philmd@redhat.com> In-Reply-To: <20190615154352.26824-1-philmd@redhat.com> References: <20190615154352.26824-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Sat, 15 Jun 2019 15:44:10 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 07/23] target/arm: Declare some function publicly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In few commits we will split the v7-M functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 69 +++++++++++++----------------------------- target/arm/internals.h | 45 +++++++++++++++++++++++++++ 2 files changed, 66 insertions(+), 48 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9a3766b759..a1e74cc471 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -35,17 +35,6 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ =20 #ifndef CONFIG_USER_ONLY -/* Cacheability and shareability attributes for a memory access */ -typedef struct ARMCacheAttrs { - unsigned int attrs:8; /* as in the MAIR register encoding */ - unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ -} ARMCacheAttrs; - -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); =20 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, @@ -53,24 +42,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_= ulong address, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs); =20 -/* Security attributes for an address, as returned by v8m_security_lookup.= */ -typedef struct V8M_SAttributes { - bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE= */ - bool ns; - bool nsc; - uint8_t sregion; - bool srvalid; - uint8_t iregion; - bool irvalid; -} V8M_SAttributes; - -static void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_i= dx, - V8M_SAttributes *sattrs); #endif =20 -static void switch_mode(CPUARMState *env, int mode); - static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -7552,7 +7525,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) return 0; } =20 -static void switch_mode(CPUARMState *env, int mode) +void switch_mode(CPUARMState *env, int mode) { ARMCPU *cpu =3D env_archcpu(env); =20 @@ -7574,7 +7547,7 @@ void aarch64_sync_64_to_32(CPUARMState *env) =20 #else =20 -static void switch_mode(CPUARMState *env, int mode) +void switch_mode(CPUARMState *env, int mode) { int old_mode; int i; @@ -7988,9 +7961,9 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) * stack pointers if it is done for the CONTROL register for the current * security state. */ -static void write_v7m_control_spsel_for_secstate(CPUARMState *env, - bool new_spsel, - bool secstate) +void write_v7m_control_spsel_for_secstate(CPUARMState *env, + bool new_spsel, + bool secstate) { bool old_is_psp =3D v7m_using_psp(env); =20 @@ -8015,7 +7988,7 @@ static void write_v7m_control_spsel_for_secstate(CPUA= RMState *env, * Write to v7M CONTROL.SPSEL bit. This may change the current * stack pointer between Main and Process stack pointers. */ -static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) +void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) { write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); } @@ -8041,7 +8014,7 @@ void write_v7m_exception(CPUARMState *env, uint32_t n= ew_exc) } =20 /* Switch M profile security state between NS and S */ -static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) +void switch_v7m_security_state(CPUARMState *env, bool new_secstate) { uint32_t new_ss_msp, new_ss_psp; =20 @@ -9447,7 +9420,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static void arm_log_exception(int idx) +void arm_log_exception(int idx) { if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *exc =3D NULL; @@ -12122,9 +12095,9 @@ static bool v8m_is_sau_exempt(CPUARMState *env, (address >=3D 0xe00ff000 && address <=3D 0xe00fffff); } =20 -static void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_i= dx, - V8M_SAttributes *sattrs) +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + V8M_SAttributes *sattrs) { /* Look up the security attributes for this address. Compare the * pseudocode SecurityCheck() function. @@ -12229,11 +12202,11 @@ static void v8m_security_lookup(CPUARMState *env,= uint32_t address, } } =20 -static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion) { /* Perform a PMSAv8 MPU lookup (without also doing the SAU check * that a full phys-to-virt translation does). @@ -12633,11 +12606,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheA= ttrs s1, ARMCacheAttrs s2) * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUIdx_S12NS= E1) { /* Call ourselves recursively to do the stage 1 and then stage 2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a02f458f3..04711b317a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -985,4 +985,49 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } =20 +void arm_log_exception(int idx); + +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ +} ARMCacheAttrs; + +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); + +/* Security attributes for an address, as returned by v8m_security_lookup.= */ +typedef struct V8M_SAttributes { + bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE= */ + bool ns; + bool nsc; + uint8_t sregion; + bool srvalid; + uint8_t iregion; + bool irvalid; +} V8M_SAttributes; + +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + V8M_SAttributes *sattrs); + +void switch_mode(CPUARMState *, int); + +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion); + +void write_v7m_control_spsel_for_secstate(CPUARMState *env, + bool new_spsel, + bool secstate); + +void write_v7m_control_spsel(CPUARMState *env, bool new_spsel); + +void switch_v7m_security_state(CPUARMState *env, bool new_secstate); + #endif --=20 2.20.1