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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v3 33/50] target/riscv: fetch code with translator_ld X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "Emilio G. Cota" , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 313c27b700..899abf41fa 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu->env_ptr; =20 - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode =3D translator_ldl(env, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 --=20 2.20.1