From nobody Sat Apr 27 07:28:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560514874; cv=none; d=zoho.com; s=zohoarc; b=WUQFq1T6URsKEvrzSBWXjtNBOdobsH/CUvAqvFVDBnHS4qKMFS9BpeWrfOTHlVqK4BrM14rVnjU5AnIgRIZysT9Wk9Ps8Ash1IHTM4zRCf/gfq6nyJ+O/PqFNgg8qHnLDNDp0cdYaIb5a9Wfc/CoazH4YIzJ1IYdhNGlP8nQ8os= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560514874; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=1/imMTLThbsIUg9X7x53ZVTveZQJ+RedU+3e0N9kmuw=; b=VJ7R2RlIKIGrwOjQmKOIAMRpig0edovAHwtdOa/zwuhYMVL/YLFYvRfhipaLaRW7zj3DcrwxOmTBwjtppbn3CvanR0LKxnTjY7fOj7UH3ItB+G5HJzDYlxY/MAtE8NwSoUtstd/ZdarZHKMrvDPGBTFosNNMhDtWVt9lMGI4+J8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560514874570283.9566990873998; Fri, 14 Jun 2019 05:21:14 -0700 (PDT) Received: from localhost ([::1]:50862 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hblCe-0001Us-D1 for importer@patchew.org; Fri, 14 Jun 2019 08:21:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51852) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hbl2L-0002Yy-OH for qemu-devel@nongnu.org; Fri, 14 Jun 2019 08:10:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hbl2J-0003tL-DN for qemu-devel@nongnu.org; Fri, 14 Jun 2019 08:10:29 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:39363) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hbl2J-0003VC-1o for qemu-devel@nongnu.org; Fri, 14 Jun 2019 08:10:27 -0400 Received: by mail-wm1-f68.google.com with SMTP id z23so2081756wma.4 for ; Fri, 14 Jun 2019 05:09:55 -0700 (PDT) Received: from localhost ([83.137.6.186]) by smtp.gmail.com with ESMTPSA id f204sm3969987wme.18.2019.06.14.05.09.52 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 05:09:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=1/imMTLThbsIUg9X7x53ZVTveZQJ+RedU+3e0N9kmuw=; b=oc369jip1lktg8t5H1w1UiwDEpoisuohNV0khn9oR3fyd6eLNqM4skv9VT/H9xX+LB ZBrQtwujgFxYj4CX13jR6EMJ+s4SUHX3sRab3gP4hSldKWBCzdhEHSEW0eg63wwIIQDu 2BUVmc/K5mr3/zwB1BLht9kTRwG5FW+/DQXIUStckt9qh0PwlS9+JACVgVV7ctPzmbkL sHkRT0wHzzNSLB8AMtd0+Pcmf2AJrfPyAmxyFo6G5xs7u9OnHGR8UJlzbRaRiYrchWkM gxYk+C/wkLrep9K3KWYD7d9dGY9eoA/eYaBas1QAxdwwqxSTDyQ1LkgxX3FDhhpFxqDy FAcQ== X-Gm-Message-State: APjAAAXbrwZDyq1TrIWf+lI3LC1XaD7ulWj24MhGoKlaaq5yshYLzL61 imEMON8uqUHKtiaEFnxf/Jxx3L812lGtZA== X-Google-Smtp-Source: APXvYqy56TBxLXwEG86ivExecUEC4oXKSbyP8sno4qVcYm/t+du44rBJWBmRtQWWlo+3rf70h91Z6Q== X-Received: by 2002:a1c:4d6:: with SMTP id 205mr7166914wme.148.1560514194103; Fri, 14 Jun 2019 05:09:54 -0700 (PDT) Date: Fri, 14 Jun 2019 05:08:30 -0700 Message-Id: <20190614120830.21850-1-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.68 Subject: [Qemu-devel] [PATCH] RISC-V: Fix a memory leak when realizing a sifive_e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in SiFiveESoCState, so instead we just include them within the struct. Thanks to Peter for pointing out the bug and suggesting the fix! Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/sifive_e.c | 12 +++++------- include/hw/riscv/sifive_e.h | 2 ++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 80ac56fa7d5e..83375afcd1d6 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -158,17 +158,15 @@ static void riscv_sifive_e_soc_realize(DeviceState *d= ev, Error **errp) =20 SiFiveESoCState *s =3D RISCV_E_SOC(dev); MemoryRegion *sys_mem =3D get_system_memory(); - MemoryRegion *xip_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); =20 object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); =20 /* Mask ROM */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom", + memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom", memmap[SIFIVE_E_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, mask_rom); + memmap[SIFIVE_E_MROM].base, &s->mask_rom); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_E_PLIC].base, @@ -228,10 +226,10 @@ static void riscv_sifive_e_soc_realize(DeviceState *d= ev, Error **errp) memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); =20 /* Flash memory */ - memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", + memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip", memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_set_readonly(xip_mem, true); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_me= m); + memory_region_set_readonly(&s->xip_mem, true); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, &s->xi= p_mem); } =20 static void riscv_sifive_e_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 3b14eb74621f..d175b24cb209 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -33,6 +33,8 @@ typedef struct SiFiveESoCState { RISCVHartArrayState cpus; DeviceState *plic; SIFIVEGPIOState gpio; + MemoryRegion xip_mem; + MemoryRegion mask_rom; } SiFiveESoCState; =20 typedef struct SiFiveEState { --=20 2.21.0