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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y24sm2091238wmi.10.2019.06.14.03.45.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Jun 2019 03:45:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=08Z7f4ISnw8IsjRb+rdkg212YqVM77nn40XmfzlB6eY=; b=HBOOEWHYhDoCDaVMxHlMQskSwEIpWvgwGujwDhIOBvMmKXeKs/2nOg9US7rvOE92VJ md4O4MyvJyCmfXru1ocEXzs4XTh0I4RGfHxzSKJxUZDluUKFStFNhYi4TEmxj5M0L18F y1cA0MksR0JX7wNOYbtCeXLIk15DRAjPA+iUVtrBFyRA7lt5a5gn/+0TyFBb+Q0r9f8f KtcW6R53WH4kiHZwMWwF7Cd+lyaMgs1GZF5MTViVpCvENuUiaomeS8Ng9B8oXJ6TUxVa 41iMo5ia7225Mv0+C6/1syaaZc8uRwzBB9F9ClUWZvGuR8ZfPVuK4TSOnSzqb0rBo4XB wJTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=08Z7f4ISnw8IsjRb+rdkg212YqVM77nn40XmfzlB6eY=; b=Ly4VzWPjm7eHyo70X8Rn+QcmJc/gQbZY3BByPLVUlBpO1Uly6KgUIcG61iSgacR5/f wGpxpCybHMBdkbrJoFKkgkteKPgpQDSAL8hIbrQt6xqUbpRMr8+nlCEyPCa8L3VneoTU 2RKIXyA5e2yDlpafRR1DOMP211Su5Yg/Po3BMwa0ME6oTZnj0lWzbOV8pbdP9Nk4LGPG Qc1Ab3z2TIh/Dlg4bCXqKBXjT1OE6EAfl1kkfOsuy4ZH7QEoeS4Q5GR/lkOkfMGfokXx HOvm2xsUgwpnYPnWZ1g1X/gqhiDTxnO55R8875OHMYacxPMVjOGeG+YQbYqea+WHowM/ kRxQ== X-Gm-Message-State: APjAAAXngjKMKprABJ5GfhR7THLroYOvsY8JdwCa4N6hQiCOr0VFDCBY eWFdpb1NO9lAZb7BjPd1v8GynQbrXh9OQg== X-Google-Smtp-Source: APXvYqy0kZkDbtYWpYNivI9UjFC/x1x0oakT3xeI5sGrR9BJFU8cj5Hyt9XTijU5xfLCHo995KTv8w== X-Received: by 2002:a1c:7f96:: with SMTP id a144mr7296493wmd.124.1560509101448; Fri, 14 Jun 2019 03:45:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 14 Jun 2019 11:44:57 +0100 Message-Id: <20190614104457.24703-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190614104457.24703-1-peter.maydell@linaro.org> References: <20190614104457.24703-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 2/2] target/arm: Only implement doubles if the FPU supports them X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP=3D=3D0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 +++ target/arm/translate-vfp.inc.c | 84 ++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92298624215..29be1f7ea97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3382,6 +3382,12 @@ static inline bool isar_feature_aa32_fpshvec(const A= RMISARegisters *id) return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point */ + return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 85187bcc9dc..a3df81d3b07 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -173,6 +173,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) ((a->vm | a->vn | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd =3D a->vd; rn =3D a->vn; rm =3D a->vm; @@ -301,6 +306,11 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINM= AXNM *a) ((a->vm | a->vn | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd =3D a->vd; rn =3D a->vn; rm =3D a->vm; @@ -382,6 +392,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) ((a->vm | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd =3D a->vd; rm =3D a->vm; =20 @@ -440,6 +455,11 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd =3D a->vd; rm =3D a->vm; =20 @@ -1268,6 +1288,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3Op= DPFn *fn, return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1413,6 +1437,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2Op= DPFn *fn, int vd, int vm) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1773,6 +1801,10 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp= *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -1878,6 +1910,10 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2028,6 +2064,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2097,6 +2137,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2159,6 +2203,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2215,6 +2263,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2272,6 +2324,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2327,6 +2383,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2351,6 +2411,10 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_= sp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2375,6 +2439,10 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_= dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2425,6 +2493,10 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_V= CVT_int_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2461,6 +2533,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2550,6 +2626,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2642,6 +2722,10 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_V= CVT_dp_int *a) return false; } =20 + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1