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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y6sm2010576wrp.12.2019.06.13.05.15.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 05:15:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5gtpw2YUK/SlJN0xIUzASKxApJAmaIC/1IkdztKlHx0=; b=UNa8JizKuD3noTjRRWXOi0qVIDZpZkTbDbpGSR+M99Rw9+nfjjk5UcNsXGAjb75E/d 4P9aqhhPimpcu2HNpgluey1XDs2LNE8P+JAGtxz9UIDtlE0suJtfMRpD0/nsC4IOb+wL VoUJd6RBubV35YK2sHnjXjTlQKvbgAt66Nzgl158aulsq3bhZo+IxgvXwMxtPJGvHoyv OkBp6R3ntNcPr9SpVLZ2EBp/aHGflEkCkXPRQoy7EmA+XsPlFiM8gXGohoQhr23Qaz9N FoKSTEZQN0OnCUl3mIwFqV3C0DTkexSoKy9Iyv8tcQ9iVQ1AToe6JXZskqalXPT4eiUj k/Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5gtpw2YUK/SlJN0xIUzASKxApJAmaIC/1IkdztKlHx0=; b=HtHdwLatQxsazZXLSu+kr0tgE1wMv4JCEKUdFHBMmtaJT0Q5aTX5qH3nlYLELZPC1w h0SjwtKO3HThrHSulClzoXCDFI6lGx48QY9ZdTtoR7GD4Ik7HxIhWAWxCGvVZvIbYQob ZNXEvx2+PCWDRr5pGnOCmNrxXRvnqydqUXJ2AESt5/yWsViZ5KHStv7ZPruBHc5V8SNY PBVf3YatWSoXZiJK6TblheyVfWaHQEr/q/bylw/0mBhluox3zMfyBBYfckSLY6EEnHsN RIVs/6ZNu6czndJc2u/uZaZqtY+1OzMf0T+b3Fg2+GbHwBwrv6tM2vAAARxT/VQjK6nj yUxQ== X-Gm-Message-State: APjAAAW+eatYEdhDdm1HcCaAeMxRHD9fmy2hp7R8AF5Xx53r/cMsVab+ 0UAT5d63lp3yBgl1U1lz4eYv0CSsR4x1tw== X-Google-Smtp-Source: APXvYqxRHNjzcJA5tnftSwf64b6oXCqoIiXghOZlM0ZJWrqg011cY6GI1TpJLnpgGfhvX+2EHyRQgg== X-Received: by 2002:a05:600c:2149:: with SMTP id v9mr3470964wml.141.1560428125378; Thu, 13 Jun 2019 05:15:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Jun 2019 13:14:32 +0100 Message-Id: <20190613121433.5246-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190613121433.5246-1-peter.maydell@linaro.org> References: <20190613121433.5246-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 47/48] target/arm: Convert float-to-integer VCVT insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 72 ++++++++++ target/arm/translate.c | 241 +-------------------------------- target/arm/vfp.decode | 6 + 3 files changed, 80 insertions(+), 239 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index db07fdd8736..8216dba796e 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2578,3 +2578,75 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) tcg_temp_free_ptr(fpst); return true; } + +static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + vm =3D tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizs(vm, vm, fpst); + } else { + gen_helper_vfp_tosis(vm, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizs(vm, vm, fpst); + } else { + gen_helper_vfp_touis(vm, vm, fpst); + } + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) +{ + TCGv_i32 vd; + TCGv_i64 vm; + TCGv_ptr fpst; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + vm =3D tcg_temp_new_i64(); + vd =3D tcg_temp_new_i32(); + neon_load_reg64(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizd(vd, vm, fpst); + } else { + gen_helper_vfp_tosid(vd, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizd(vd, vm, fpst); + } else { + gen_helper_vfp_touid(vd, vm, fpst); + } + } + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i64(vm); + tcg_temp_free_ptr(fpst); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index d7a77fca9ac..4a66a35a7f6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1418,9 +1418,7 @@ static inline void gen_vfp_##name(int dp, int neon) \ tcg_temp_free_ptr(statusptr); \ } =20 -VFP_GEN_FTOI(toui) VFP_GEN_FTOI(touiz) -VFP_GEN_FTOI(tosi) VFP_GEN_FTOI(tosiz) #undef VFP_GEN_FTOI =20 @@ -1612,33 +1610,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) } =20 #define tcg_gen_ld_f32 tcg_gen_ld_i32 -#define tcg_gen_ld_f64 tcg_gen_ld_i64 #define tcg_gen_st_f32 tcg_gen_st_i32 -#define tcg_gen_st_f64 tcg_gen_st_i64 - -static inline void gen_mov_F0_vreg(int dp, int reg) -{ - if (dp) - tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); -} - -static inline void gen_mov_F1_vreg(int dp, int reg) -{ - if (dp) - tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); -} - -static inline void gen_mov_vreg_F0(int dp, int reg) -{ - if (dp) - tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); -} =20 #define ARM_CP_RW_BIT (1 << 20) =20 @@ -2983,9 +2955,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask; - int dp, veclen; - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { return 1; } @@ -3005,214 +2974,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) return 0; } } - - if (extract32(insn, 28, 4) =3D=3D 0xf) { - /* - * Encodings with T=3D1 (Thumb) or unconditional (ARM): these - * were all handled by the decodetree decoder, so any insn - * patterns which get here must be UNDEF. - */ - return 1; - } - - /* - * FIXME: this access check should not take precedence over UNDEF - * for invalid encodings; we will generate incorrect syndrome informat= ion - * for attempts to execute invalid vfp/neon encodings with FP disabled. - */ - if (!vfp_access_check(s)) { - return 0; - } - - dp =3D ((insn & 0xf00) =3D=3D 0xb00); - switch ((insn >> 24) & 0xf) { - case 0xe: - if (insn & (1 << 4)) { - /* already handled by decodetree */ - return 1; - } else { - /* data processing */ - bool rd_is_dp =3D dp; - bool rm_is_dp =3D dp; - bool no_output =3D false; - - /* The opcode is in bits 23, 21, 20 and 6. */ - op =3D ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) = & 1); - rn =3D VFP_SREG_N(insn); - - switch (op) { - case 0 ... 14: - /* Already handled by decodetree */ - return 1; - case 15: - switch (rn) { - case 0 ... 23: - case 28 ... 31: - /* Already handled by decodetree */ - return 1; - default: - break; - } - default: - break; - } - - if (op =3D=3D 15) { - /* rn is opcode, encoded as per VFP_SREG_N. */ - switch (rn) { - case 0x18: /* vcvtr.u32.fxx */ - case 0x19: /* vcvtz.u32.fxx */ - case 0x1a: /* vcvtr.s32.fxx */ - case 0x1b: /* vcvtz.s32.fxx */ - rd_is_dp =3D false; - break; - - default: - return 1; - } - } else if (dp) { - /* rn is register number */ - VFP_DREG_N(rn, insn); - } - - if (rd_is_dp) { - VFP_DREG_D(rd, insn); - } else { - rd =3D VFP_SREG_D(insn); - } - if (rm_is_dp) { - VFP_DREG_M(rm, insn); - } else { - rm =3D VFP_SREG_M(insn); - } - - veclen =3D s->vec_len; - if (op =3D=3D 15 && rn > 3) { - veclen =3D 0; - } - - /* Shut up compiler warnings. */ - delta_m =3D 0; - delta_d =3D 0; - bank_mask =3D 0; - - if (veclen > 0) { - if (dp) - bank_mask =3D 0xc; - else - bank_mask =3D 0x18; - - /* Figure out what type of vector operation this is. */ - if ((rd & bank_mask) =3D=3D 0) { - /* scalar */ - veclen =3D 0; - } else { - if (dp) - delta_d =3D (s->vec_stride >> 1) + 1; - else - delta_d =3D s->vec_stride + 1; - - if ((rm & bank_mask) =3D=3D 0) { - /* mixed scalar/vector */ - delta_m =3D 0; - } else { - /* vector */ - delta_m =3D delta_d; - } - } - } - - /* Load the initial operands. */ - if (op =3D=3D 15) { - switch (rn) { - default: - /* One source operand. */ - gen_mov_F0_vreg(rm_is_dp, rm); - break; - } - } else { - /* Two source operands. */ - gen_mov_F0_vreg(dp, rn); - gen_mov_F1_vreg(dp, rm); - } - - for (;;) { - /* Perform the calculation. */ - switch (op) { - case 15: /* extension space */ - switch (rn) { - case 24: /* ftoui */ - gen_vfp_toui(dp, 0); - break; - case 25: /* ftouiz */ - gen_vfp_touiz(dp, 0); - break; - case 26: /* ftosi */ - gen_vfp_tosi(dp, 0); - break; - case 27: /* ftosiz */ - gen_vfp_tosiz(dp, 0); - break; - default: /* undefined */ - g_assert_not_reached(); - } - break; - default: /* undefined */ - return 1; - } - - /* Write back the result, if any. */ - if (!no_output) { - gen_mov_vreg_F0(rd_is_dp, rd); - } - - /* break out of the loop if we have finished */ - if (veclen =3D=3D 0) { - break; - } - - if (op =3D=3D 15 && delta_m =3D=3D 0) { - /* single source one-many */ - while (veclen--) { - rd =3D ((rd + delta_d) & (bank_mask - 1)) - | (rd & bank_mask); - gen_mov_vreg_F0(dp, rd); - } - break; - } - /* Setup the next operands. */ - veclen--; - rd =3D ((rd + delta_d) & (bank_mask - 1)) - | (rd & bank_mask); - - if (op =3D=3D 15) { - /* One source operand. */ - rm =3D ((rm + delta_m) & (bank_mask - 1)) - | (rm & bank_mask); - gen_mov_F0_vreg(dp, rm); - } else { - /* Two source operands. */ - rn =3D ((rn + delta_d) & (bank_mask - 1)) - | (rn & bank_mask); - gen_mov_F0_vreg(dp, rn); - if (delta_m) { - rm =3D ((rm + delta_m) & (bank_mask - 1)) - | (rm & bank_mask); - gen_mov_F1_vreg(dp, rm); - } - } - } - } - break; - case 0xc: - case 0xd: - /* Already handled by decodetree */ - return 1; - default: - /* Should never happen. */ - return 1; - } - return 0; + /* If the decodetree decoder didn't handle this insn, it must be UNDEF= */ + return 1; } =20 static inline bool use_goto_tb(DisasContext *s, target_ulong dest) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index c3223a124ac..ea24365bb4c 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -234,3 +234,9 @@ VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ vd=3D%vd_sp imm=3D%vm_sp opc=3D%vcvt_fix_op VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ vd=3D%vd_dp imm=3D%vm_sp opc=3D%vcvt_fix_op + +# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on = size +VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_dp --=20 2.20.1