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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 35/48] target/arm: Convert VABS to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 167 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 12 ++- target/arm/vfp.decode | 5 + 3 files changed, 180 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a2eeb6cb511..d0282f1f921 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1111,6 +1111,14 @@ typedef void VFPGen3OpSPFn(TCGv_i32 vd, typedef void VFPGen3OpDPFn(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst); =20 +/* + * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp(). + * The callback should emit code to write a value to vd (which + * should be written to only). + */ +typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); +typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); + /* * Perform a 3-operand VFP data processing instruction. fn is the * callback to do the actual operation; this function deals with the @@ -1274,6 +1282,155 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, return true; } =20 +static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int = vm) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i32 f0, fd; + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0x18; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D s->vec_stride + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i32(); + fd =3D tcg_temp_new_i32(); + + neon_load_reg32(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg32(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + if (delta_m =3D=3D 0) { + /* single source one-many */ + while (veclen--) { + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + neon_store_reg32(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg32(f0, vm); + } + + tcg_temp_free_i32(f0); + tcg_temp_free_i32(fd); + + return true; +} + +static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int = vm) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i64 f0, fd; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0xc; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D (s->vec_stride >> 1) + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i64(); + fd =3D tcg_temp_new_i64(); + + neon_load_reg64(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg64(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + if (delta_m =3D=3D 0) { + /* single source one-many */ + while (veclen--) { + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + neon_store_reg64(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg64(f0, vm); + } + + tcg_temp_free_i64(f0); + tcg_temp_free_i64(fd); + + return true; +} + static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fp= st) { /* Note that order of inputs to the add matters for NaNs */ @@ -1731,3 +1888,13 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) tcg_temp_free_i64(fd); return true; } + +static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a) +{ + return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm); +} + +static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) +{ + return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 30d96fbf5a6..010dc32c5f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3096,6 +3096,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) case 0 ... 14: /* Already handled by decodetree */ return 1; + case 15: + switch (rn) { + case 1: + /* Already handled by decodetree */ + return 1; + default: + break; + } default: break; } @@ -3104,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ - case 0x01: /* vabs */ case 0x02: /* vneg */ case 0x03: /* vsqrt */ break; @@ -3284,9 +3291,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 0: /* cpy */ /* no-op */ break; - case 1: /* abs */ - gen_vfp_abs(dp); - break; case 2: /* neg */ gen_vfp_neg(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 1818d4f71e1..7035861c270 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -156,3 +156,8 @@ VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4= l:4 \ vd=3D%vd_sp VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ vd=3D%vd_dp + +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1