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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y6sm2010576wrp.12.2019.06.13.05.15.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 05:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZrHyvKvOWaE4Pp/kVtSvphKsec2oq7Qnq1JNeO01iSY=; b=DBOFN0Yq9c90uggDHRoPGNbmriMw0X6gV3Q3BI++NUUsLF0weDM3cUa/Cf2DzWxpOV jY7Gvga9BsdG78sQMOB72Tclccn/du57tS868vqm+yewl5hO7X0+nYtEgM0da4ceArMP RXVbPmH1w276FlJKXZof1CBBUC70V2ePTv5DwXX7Q+yRo/4P0skZYr+VgYGuHcfVMS2n AcRFwGog5Wvo9Bx9XLYojRTxIw2q589SCZdXCYYE0f3/IqJViBc0qMAYZukaC1LvuNay z5h6hYLBu/73PAV15AlV3X4EfsU5txGk/kE0qt2ejVYOXDrM5PB0feJRG2nXmLmERSC7 o9zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZrHyvKvOWaE4Pp/kVtSvphKsec2oq7Qnq1JNeO01iSY=; b=W+9OrOhI/JfRmRDJ+6KxQU74/XHhx4qvqGJeseXWKWZDnaEtz4VLKXRTMM4JpS3Q7g mE1aaFIa1MYjl6gylcdayFECC8kgsNLAvAo60/uQ2TX6MUFLzwItEg94/DQlax8wo0pt SU98STpkWU/xEywuTUIAefVsBcN1o33zwom/RqhmWwrNZ2x21GP9nGy4mEVa92b68VzP DRloGEO18gO5hkqBtMfZM3bKSf/2WsVNF7Igrq8++CcwesnPZb2bChAocwoSKyzNE+AO tmac0EM+/tTpfwbKLE65lXk1XwvloV49BLBIlHeSgNnsO1ccJ4jYMsXrd7EekMmRdnb4 zTIA== X-Gm-Message-State: APjAAAVn/hEbuBEd/2QFECIGanWuGu+Bz/QBK8v6a4BYkdBqlc/y2adZ AdGlwy5o6eumpUe1EvkpkwdtxqHwKaB8gA== X-Google-Smtp-Source: APXvYqw26ErsPLlw+wexDBM+/w3wwbhk+yXHyo4B0Ra3HATs+R3i8j6bowRV3C3jRWGwuoNMpNl3xw== X-Received: by 2002:adf:f181:: with SMTP id h1mr1582290wro.86.1560428100925; Thu, 13 Jun 2019 05:15:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Jun 2019 13:14:08 +0100 Message-Id: <20190613121433.5246-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190613121433.5246-1-peter.maydell@linaro.org> References: <20190613121433.5246-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 46 +++++++++++++++++++++------------- target/arm/translate.c | 18 ------------- 2 files changed, 28 insertions(+), 36 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 32a1805e582..9729946d734 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -857,7 +857,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_= 64_sp *a) static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) { uint32_t offset; - TCGv_i32 addr; + TCGv_i32 addr, tmp; =20 if (!vfp_access_check(s)) { return true; @@ -876,13 +876,15 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_V= LDR_VSTR_sp *a) addr =3D load_reg(s, a->rn); } tcg_gen_addi_i32(addr, addr, offset); + tmp =3D tcg_temp_new_i32(); if (a->l) { - gen_vfp_ld(s, false, addr); - gen_mov_vreg_F0(false, a->vd); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd); } else { - gen_mov_F0_vreg(false, a->vd); - gen_vfp_st(s, false, addr); + neon_load_reg32(tmp, a->vd); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } + tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); =20 return true; @@ -892,6 +894,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_sp *a) { uint32_t offset; TCGv_i32 addr; + TCGv_i64 tmp; =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { @@ -915,13 +918,15 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_sp *a) addr =3D load_reg(s, a->rn); } tcg_gen_addi_i32(addr, addr, offset); + tmp =3D tcg_temp_new_i64(); if (a->l) { - gen_vfp_ld(s, true, addr); - gen_mov_vreg_F0(true, a->vd); + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd); } else { - gen_mov_F0_vreg(true, a->vd); - gen_vfp_st(s, true, addr); + neon_load_reg64(tmp, a->vd); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } + tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); =20 return true; @@ -930,7 +935,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_sp *a) static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) { uint32_t offset; - TCGv_i32 addr; + TCGv_i32 addr, tmp; int i, n; =20 n =3D a->imm; @@ -976,18 +981,20 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) } =20 offset =3D 4; + tmp =3D tcg_temp_new_i32(); for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_vfp_ld(s, false, addr); - gen_mov_vreg_F0(false, a->vd + i); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd + i); } else { /* store */ - gen_mov_F0_vreg(false, a->vd + i); - gen_vfp_st(s, false, addr); + neon_load_reg32(tmp, a->vd + i); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); } + tcg_temp_free_i32(tmp); if (a->w) { /* writeback */ if (a->p) { @@ -1006,6 +1013,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) { uint32_t offset; TCGv_i32 addr; + TCGv_i64 tmp; int i, n; =20 n =3D a->imm >> 1; @@ -1056,18 +1064,20 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) } =20 offset =3D 8; + tmp =3D tcg_temp_new_i64(); for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_vfp_ld(s, true, addr); - gen_mov_vreg_F0(true, a->vd + i); + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd + i); } else { /* store */ - gen_mov_F0_vreg(true, a->vd + i); - gen_vfp_st(s, true, addr); + neon_load_reg64(tmp, a->vd + i); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); } + tcg_temp_free_i64(tmp); if (a->w) { /* writeback */ if (a->p) { diff --git a/target/arm/translate.c b/target/arm/translate.c index f9b07247b4c..1c5c87d7d01 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1522,24 +1522,6 @@ VFP_GEN_FIX(uhto, ) VFP_GEN_FIX(ulto, ) #undef VFP_GEN_FIX =20 -static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr) -{ - if (dp) { - gen_aa32_ld64(s, cpu_F0d, addr, get_mem_index(s)); - } else { - gen_aa32_ld32u(s, cpu_F0s, addr, get_mem_index(s)); - } -} - -static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr) -{ - if (dp) { - gen_aa32_st64(s, cpu_F0d, addr, get_mem_index(s)); - } else { - gen_aa32_st32(s, cpu_F0s, addr, get_mem_index(s)); - } -} - static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { --=20 2.20.1