From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329586; cv=none; d=zoho.com; s=zohoarc; b=ckc6rq57Fjcjhd5M7xj+S0x7+eAEOs2V8oNF+DxVv8KkErzKTnNNYpcMPv2JBm225cbrF+81kzgnKx6XdqCRFWfS++c3OY6apyFb6reZO9fO9z/x27nxF168/BzfnUVwU34RuJFCVIeRRT2QQenk1AuiRfF6gwgDToTAx0P6tlo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560329586; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=S+75E38INAWB1jPGC52Ts77KsTZ965b3DV0R3efyKy4=; b=AEErb8O5I4eYtIIrj6CG0xj6W5v6zcLzCGZcpWhol4Qj9ihyv4Awpm2EIHp+A/P3jmcuvzqvmnQd/pjswgOK1KmKhUcTGEaZJ94gDCnDCVQWSNsrPW6HDFBOHXKTFdNOUC3nVGTko9B+8QYMwo5EA3I7AovQAVIYaFanU+zemPM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560329586310337.22503298889603; Wed, 12 Jun 2019 01:53:06 -0700 (PDT) Received: from localhost ([::1]:57658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haz0B-0000xu-Mo for importer@patchew.org; Wed, 12 Jun 2019 04:53:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57848) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hayrw-0003Ht-7C for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hayru-0006Lr-Sd for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:32 -0400 Received: from mga11.intel.com ([192.55.52.93]:10702) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hayru-0005vD-JD for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:30 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:28 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:27 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175072" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:40:56 +0800 Message-Id: <20190612084104.34984-2-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 1/9] i386: Add die-level cpu topology to x86CPU on PCMachine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The die-level as the first PC-specific cpu topology is added to the leagcy cpu topology model, which has one die per package implicitly and only the numbers of sockets/cores/threads are configurable. In the new model with die-level support, the total number of logical processors (including offline) on board will be calculated as: #cpus =3D #sockets * #dies * #cores * #threads and considering compatibility, the default value for #dies would be initialized to one in x86_cpu_initfn() and pc_machine_initfn(). Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 9 +++++++-- include/hw/i386/pc.h | 2 ++ target/i386/cpu.c | 1 + target/i386/cpu.h | 2 ++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 12c1e08b85..9e9a42f007 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2308,9 +2308,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, return; } =20 - /* if APIC ID is not set, set it based on socket/core/thread propertie= s */ + /* + * If APIC ID is not set, + * set it based on socket/die/core/thread properties. + */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (ms->smp.max_cpus - 1) / smp_threads / smp_core= s; + int max_socket =3D (ms->smp.max_cpus - 1) / + smp_threads / smp_cores / pcms->smp_dies; =20 if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); @@ -2620,6 +2624,7 @@ static void pc_machine_initfn(Object *obj) pcms->smbus_enabled =3D true; pcms->sata_enabled =3D true; pcms->pit_enabled =3D true; + pcms->smp_dies =3D 1; =20 pc_system_flash_create(pcms); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b260262640..fae9217e34 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -24,6 +24,7 @@ * PCMachineState: * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling * @boot_cpus: number of present VCPUs + * @smp_dies: number of dies per one package */ struct PCMachineState { /*< private >*/ @@ -59,6 +60,7 @@ struct PCMachineState { bool apic_xrupt_override; unsigned apic_id_limit; uint16_t boot_cpus; + unsigned smp_dies; =20 /* NUMA information: */ uint64_t numa_nodes; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 23119699de..a16be205fe 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5619,6 +5619,7 @@ static void x86_cpu_initfn(Object *obj) CPUX86State *env =3D &cpu->env; FeatureWord w; =20 + env->nr_dies =3D 1; cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "family", "int", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index edad6e1efb..5daa2eeafa 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1349,6 +1349,8 @@ typedef struct CPUX86State { uint64_t xss; =20 TPRAccess tpr_access_type; + + unsigned nr_dies; } CPUX86State; =20 struct kvm_msrs; --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329362; cv=none; d=zoho.com; s=zohoarc; b=HSEO5uSD28Jn4zUm9T8J3880QJ4kKQ5xX61dO5JkMixIcBvkhqft/QeipogvvT54pHWYbDhQEYu7D73qwWqZmWuOus6/r6YXm69kHwGXHdxySxg8xafQfB5B+8GRNOun8+ZicRozWYAnYaTH/0tI96TU68dE+Zo1d+w8Gb16+kw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560329362; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 12 Jun 2019 04:44:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hayri-0006DR-Ig for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:22 -0400 Received: from mga11.intel.com ([192.55.52.93]:10704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hayqz-0005vT-K9 for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:18 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:29 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:28 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175079" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:40:57 +0800 Message-Id: <20190612084104.34984-3-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 2/9] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To support multiple dies configuration on PCMachine, the best place to set CPUX86State->nr_dies with requested PCMachineState->smp_dies is in pc_new_cpu() and pc_cpu_pre_plug(). Refactoring pc_new_cpu() is applied and redundant parameter "const char *typename" would be removed. Suggested-by: Eduardo Habkost Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9e9a42f007..af2e95a1b9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1520,12 +1520,16 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, i= nt level) } } =20 -static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) +static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) { Object *cpu =3D NULL; Error *local_err =3D NULL; + CPUX86State *env =3D NULL; =20 - cpu =3D object_new(typename); + cpu =3D object_new(MACHINE(pcms)->cpu_type); + + env =3D &X86_CPU(cpu)->env; + env->nr_dies =3D pcms->smp_dies; =20 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); object_property_set_bool(cpu, true, "realized", &local_err); @@ -1551,7 +1555,7 @@ void pc_hot_add_cpu(MachineState *ms, const int64_t i= d, Error **errp) return; } =20 - pc_new_cpu(ms->cpu_type, apic_id, &local_err); + pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -1576,8 +1580,7 @@ void pc_cpus_init(PCMachineState *pcms) ms->smp.max_cpus - 1)= + 1; possible_cpus =3D mc->possible_cpu_arch_ids(ms); for (i =3D 0; i < ms->smp.cpus; i++) { - pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arc= h_id, - &error_fatal); + pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); } } =20 @@ -2297,6 +2300,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, CPUArchId *cpu_slot; X86CPUTopoInfo topo; X86CPU *cpu =3D X86_CPU(dev); + CPUX86State *env =3D &cpu->env; MachineState *ms =3D MACHINE(hotplug_dev); PCMachineState *pcms =3D PC_MACHINE(hotplug_dev); unsigned int smp_cores =3D ms->smp.cores; @@ -2308,6 +2312,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, return; } =20 + env->nr_dies =3D pcms->smp_dies; + /* * If APIC ID is not set, * set it based on socket/die/core/thread properties. --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 12 Jun 2019 04:44:18 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:30 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:29 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175081" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:40:58 +0800 Message-Id: <20190612084104.34984-4-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 3/9] i386/cpu: Consolidate die-id validity in smp context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The field die_id (default as 0) and has_die_id are introduced to X86CPU. Following the legacy smp check rules, the die_id validity is added to the same contexts as leagcy smp variables such as hmp_hotpluggable_cpus(), machine_set_cpu_numa_node(), cpu_slot_to_string() and pc_cpu_pre_plug(). Acked-by: Dr. David Alan Gilbert Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- hmp.c | 3 +++ hw/core/machine.c | 12 ++++++++++++ hw/i386/pc.c | 14 ++++++++++++++ include/hw/i386/topology.h | 2 ++ qapi/misc.json | 6 ++++-- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 7 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hmp.c b/hmp.c index be5e345c6f..b567c86628 100644 --- a/hmp.c +++ b/hmp.c @@ -3113,6 +3113,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict = *qdict) if (c->has_socket_id) { monitor_printf(mon, " socket-id: \"%" PRIu64 "\"\n", c->soc= ket_id); } + if (c->has_die_id) { + monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id= ); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_= id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index f1a0f45f9c..9eeba448ed 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -679,6 +679,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } =20 + if (props->has_die_id && !slot->props.has_die_id) { + error_setg(errp, "die-id is not supported"); + return; + } + /* skip slots with explicit mismatch */ if (props->has_thread_id && props->thread_id !=3D slot->props.thre= ad_id) { continue; @@ -688,6 +693,10 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } =20 + if (props->has_die_id && props->die_id !=3D slot->props.die_id) { + continue; + } + if (props->has_socket_id && props->socket_id !=3D slot->props.sock= et_id) { continue; } @@ -945,6 +954,9 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) if (cpu->props.has_socket_id) { g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_= id); } + if (cpu->props.has_die_id) { + g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index af2e95a1b9..6e774c6c8e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2329,6 +2329,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, error_setg(errp, "Invalid CPU socket-id: %u must be in range 0= :%u", cpu->socket_id, max_socket); return; + } else if (cpu->die_id > pcms->smp_dies - 1) { + error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u= ", + cpu->die_id, max_socket); + return; } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); @@ -2348,6 +2352,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, } =20 topo.pkg_id =3D cpu->socket_id; + topo.die_id =3D cpu->die_id; topo.core_id =3D cpu->core_id; topo.smt_id =3D cpu->thread_id; cpu->apic_id =3D apicid_from_topo_ids(smp_cores, smp_threads, &top= o); @@ -2385,6 +2390,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, } cpu->socket_id =3D topo.pkg_id; =20 + if (cpu->die_id !=3D -1 && cpu->die_id !=3D topo.die_id) { + error_setg(errp, "property die-id: %u doesn't match set apic-id:" + " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); + return; + } + cpu->die_id =3D topo.die_id; + if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_i= d); @@ -2701,6 +2713,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) ms->smp.cores, ms->smp.threads, &topo); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; + ms->possible_cpus->cpus[i].props.has_die_id =3D true; + ms->possible_cpus->cpus[i].props.die_id =3D topo.die_id; ms->possible_cpus->cpus[i].props.has_core_id =3D true; ms->possible_cpus->cpus[i].props.core_id =3D topo.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 1ebaee0f76..c9fb41588e 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -47,6 +47,7 @@ typedef uint32_t apic_id_t; =20 typedef struct X86CPUTopoInfo { unsigned pkg_id; + unsigned die_id; unsigned core_id; unsigned smt_id; } X86CPUTopoInfo; @@ -130,6 +131,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo->core_id =3D (apicid >> apicid_core_offset(nr_cores, nr_threads))= & ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_thread= s)); topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_cores, nr_threads); + topo->die_id =3D 0; } =20 /* Make APIC ID for the CPU 'cpu_index' diff --git a/qapi/misc.json b/qapi/misc.json index 8b3ca4fdd3..cd236c89b3 100644 --- a/qapi/misc.json +++ b/qapi/misc.json @@ -2924,10 +2924,11 @@ # # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to -# @core-id: core number within socket the CPU belongs to +# @die-id: die number within node/board the CPU belongs to (Since 4.1) +# @core-id: core number within die the CPU belongs to # @thread-id: thread number within core the CPU belongs to # -# Note: currently there are 4 properties that could be present +# Note: currently there are 5 properties that could be present # but management should be prepared to pass through other # properties with device_add command to allow for future # interface extension. This also requires the filed names to be kept in @@ -2938,6 +2939,7 @@ { 'struct': 'CpuInstanceProperties', 'data': { '*node-id': 'int', '*socket-id': 'int', + '*die-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a16be205fe..0fc543096f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5845,11 +5845,13 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5daa2eeafa..69495f0a8a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1475,6 +1475,7 @@ struct X86CPU { =20 int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; + int32_t die_id; int32_t core_id; int32_t thread_id; =20 --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329751; cv=none; d=zoho.com; s=zohoarc; b=FWI/eUacSBzTBmAlKZWhFjUh9OAAJhEU+Vct8P9JjQDV+H11+bmjgvoYME3aBLh208uRjVFIldk5GQ1/W87T8/9NEHmh0njeJtHwIF6P4ek5McNDILyhQWJHexakhyXoj7TD9lEywkUKYUwbLhRhSndkRcauKK/FeXga8YXPlUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560329751; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sQGdNDF9BmCAJugIuOCyNINVQAyiybHl9pW5DcPZmYE=; b=mBnX1yUMjy8bsZ16fphvv67KjTWA0fhfcQNILg8FKew7O+rlTbho5gfqZGnH1wEMJ8SmDvpMCmKDiDN7hJ/rkZpVuIl6SMrcss1PrwzxxNdS9K1OrhsivQHY5aDBdp55TZWHSQnfoZ1LRpO4ckDnCUCET/7zNlXNToH4flU8tgg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560329751738923.1209560265245; Wed, 12 Jun 2019 01:55:51 -0700 (PDT) Received: from localhost ([::1]:57684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haz2n-0003pn-Nm for importer@patchew.org; Wed, 12 Jun 2019 04:55:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57792) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hayrp-00038i-Rf for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hayri-0006EF-T0 for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:25 -0400 Received: from mga11.intel.com ([192.55.52.93]:10704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hayri-0005vT-KF for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:18 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:31 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:30 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175085" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:40:59 +0800 Message-Id: <20190612084104.34984-5-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 4/9] i386: Update new x86_apicid parsing rules with die_offset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In new sockets/dies/cores/threads model, the apicid of logical cpu could imply die level info of guest cpu topology thus x86_apicid_from_cpu_idx() need to be refactored with #dies value, so does apicid_*_offset(). To keep semantic compatibility, the legacy pkg_offset which helps to generate CPUIDs such as 0x3 for L3 cache should be mapping to die_offset. Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 29 ++++++++++----- include/hw/i386/topology.h | 76 +++++++++++++++++++++++++++----------- target/i386/cpu.c | 13 ++++--- 3 files changed, 81 insertions(+), 37 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6e774c6c8e..b4dbd1064d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -933,10 +933,11 @@ void enable_compat_apic_id_mode(void) static uint32_t x86_cpu_apic_id_from_index(MachineState *ms, unsigned int cpu_index) { + PCMachineState *pcms =3D PC_MACHINE(ms); uint32_t correct_id; static bool warned; =20 - correct_id =3D x86_apicid_from_cpu_idx(ms->smp.cores, + correct_id =3D x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, ms->smp.threads, cpu_index); if (compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { @@ -2355,18 +2356,21 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, topo.die_id =3D cpu->die_id; topo.core_id =3D cpu->core_id; topo.smt_id =3D cpu->thread_id; - cpu->apic_id =3D apicid_from_topo_ids(smp_cores, smp_threads, &top= o); + cpu->apic_id =3D apicid_from_topo_ids(pcms->smp_dies, smp_cores, + smp_threads, &topo); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &to= po); - error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] w= ith" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, - ms->possible_cpus->len - 1); + x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, + smp_cores, smp_threads, &topo); + error_setg(errp, + "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" + " APIC ID %" PRIu32 ", valid index range 0:%d", + topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + cpu->apic_id, ms->possible_cpus->len - 1); return; } =20 @@ -2382,7 +2386,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); + x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, + smp_cores, smp_threads, &topo); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pk= g_id); @@ -2679,10 +2684,12 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cp= u_index) static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { X86CPUTopoInfo topo; + PCMachineState *pcms =3D PC_MACHINE(ms); =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - ms->smp.cores, ms->smp.threads, &topo); + pcms->smp_dies, ms->smp.cores, + ms->smp.threads, &topo); return topo.pkg_id % nb_numa_nodes; } =20 @@ -2690,6 +2697,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) { int i; unsigned int max_cpus =3D ms->smp.max_cpus; + PCMachineState *pcms =3D PC_MACHINE(ms); =20 if (ms->possible_cpus) { /* @@ -2710,7 +2718,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(= MachineState *ms) ms->possible_cpus->cpus[i].vcpus_count =3D 1; ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= ms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - ms->smp.cores, ms->smp.threads, &topo); + pcms->smp_dies, ms->smp.cores, + ms->smp.threads, &topo); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; ms->possible_cpus->cpus[i].props.has_die_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index c9fb41588e..4ff5b2da6c 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -63,88 +63,120 @@ static unsigned apicid_bitwidth_for_count(unsigned cou= nt) =20 /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_cores, unsigned nr_thr= eads) +static inline unsigned apicid_smt_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_threads); } =20 /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_core_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { return apicid_bitwidth_for_count(nr_cores); } =20 +/* Bit width of the Die_ID field */ +static inline unsigned apicid_die_width(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_bitwidth_for_count(nr_dies); +} + /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_cores, +static inline unsigned apicid_core_offset(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads) { - return apicid_smt_width(nr_cores, nr_threads); + return apicid_smt_width(nr_dies, nr_cores, nr_threads); +} + +/* Bit offset of the Die_ID field */ +static inline unsigned apicid_die_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) +{ + return apicid_core_offset(nr_dies, nr_cores, nr_threads) + + apicid_core_width(nr_dies, nr_cores, nr_threads); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_th= reads) +static inline unsigned apicid_pkg_offset(unsigned nr_dies, + unsigned nr_cores, + unsigned nr_threads) { - return apicid_core_offset(nr_cores, nr_threads) + - apicid_core_width(nr_cores, nr_threads); + return apicid_die_offset(nr_dies, nr_cores, nr_threads) + + apicid_die_width(nr_dies, nr_cores, nr_threads); } =20 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores, +static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, const X86CPUTopoInfo *topo) { - return (topo->pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) | - (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) | + return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threa= ds)) | + (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threa= ds)) | topo->smt_id; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_cores, +static inline void x86_topo_ids_from_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, X86CPUTopoInfo *topo) { - unsigned core_index =3D cpu_index / nr_threads; + topo->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo->core_id =3D cpu_index / nr_threads % nr_cores; topo->smt_id =3D cpu_index % nr_threads; - topo->core_id =3D core_index % nr_cores; - topo->pkg_id =3D core_index / nr_cores; } =20 /* Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, + unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, X86CPUTopoInfo *topo) { topo->smt_id =3D apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_cores, nr_threads= )); - topo->core_id =3D (apicid >> apicid_core_offset(nr_cores, nr_threads))= & - ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_thread= s)); - topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_cores, nr_threads); - topo->die_id =3D 0; + ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); + topo->core_id =3D + (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_thre= ads)); + topo->die_id =3D + (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & + ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threa= ds)); + topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_thr= eads); } =20 /* Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores, +static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, + unsigned nr_cores, unsigned nr_threads, unsigned cpu_index) { X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_cores, nr_threads, &topo); + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); } =20 #endif /* HW_I386_TOPOLOGY_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0fc543096f..09e20a2c3b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4245,7 +4245,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t pkg_offset; + uint32_t die_offset; uint32_t limit; uint32_t signature[3]; =20 @@ -4334,10 +4334,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - pkg_offset =3D apicid_pkg_offset(cs->nr_cores, cs->nr_thre= ads); + die_offset =3D apicid_die_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << pkg_offset), cs->nr_cores, + (1 << die_offset), cs->nr_cores, eax, ebx, ecx, edx); break; } @@ -4419,12 +4420,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: - *eax =3D apicid_core_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_core_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(cs->nr_cores, cs->nr_threads); + *eax =3D apicid_pkg_offset(env->nr_dies, + cs->nr_cores, cs->nr_threads); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329569; cv=none; d=zoho.com; s=zohoarc; b=mB2+YDxgSYeDq563niCOhx/ilWACEWmTKYo6q0SfPOu1UtGR2HWw+dlnBVQocfbUC59fupwzvmspEfYNN6pEf6cawk+pBDhQFgSc/QsvRvxVhdj2ciGNuJVO5kK+IelxLeDUfiI5/DdHICWHRj/H95uBzlWPdgNUJFv0YXXJ7sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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d="scan'208";a="184175087" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:41:00 +0800 Message-Id: <20190612084104.34984-6-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 5/9] tests/x86-cpuid: Update testcases in test_topo_bits() with multiple dies X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The corresponding topo_bits tests are updated to support die configurations. Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- tests/test-x86-cpuid.c | 84 ++++++++++++++++++++++-------------------- 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c index ff225006e4..1942287f33 100644 --- a/tests/test-x86-cpuid.c +++ b/tests/test-x86-cpuid.c @@ -28,74 +28,80 @@ =20 static void test_topo_bits(void) { - /* simple tests for 1 thread per core, 1 core per socket */ - g_assert_cmpuint(apicid_smt_width(1, 1), =3D=3D, 0); - g_assert_cmpuint(apicid_core_width(1, 1), =3D=3D, 0); + /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ + g_assert_cmpuint(apicid_smt_width(1, 1, 1), =3D=3D, 0); + g_assert_cmpuint(apicid_core_width(1, 1, 1), =3D=3D, 0); + g_assert_cmpuint(apicid_die_width(1, 1, 1), =3D=3D, 0); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 2), =3D=3D, 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 3), =3D=3D, 3); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), =3D=3D, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), =3D=3D, 3); =20 =20 /* Test field width calculation for multiple values */ - g_assert_cmpuint(apicid_smt_width(1, 2), =3D=3D, 1); - g_assert_cmpuint(apicid_smt_width(1, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_smt_width(1, 4), =3D=3D, 2); + g_assert_cmpuint(apicid_smt_width(1, 1, 2), =3D=3D, 1); + g_assert_cmpuint(apicid_smt_width(1, 1, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_smt_width(1, 1, 4), =3D=3D, 2); =20 - g_assert_cmpuint(apicid_smt_width(1, 14), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 15), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 16), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 17), =3D=3D, 5); + g_assert_cmpuint(apicid_smt_width(1, 1, 14), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 15), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 16), =3D=3D, 4); + g_assert_cmpuint(apicid_smt_width(1, 1, 17), =3D=3D, 5); =20 =20 - g_assert_cmpuint(apicid_core_width(30, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(31, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(32, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(33, 2), =3D=3D, 6); + g_assert_cmpuint(apicid_core_width(1, 30, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 31, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 32, 2), =3D=3D, 5); + g_assert_cmpuint(apicid_core_width(1, 33, 2), =3D=3D, 6); =20 + g_assert_cmpuint(apicid_die_width(1, 30, 2), =3D=3D, 0); + g_assert_cmpuint(apicid_die_width(2, 30, 2), =3D=3D, 1); + g_assert_cmpuint(apicid_die_width(3, 30, 2), =3D=3D, 2); + g_assert_cmpuint(apicid_die_width(4, 30, 2), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly */ =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - g_assert_cmpuint(apicid_smt_width(6, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_core_width(6, 3), =3D=3D, 3); - g_assert_cmpuint(apicid_pkg_offset(6, 3), =3D=3D, 5); + g_assert_cmpuint(apicid_smt_width(1, 6, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_core_offset(1, 6, 3), =3D=3D, 2); + g_assert_cmpuint(apicid_die_offset(1, 6, 3), =3D=3D, 5); + g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), =3D=3D, 5); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2), =3D=3D, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), =3D=3D, 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), =3D=3D, (1 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), =3D=3D, (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), =3D=3D, (1 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), =3D=3D, (2 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), =3D=3D, (2 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), =3D=3D, (2 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), =3D=3D, (5 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), =3D=3D, (5 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), =3D=3D, (5 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 0 * 3 + 0),= =3D=3D, - (1 << 5)); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 1 * 3 + 1),= =3D=3D, - (1 << 5) | (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 3 * 6 * 3 + 5 * 3 + 2),= =3D=3D, - (3 << 5) | (5 << 2) | 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 1 * 6 * 3 + 0 * 3 + 0), =3D=3D, (1 << 5)); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 1 * 6 * 3 + 1 * 3 + 1), =3D=3D, (1 << 5) | (1 << 2) |= 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + 3 * 6 * 3 + 5 * 3 + 2), =3D=3D, (3 << 5) | (5 << 2) |= 2); } =20 int main(int argc, char **argv) --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 12 Jun 2019 04:44:19 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:33 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:32 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175089" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:41:01 +0800 Message-Id: <20190612084104.34984-7-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 6/9] i386/cpu: Add CPUID.1F generation support for multi-dies PCMachine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be exposed if guests want to emulate multiple software-visible die within each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they can be generated by almost same code as 0xb except die_offset setting. If the number of dies per package is less than 2, the qemu will not expose CPUID.1F regardless of whether the host supports CPUID.1F. Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 4 ++++ target/i386/kvm.c | 12 ++++++++++++ 3 files changed, 53 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 09e20a2c3b..127aff74a6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4437,6 +4437,42 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; } =20 + assert(!(*eax & ~0x1f)); + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ + break; + case 0x1F: + /* V2 Extended Topology Enumeration Leaf */ + if (env->nr_dies < 2 || !cpu->enable_cpuid_0x1f) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + *ecx =3D count & 0xff; + *edx =3D cpu->apic_id; + switch (count) { + case 0: + *eax =3D apicid_core_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; + break; + case 1: + *eax =3D apicid_die_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; + break; + case 2: + *eax =3D apicid_pkg_offset(env->nr_dies, cs->nr_cores, + cs->nr_threads); + *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; + break; + default: + *eax =3D 0; + *ebx =3D 0; + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; + } assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; @@ -5890,6 +5926,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), + DEFINE_PROP_BOOL("cpuid-0x1f", X86CPU, enable_cpuid_0x1f, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 69495f0a8a..0434dfb62a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -726,6 +726,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) +#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) =20 /* MSR Feature Bits */ #define MSR_ARCH_CAP_RDCL_NO (1U << 0) @@ -1444,6 +1445,9 @@ struct X86CPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; =20 + /* V2 Compatibility bits for old machine types: */ + bool enable_cpuid_0x1f; + /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 3b29ce5c0d..9b4da9b265 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1081,6 +1081,10 @@ int kvm_arch_init_vcpu(CPUState *cs) } break; } + case 0x1f: + if (env->nr_dies < 2 || !cpu->enable_cpuid_0x1f) { + break; + } case 4: case 0xb: case 0xd: @@ -1088,6 +1092,11 @@ int kvm_arch_init_vcpu(CPUState *cs) if (i =3D=3D 0xd && j =3D=3D 64) { break; } + + if (i =3D=3D 0x1f && j =3D=3D 64) { + break; + } + c->function =3D i; c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; c->index =3D j; @@ -1099,6 +1108,9 @@ int kvm_arch_init_vcpu(CPUState *cs) if (i =3D=3D 0xb && !(c->ecx & 0xff00)) { break; } + if (i =3D=3D 0x1f && !(c->ecx & 0xff00)) { + break; + } if (i =3D=3D 0xd && c->eax =3D=3D 0) { continue; } --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329356; cv=none; d=zoho.com; s=zohoarc; b=gCZRrLKjL9X1/bz/zJmMwdOViOIbKhlepaQB1i5PvVifptSbpltyrLOpSsSrfDScjCzg78l+47ZVGmKsKYUPINi25DBmY000PSEwFbz7w8vjlhpoAohyKdNCgXbnGiy05cHWxGE9dEsyVBeDRXJ7S3yFvpWy/WIyRh1YJDdjHJY= ARC-Message-Signature: i=1; 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Wed, 12 Jun 2019 04:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57729) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hayrm-00038R-UM for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hayrk-0006G1-24 for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:22 -0400 Received: from mga11.intel.com ([192.55.52.93]:10704) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hayrj-0005vT-MS for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:19 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:34 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175091" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:41:02 +0800 Message-Id: <20190612084104.34984-8-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 7/9] target/i386: Support multi-dies when host doesn't support CPUID.1F X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In guest CPUID generation process, the cpuid_min_level would be adjusted to the maximum passed value for basic CPUID configuration and it should not be restricted by the limited value returned from cpu_x86_cpuid(). After the ba= sic cpu_x86_cpuid() loop is finished, the cpuid_0_entry.eax needs to be configu= red again by the last adjusted cpuid_min_level value. If a user wants to expose CPUID.1F by passing dies > 1 for any reason witho= ut host support, a per-cpu smp topology warning will appear but it's not block= ed. Signed-off-by: Like Xu --- target/i386/kvm.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9b4da9b265..8bf1604d2b 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -931,12 +931,12 @@ int kvm_arch_init_vcpu(CPUState *cs) struct kvm_cpuid_entry2 *c; uint32_t signature[3]; int kvm_base =3D KVM_CPUID_SIGNATURE; - int r; + int r, cpuid_0_entry, cpuid_min_level; Error *local_err =3D NULL; =20 memset(&cpuid_data, 0, sizeof(cpuid_data)); =20 - cpuid_i =3D 0; + cpuid_i =3D cpuid_0_entry =3D cpuid_min_level =3D 0; =20 r =3D kvm_arch_set_tsc_khz(cs); if (r < 0) { @@ -1050,6 +1050,12 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); =20 + /* Allow 0x1f setting regardless of kvm support if nr_dies > 1 */ + if (limit < 0x1f && env->nr_dies > 1 && cpu->enable_cpuid_0x1f) { + limit =3D env->cpuid_level =3D env->cpuid_min_level =3D 0x1f; + warn_report("CPU topology: the CPUID.1F isn't supported on the hos= t."); + } + for (i =3D 0; i <=3D limit; i++) { if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { fprintf(stderr, "unsupported level value: 0x%x\n", limit); @@ -1151,8 +1157,22 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); break; } + + /* Remember the index of cpuid.0 leaf for reconfiguration. */ + cpuid_0_entry =3D (i =3D=3D 0) ? (cpuid_i - 1) : cpuid_0_entry; + + /* Adjust cpuid_min_level to the maximum index of valid basic cpui= ds. */ + cpuid_min_level =3D + ((c->eax | c->ebx | c->ecx | c->edx | c->flags | c->index)= && + (i > cpuid_min_level)) ? i : cpuid_min_lev= el; } =20 + env->cpuid_level =3D env->cpuid_min_level =3D cpuid_min_level; + + /* Reconfigure cpuid_0_eax value to follow CPUID.0 instruction spec.*/ + c =3D &cpuid_data.entries[cpuid_0_entry]; + cpu_x86_cpuid(env, 0, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + if (limit >=3D 0x0a) { uint32_t eax, edx; =20 --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560329387; cv=none; d=zoho.com; s=zohoarc; b=ff8wXkmgkg3ZrQAXV3Ry00bWoIOQIHL8lP6bdhZdXAKYjz4sXmAoR4bsFikeIKZoOSR/ljU98pFaYcjtN28Ov4VS1qNZZPewxm4CynxhI1lnGcAcJuF8m1z7COHdVVVR8kNKdIMkocO352XGGoOf89FGOlAMKn2AbUW7rJILnds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560329387; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nQJX8PXqgmGclSLR5PhhXtmJ5x4t/78/JcxVDZR3yvY=; b=UZ6CvYk174AaZxXThqaWRoAvg7o42XpsWJFimJr7KPUe7R1nd8eZyXJgmeUrIBSU7xgRL0umD7mzhVgkURlOO528i9UnZaxmPPAgHU8j0rJut1VLcXixcDQyvOwNPpprZ+qzoMuxovBa36twVyPg6/uQ5Rx4Sx8ZwHK+2YzkyOE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560329387208338.75757305084585; Wed, 12 Jun 2019 01:49:47 -0700 (PDT) Received: from localhost ([::1]:57634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haywy-0005b4-3V for importer@patchew.org; Wed, 12 Jun 2019 04:49:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57801) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hayrq-00039n-GX for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hayrk-0006G7-4n for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:26 -0400 Received: from mga11.intel.com ([192.55.52.93]:10698) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hayrj-0005un-PA for qemu-devel@nongnu.org; Wed, 12 Jun 2019 04:44:20 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:37 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:34 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175093" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:41:03 +0800 Message-Id: <20190612084104.34984-9-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Subject: [Qemu-devel] [PATCH v3 8/9] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" To make smp_parse() more flexible and expansive, a smp_parse function pointer is added to MachineClass that machine types could override. The generic smp_parse() code in vl.c is moved to hw/core/machine.c, and become the default implementation of MachineClass::smp_parse. A PC-specific function called pc_smp_parse() has been added to hw/i386/pc.c, which in this patch changes nothing against the default one . Suggested-by: Eduardo Habkost Signed-off-by: Like Xu Reviewed-by: Eduardo Habkost --- hw/core/machine.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ hw/i386/pc.c | 76 +++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 5 +++ include/hw/i386/pc.h | 1 + vl.c | 75 ++---------------------------------------- 5 files changed, 161 insertions(+), 73 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 9eeba448ed..d58a684abf 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -11,6 +11,9 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/option.h" +#include "qapi/qmp/qerror.h" +#include "sysemu/replay.h" #include "qemu/units.h" #include "hw/boards.h" #include "qapi/error.h" @@ -722,6 +725,79 @@ void machine_set_cpu_numa_node(MachineState *machine, } } =20 +static void smp_parse(MachineState *ms, QemuOpts *opts) +{ + /* copy it from legacy smp_parse() in vl.c */ + if (opts) { + unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); + unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); + unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); + unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); + + /* compute missing values, prefer sockets over cores over threads = */ + if (cpus =3D=3D 0 || sockets =3D=3D 0) { + cores =3D cores > 0 ? cores : 1; + threads =3D threads > 0 ? threads : 1; + if (cpus =3D=3D 0) { + sockets =3D sockets > 0 ? sockets : 1; + cpus =3D cores * threads * sockets; + } else { + ms->smp.max_cpus =3D + qemu_opt_get_number(opts, "maxcpus", cpus); + sockets =3D ms->smp.max_cpus / (cores * threads); + } + } else if (cores =3D=3D 0) { + threads =3D threads > 0 ? threads : 1; + cores =3D cpus / (sockets * threads); + cores =3D cores > 0 ? cores : 1; + } else if (threads =3D=3D 0) { + threads =3D cpus / (cores * sockets); + threads =3D threads > 0 ? threads : 1; + } else if (sockets * cores * threads < cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) < " + "smp_cpus (%u)", + sockets, cores, threads, cpus); + exit(1); + } + + ms->smp.max_cpus =3D + qemu_opt_get_number(opts, "maxcpus", cpus); + + if (ms->smp.max_cpus < cpus) { + error_report("maxcpus must be equal to or greater than smp"); + exit(1); + } + + if (sockets * cores * threads > ms->smp.max_cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) > " + "maxcpus (%u)", + sockets, cores, threads, + ms->smp.max_cpus); + exit(1); + } + + if (sockets * cores * threads !=3D ms->smp.max_cpus) { + warn_report("Invalid CPU topology deprecated: " + "sockets (%u) * cores (%u) * threads (%u) " + "!=3D maxcpus (%u)", + sockets, cores, threads, + ms->smp.max_cpus); + } + + ms->smp.cpus =3D cpus; + ms->smp.cores =3D cores; + ms->smp.threads =3D threads; + } + + if (ms->smp.cpus > 1) { + Error *blocker =3D NULL; + error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); + replay_add_blocker(blocker); + } +} + static void machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -729,6 +805,7 @@ static void machine_class_init(ObjectClass *oc, void *d= ata) /* Default 128 MB as guest ram size */ mc->default_ram_size =3D 128 * MiB; mc->rom_file_has_mr =3D true; + mc->smp_parse =3D smp_parse; =20 /* numa node memory size aligned on 8MB by default. * On Linux, each node's border has to be 8MB aligned diff --git a/hw/i386/pc.c b/hw/i386/pc.c index b4dbd1064d..63b44bd2bd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -78,6 +78,8 @@ #include "hw/i386/intel_iommu.h" #include "hw/net/ne2000-isa.h" #include "standard-headers/asm-x86/bootparam.h" +#include "sysemu/replay.h" +#include "qapi/qmp/qerror.h" =20 /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -1539,6 +1541,79 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t= apic_id, Error **errp) error_propagate(errp, local_err); } =20 +void pc_smp_parse(MachineState *ms, QemuOpts *opts) +{ + /* copy it from legacy smp_parse() in vl.c */ + if (opts) { + unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); + unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); + unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); + unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); + + /* compute missing values, prefer sockets over cores over threads = */ + if (cpus =3D=3D 0 || sockets =3D=3D 0) { + cores =3D cores > 0 ? cores : 1; + threads =3D threads > 0 ? threads : 1; + if (cpus =3D=3D 0) { + sockets =3D sockets > 0 ? sockets : 1; + cpus =3D cores * threads * sockets; + } else { + ms->smp.max_cpus =3D + qemu_opt_get_number(opts, "maxcpus", cpus); + sockets =3D ms->smp.max_cpus / (cores * threads); + } + } else if (cores =3D=3D 0) { + threads =3D threads > 0 ? threads : 1; + cores =3D cpus / (sockets * threads); + cores =3D cores > 0 ? cores : 1; + } else if (threads =3D=3D 0) { + threads =3D cpus / (cores * sockets); + threads =3D threads > 0 ? threads : 1; + } else if (sockets * cores * threads < cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) < " + "smp_cpus (%u)", + sockets, cores, threads, cpus); + exit(1); + } + + ms->smp.max_cpus =3D + qemu_opt_get_number(opts, "maxcpus", cpus); + + if (ms->smp.max_cpus < cpus) { + error_report("maxcpus must be equal to or greater than smp"); + exit(1); + } + + if (sockets * cores * threads > ms->smp.max_cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) > " + "maxcpus (%u)", + sockets, cores, threads, + ms->smp.max_cpus); + exit(1); + } + + if (sockets * cores * threads !=3D ms->smp.max_cpus) { + warn_report("Invalid CPU topology deprecated: " + "sockets (%u) * cores (%u) * threads (%u) " + "!=3D maxcpus (%u)", + sockets, cores, threads, + ms->smp.max_cpus); + } + + ms->smp.cpus =3D cpus; + ms->smp.cores =3D cores; + ms->smp.threads =3D threads; + } + + if (ms->smp.cpus > 1) { + Error *blocker =3D NULL; + error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); + replay_add_blocker(blocker); + } +} + void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) { int64_t apic_id =3D x86_cpu_apic_id_from_index(ms, id); @@ -2779,6 +2854,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->has_hotpluggable_cpus =3D true; mc->default_boot_order =3D "cad"; mc->hot_add_cpu =3D pc_hot_add_cpu; + mc->smp_parse =3D pc_smp_parse; mc->block_default_type =3D IF_IDE; mc->max_cpus =3D 255; mc->reset =3D pc_machine_reset; diff --git a/include/hw/boards.h b/include/hw/boards.h index 1e000229e1..c025f33407 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -158,6 +158,10 @@ typedef struct { * @kvm_type: * Return the type of KVM corresponding to the kvm-type string option or * computed based on other criteria such as the host kernel capabilitie= s. + * @smp_parse: + * The function pointer to hook different machine specific functions for + * parsing "smp-opts" from QemuOpts to MachineState::CpuTopology and mo= re + * machine specific topology fields, such as smp_dies for PCMachine. */ struct MachineClass { /*< private >*/ @@ -174,6 +178,7 @@ struct MachineClass { void (*reset)(MachineState *state); void (*hot_add_cpu)(MachineState *state, const int64_t id, Error **err= p); int (*kvm_type)(MachineState *machine, const char *arg); + void (*smp_parse)(MachineState *ms, QemuOpts *opts); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index fae9217e34..7ca24746cc 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -189,6 +189,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int l= evel); =20 void pc_cpus_init(PCMachineState *pcms); void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); +void pc_smp_parse(MachineState *ms, QemuOpts *opts); =20 void pc_guest_info_init(PCMachineState *pcms); =20 diff --git a/vl.c b/vl.c index 0760b2724e..53ea9b6d6f 100644 --- a/vl.c +++ b/vl.c @@ -1245,78 +1245,6 @@ static QemuOptsList qemu_smp_opts =3D { }, }; =20 -static void smp_parse(QemuOpts *opts) -{ - if (opts) { - unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); - unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); - unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); - unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); - - /* compute missing values, prefer sockets over cores over threads = */ - if (cpus =3D=3D 0 || sockets =3D=3D 0) { - cores =3D cores > 0 ? cores : 1; - threads =3D threads > 0 ? threads : 1; - if (cpus =3D=3D 0) { - sockets =3D sockets > 0 ? sockets : 1; - cpus =3D cores * threads * sockets; - } else { - current_machine->smp.max_cpus =3D - qemu_opt_get_number(opts, "maxcpus", cpus); - sockets =3D current_machine->smp.max_cpus / (cores * threa= ds); - } - } else if (cores =3D=3D 0) { - threads =3D threads > 0 ? threads : 1; - cores =3D cpus / (sockets * threads); - cores =3D cores > 0 ? cores : 1; - } else if (threads =3D=3D 0) { - threads =3D cpus / (cores * sockets); - threads =3D threads > 0 ? threads : 1; - } else if (sockets * cores * threads < cpus) { - error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) < " - "smp_cpus (%u)", - sockets, cores, threads, cpus); - exit(1); - } - - current_machine->smp.max_cpus =3D - qemu_opt_get_number(opts, "maxcpus", cpus); - - if (current_machine->smp.max_cpus < cpus) { - error_report("maxcpus must be equal to or greater than smp"); - exit(1); - } - - if (sockets * cores * threads > current_machine->smp.max_cpus) { - error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) > " - "maxcpus (%u)", - sockets, cores, threads, - current_machine->smp.max_cpus); - exit(1); - } - - if (sockets * cores * threads !=3D current_machine->smp.max_cpus) { - warn_report("Invalid CPU topology deprecated: " - "sockets (%u) * cores (%u) * threads (%u) " - "!=3D maxcpus (%u)", - sockets, cores, threads, - current_machine->smp.max_cpus); - } - - current_machine->smp.cpus =3D cpus; - current_machine->smp.cores =3D cores; - current_machine->smp.threads =3D threads; - } - - if (current_machine->smp.cpus > 1) { - Error *blocker =3D NULL; - error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); - replay_add_blocker(blocker); - } -} - static void realtime_init(void) { if (enable_mlock) { @@ -4043,7 +3971,8 @@ int main(int argc, char **argv, char **envp) current_machine->smp.cores =3D 1; current_machine->smp.threads =3D 1; =20 - smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); + machine_class->smp_parse(current_machine, + qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); =20 /* sanity-check smp_cpus and max_cpus against machine_class */ if (current_machine->smp.cpus < machine_class->min_cpus) { --=20 2.21.0 From nobody Fri Apr 19 20:16:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 12 Jun 2019 04:44:18 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2019 01:43:37 -0700 Received: from likexu-e5-2699-v4.sh.intel.com ([10.239.48.178]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2019 01:43:35 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,363,1557212400"; d="scan'208";a="184175095" From: Like Xu To: qemu-devel@nongnu.org, Eduardo Habkost Date: Wed, 12 Jun 2019 16:41:04 +0800 Message-Id: <20190612084104.34984-10-like.xu@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612084104.34984-1-like.xu@linux.intel.com> References: <20190612084104.34984-1-like.xu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Subject: [Qemu-devel] [PATCH v3 9/9] vl.c: Add -smp, dies=* command line support and update doc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr . David Alan Gilbert" , like.xu@linux.intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" For PC target, users could configure the number of dies per one package via command line with this patch, such as "-smp dies=3D2,cores=3D4". The parsing rules of new cpu-topology model obey the same restrictions/logic as the legacy socket/core/thread model especially on missing values computi= ng. Signed-off-by: Like Xu --- hw/i386/pc.c | 32 ++++++++++++++++++-------------- qemu-options.hx | 17 +++++++++-------- vl.c | 3 +++ 3 files changed, 30 insertions(+), 22 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 63b44bd2bd..8a5da4f0c1 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1543,10 +1543,13 @@ static void pc_new_cpu(PCMachineState *pcms, int64_= t apic_id, Error **errp) =20 void pc_smp_parse(MachineState *ms, QemuOpts *opts) { - /* copy it from legacy smp_parse() in vl.c */ + PCMachineState *pcms =3D (PCMachineState *) + object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE); + if (opts) { unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); + unsigned dies =3D qemu_opt_get_number(opts, "dies", 1); unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); =20 @@ -1556,24 +1559,24 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) threads =3D threads > 0 ? threads : 1; if (cpus =3D=3D 0) { sockets =3D sockets > 0 ? sockets : 1; - cpus =3D cores * threads * sockets; + cpus =3D cores * threads * dies * sockets; } else { ms->smp.max_cpus =3D qemu_opt_get_number(opts, "maxcpus", cpus); - sockets =3D ms->smp.max_cpus / (cores * threads); + sockets =3D ms->smp.max_cpus / (cores * threads * dies); } } else if (cores =3D=3D 0) { threads =3D threads > 0 ? threads : 1; - cores =3D cpus / (sockets * threads); + cores =3D cpus / (sockets * dies * threads); cores =3D cores > 0 ? cores : 1; } else if (threads =3D=3D 0) { - threads =3D cpus / (cores * sockets); + threads =3D cpus / (cores * dies * sockets); threads =3D threads > 0 ? threads : 1; - } else if (sockets * cores * threads < cpus) { + } else if (sockets * dies * cores * threads < cpus) { error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) < " + "sockets (%u) * dies (%u) * cores (%u) * threads = (%u) < " "smp_cpus (%u)", - sockets, cores, threads, cpus); + sockets, dies, cores, threads, cpus); exit(1); } =20 @@ -1585,26 +1588,27 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) exit(1); } =20 - if (sockets * cores * threads > ms->smp.max_cpus) { + if (sockets * dies * cores * threads > ms->smp.max_cpus) { error_report("cpu topology: " - "sockets (%u) * cores (%u) * threads (%u) > " + "sockets (%u) * dies (%u) * cores (%u) * threads = (%u) > " "maxcpus (%u)", - sockets, cores, threads, + sockets, dies, cores, threads, ms->smp.max_cpus); exit(1); } =20 - if (sockets * cores * threads !=3D ms->smp.max_cpus) { + if (sockets * dies * cores * threads !=3D ms->smp.max_cpus) { warn_report("Invalid CPU topology deprecated: " - "sockets (%u) * cores (%u) * threads (%u) " + "sockets (%u) * dies (%u) * cores (%u) * threads (= %u) " "!=3D maxcpus (%u)", - sockets, cores, threads, + sockets, dies, cores, threads, ms->smp.max_cpus); } =20 ms->smp.cpus =3D cpus; ms->smp.cores =3D cores; ms->smp.threads =3D threads; + pcms->smp_dies =3D dies; } =20 if (ms->smp.cpus > 1) { diff --git a/qemu-options.hx b/qemu-options.hx index 0d8beb4afd..a5b314a448 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -138,25 +138,26 @@ no incompatible TCG features have been enabled (e.g. = icount/replay). ETEXI =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, - "-smp [cpus=3D]n[,maxcpus=3Dcpus][,cores=3Dcores][,threads=3Dthreads][= ,sockets=3Dsockets]\n" + "-smp [cpus=3D]n[,maxcpus=3Dcpus][,cores=3Dcores][,threads=3Dthreads][= ,dies=3Ddies][,sockets=3Dsockets]\n" " set the number of CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total cpus, including\n" " offline CPUs for hotplug, etc\n" - " cores=3D number of CPU cores on one socket\n" + " cores=3D number of CPU cores on one socket (for PC, i= t's on one die)\n" " threads=3D number of threads on one CPU core\n" + " dies=3D number of CPU dies on one socket (for PC only= )\n" " sockets=3D number of discrete sockets in the system\n= ", QEMU_ARCH_ALL) STEXI -@item -smp [cpus=3D]@var{n}[,cores=3D@var{cores}][,threads=3D@var{threads}= ][,sockets=3D@var{sockets}][,maxcpus=3D@var{maxcpus}] +@item -smp [cpus=3D]@var{n}[,cores=3D@var{cores}][,threads=3D@var{threads}= ][,dies=3Ddies][,sockets=3D@var{sockets}][,maxcpus=3D@var{maxcpus}] @findex -smp Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255 CPUs are supported. On Sparc32 target, Linux limits the number of usable C= PUs to 4. -For the PC target, the number of @var{cores} per socket, the number -of @var{threads} per cores and the total number of @var{sockets} can be -specified. Missing values will be computed. If any on the three values is -given, the total number of CPUs @var{n} can be omitted. @var{maxcpus} -specifies the maximum number of hotpluggable CPUs. +For the PC target, the number of @var{cores} per die, the number of @var{t= hreads} +per cores, the number of @var{dies} per packages and the total number of +@var{sockets} can be specified. Missing values will be computed. +If any on the three values is given, the total number of CPUs @var{n} can = be omitted. +@var{maxcpus} specifies the maximum number of hotpluggable CPUs. ETEXI =20 DEF("numa", HAS_ARG, QEMU_OPTION_numa, diff --git a/vl.c b/vl.c index 53ea9b6d6f..c6d1339442 100644 --- a/vl.c +++ b/vl.c @@ -1231,6 +1231,9 @@ static QemuOptsList qemu_smp_opts =3D { }, { .name =3D "sockets", .type =3D QEMU_OPT_NUMBER, + }, { + .name =3D "dies", + .type =3D QEMU_OPT_NUMBER, }, { .name =3D "cores", .type =3D QEMU_OPT_NUMBER, --=20 2.21.0