From nobody Fri Apr 26 05:44:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1560318745; cv=none; d=zoho.com; s=zohoarc; b=FHSzgL50LR/FC+z5k3utig6F5tDLL73fmU1xbykSmm7DHUS1MbCuuhj0j4USw5n7kQ85rqXpi5jNAtF8GJjiG6obni3LQ7oH4XaclWxxKEHMHSY5sY/IXm2jDPG2fe9ooK7BnJKwGCtr7ppsDsdoL705lqC9b54tNUAGpsoVxBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560318745; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=swiDDbo8esrQvngN2M3rwA2ZSzcW7vLIVE5TffeyMMw=; b=D4XCKmZEI6VIwkDlFNGVLnULFEfcmanBKPMTXYAwOZEwLrB/L6oq+0hwt1OfjdOkYc3IQViZFg6Et/qeTFbV9arTAv45j+t30XDhUgg+QudTsbk11ORkmuN/P7OBobjPq+mXM07WBpIHrG5pTFDMlI0lc6Z4BjGseZGNiCaUJU4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156031874392233.48824178361974; Tue, 11 Jun 2019 22:52:23 -0700 (PDT) Received: from localhost ([::1]:56812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hawBI-0006lb-T2 for importer@patchew.org; Wed, 12 Jun 2019 01:52:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58391) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haw8j-0004Od-36 for qemu-devel@nongnu.org; Wed, 12 Jun 2019 01:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1haw8h-00070l-Pn for qemu-devel@nongnu.org; Wed, 12 Jun 2019 01:49:41 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:34047) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1haw8g-0006zf-MK; Wed, 12 Jun 2019 01:49:39 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 45NwtQ4zKFz9sBr; Wed, 12 Jun 2019 15:49:34 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1560318574; bh=68ja9D+gsAavD+uwI2kDBEzDvhTjjHe39m37M5/3DuU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MIhTdr6RdAUeIM0HSVZ9yoWdrD3eMUQyOcfZ/ckJmvzcbwUzgb9/6wxqw95vYJOQV E7XQR9Juv3M4aI4uzlbE9zsKTTT2wNVrVbtjg8yNV01awBpZorOWuju8kensrTl6Ph j1Vz/OyGucNg1w6lleAGUyUxVphbsipCWGglodMg= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 12 Jun 2019 15:49:18 +1000 Message-Id: <20190612054929.21136-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190612054929.21136-1-david@gibson.dropbear.id.au> References: <20190612054929.21136-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 02/13] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Anton Blanchard , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Anton Blanchard During the conversion these instructions were incorrectly treated as stores. We need to use set_cpu_vsr* and not get_cpu_vsr*. Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() h= elpers for VSR register access") Signed-off-by: Anton Blanchard Reviewed-by: Mark Cave-Ayland Tested-by: Greg Kurz Reviewed-by: Greg Kurz Message-Id: <20190524065345.25591-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 199d22da97..cdb44b8b70 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); + gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); =20 @@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); =20 EA =3D tcg_temp_new(); @@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx) if (ctx->le_mode) { gen_bswap16x8(xth, xtl, xth, xtl); } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); --=20 2.21.0