From nobody Mon Feb 9 23:17:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1560252244; cv=none; d=zoho.com; s=zohoarc; b=c2yX5wi+qFsNYOukjBzMaLYVS+Z8hvtnOdvbiXrIAs41qbMZUUi7W7Re5hc7VrXlnxQIaB2q/ECkYGjnN1zFCnosouMQjguY/4Wz/QY1h+r2MFyFYbOBdQFitLDn/MSfEfb21EZ2B9S+mf1e8/UoNIPDsZQZY244azyRtuJIWiw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560252244; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=I5NVJmv9QCzY5wd+EPvdgPRW/eLGZfdGGf7zbG7fHeQ=; b=UmFgGCKe/xJl5t29QKwZd3iDq/TPIBjso6OWz7Zi/icp9GlJdU3IvOIuEj2Et69aavIdGld42atzz1yrCSOCJUdTP6xBybz8L3r5Sffw2elemI3ecHK4gmk5neovKzPio4Huxoni8Vg51+KLzoPq7XU13pFnB7HNJHrHHcSZmvo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1560252243967589.4394613769193; Tue, 11 Jun 2019 04:24:03 -0700 (PDT) Received: from localhost ([::1]:56400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haesf-0007WO-Gw for importer@patchew.org; Tue, 11 Jun 2019 07:23:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39137) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1haePv-0007Ex-Jb for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1haePr-0007P0-O7 for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:15 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:37025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1haePr-0007Kd-AZ for qemu-devel@nongnu.org; Tue, 11 Jun 2019 06:54:11 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 22so2394337wmg.2 for ; Tue, 11 Jun 2019 03:54:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e17sm10785945wrt.95.2019.06.11.03.54.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 03:54:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I5NVJmv9QCzY5wd+EPvdgPRW/eLGZfdGGf7zbG7fHeQ=; b=nuOwlMM/TzG3/QetfCKLe6y7JcVQEY7a1p5n0WW/DH5fyUFWBvwej67bqTYiFEwbfh qCI8EdlWY/s2pp/H3Kdilov8e0ZnF0/ljSHtuSb/A2Zi7ES0ftKMHtTTr/6QeNCIWxHu NztxKuTwrX9RWszkGSEVsJTuusUsxHBqzwDTYUagoVmrBR9aAFSrkHseuKksNB/T0gtY nk2L5rFBXBWH+GpEmrZ6aPiI+Ml4VSEZE6hVoAeSjm8rtEOTb6UNZpx7wuhGv72SHE/k UgqpH5R6K3DczpylQ2FkBbA57XwF86262OfLT53fmymIFLCjRaLX8aYTuJgI1lktuQoS sJow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I5NVJmv9QCzY5wd+EPvdgPRW/eLGZfdGGf7zbG7fHeQ=; b=SPsSrCuVyTsd26mviunRUo3afWkFwUvwaApMHat2Esu5s8+48556/iTNa4IXjXg/yz D1kBXdXfXlmMN+LIbaiinWX5gqxk8xP6lfkHXTedwJa5t0L3yCMg9j9AfSq174Fc+zXP NagOlNjixSibssgbgxWMHrrqHqhTUCRXmQ6ZODitzoV57D0RE8uxHZA7grxaxM0MwxG/ olCH0aNMjrvA/tYYrTaQ3WzKhKflNqbBZusVK8NbaslDQbllChUcsP60rM8S4adPG7ot WdyjUr3Nnv0knvLaCnK1ojh7wAqCnT5+CR71LzbIGP3qd44nTDv4pJvvKZArmzYiIg26 2Kgg== X-Gm-Message-State: APjAAAW1MvjOojCrhNVHfImP984Lcf999KXfxurfFeUn7QTpli22mnCz 6IwLE4XK7hBz3c6VE+093WOydg== X-Google-Smtp-Source: APXvYqzk5RYp51m019fcKTs1R0s6wvJBZGJJD2fnZbVSjOEY/9h00z/EPcyv8bUw4LII8FKxAcv7gw== X-Received: by 2002:a1c:a983:: with SMTP id s125mr16393854wme.18.1560250446684; Tue, 11 Jun 2019 03:54:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 11 Jun 2019 11:53:21 +0100 Message-Id: <20190611105351.9871-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190611105351.9871-1-peter.maydell@linaro.org> References: <20190611105351.9871-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PATCH v2 12/42] target/arm: Convert "double-precision" register moves to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 =3D=3D 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 =3D=3D 0x10 * VDUP with B:E =3D=3D 11 * VDUP with Q =3D=3D 1 and Vn<0> =3D=3D 1 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 147 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 83 +------------------ target/arm/vfp.decode | 36 ++++++++ 3 files changed, 185 insertions(+), 81 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 24358f3d3eb..8b0899fa05c 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -475,3 +475,150 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) =20 return true; } + +static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) +{ + /* VMOV scalar to general purpose register */ + TCGv_i32 tmp; + int pass; + uint32_t offset; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + offset =3D a->index << a->size; + pass =3D extract32(offset, 2, 1); + offset =3D extract32(offset, 0, 2) * 8; + + if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D neon_load_reg(a->vn, pass); + switch (a->size) { + case 0: + if (offset) { + tcg_gen_shri_i32(tmp, tmp, offset); + } + if (a->u) { + gen_uxtb(tmp); + } else { + gen_sxtb(tmp); + } + break; + case 1: + if (a->u) { + if (offset) { + tcg_gen_shri_i32(tmp, tmp, 16); + } else { + gen_uxth(tmp); + } + } else { + if (offset) { + tcg_gen_sari_i32(tmp, tmp, 16); + } else { + gen_sxth(tmp); + } + } + break; + case 2: + break; + } + store_reg(s, a->rt, tmp); + + return true; +} + +static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) +{ + /* VMOV general purpose register to scalar */ + TCGv_i32 tmp, tmp2; + int pass; + uint32_t offset; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + offset =3D a->index << a->size; + pass =3D extract32(offset, 2, 1); + offset =3D extract32(offset, 0, 2) * 8; + + if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D load_reg(s, a->rt); + switch (a->size) { + case 0: + tmp2 =3D neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); + tcg_temp_free_i32(tmp2); + break; + case 1: + tmp2 =3D neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); + tcg_temp_free_i32(tmp2); + break; + case 2: + break; + } + neon_store_reg(a->vn, pass, tmp); + + return true; +} + +static bool trans_VDUP(DisasContext *s, arg_VDUP *a) +{ + /* VDUP (general purpose register) */ + TCGv_i32 tmp; + int size, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + if (a->b && a->e) { + return false; + } + + if (a->q && (a->vn & 1)) { + return false; + } + + vec_size =3D a->q ? 16 : 8; + if (a->b) { + size =3D 0; + } else if (a->e) { + size =3D 1; + } else { + size =3D 2; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D load_reg(s, a->rt); + tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + vec_size, vec_size, tmp); + tcg_temp_free_i32(tmp); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3661ed57cd3..08307bb526d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3151,87 +3151,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) /* single register transfer */ rd =3D (insn >> 12) & 0xf; if (dp) { - int size; - int pass; - - VFP_DREG_N(rn, insn); - if (insn & 0xf) - return 1; - if (insn & 0x00c00060 - && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return 1; - } - - pass =3D (insn >> 21) & 1; - if (insn & (1 << 22)) { - size =3D 0; - offset =3D ((insn >> 5) & 3) * 8; - } else if (insn & (1 << 5)) { - size =3D 1; - offset =3D (insn & (1 << 6)) ? 16 : 0; - } else { - size =3D 2; - offset =3D 0; - } - if (insn & ARM_CP_RW_BIT) { - /* vfp->arm */ - tmp =3D neon_load_reg(rn, pass); - switch (size) { - case 0: - if (offset) - tcg_gen_shri_i32(tmp, tmp, offset); - if (insn & (1 << 23)) - gen_uxtb(tmp); - else - gen_sxtb(tmp); - break; - case 1: - if (insn & (1 << 23)) { - if (offset) { - tcg_gen_shri_i32(tmp, tmp, 16); - } else { - gen_uxth(tmp); - } - } else { - if (offset) { - tcg_gen_sari_i32(tmp, tmp, 16); - } else { - gen_sxth(tmp); - } - } - break; - case 2: - break; - } - store_reg(s, rd, tmp); - } else { - /* arm->vfp */ - tmp =3D load_reg(s, rd); - if (insn & (1 << 23)) { - /* VDUP */ - int vec_size =3D pass ? 16 : 8; - tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0), - vec_size, vec_size, tmp); - tcg_temp_free_i32(tmp); - } else { - /* VMOV */ - switch (size) { - case 0: - tmp2 =3D neon_load_reg(rn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); - tcg_temp_free_i32(tmp2); - break; - case 1: - tmp2 =3D neon_load_reg(rn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16= ); - tcg_temp_free_i32(tmp2); - break; - case 2: - break; - } - neon_store_reg(rn, pass, tmp); - } - } + /* already handled by decodetree */ + return 1; } else { /* !dp */ bool is_sysreg; =20 diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 28ee664d8c3..8286bdc0729 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -26,3 +26,39 @@ # 1110 1110 .... .... .... 101. .... .... # (but those patterns might also cover some Neon instructions, # which do not live in this file.) + +# VFP registers have an odd encoding with a four-bit field +# and a one-bit field which are assembled in different orders +# depending on whether the register is double or single precision. +# Each individual instruction function must do the checks for +# "double register selected but CPU does not have double support" +# and "double register number has bit 4 set but CPU does not +# support D16-D31" (which should UNDEF). +%vm_dp 5:1 0:4 +%vm_sp 0:4 5:1 +%vn_dp 7:1 16:4 +%vn_sp 16:4 7:1 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + +%vmov_idx_b 21:1 5:2 +%vmov_idx_h 21:1 6:1 + +# VMOV scalar to general-purpose register; note that this does +# include some Neon cases. +VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ + vn=3D%vn_dp size=3D0 index=3D%vmov_idx_b +VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \ + vn=3D%vn_dp size=3D1 index=3D%vmov_idx_h +VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \ + vn=3D%vn_dp size=3D2 u=3D0 + +VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \ + vn=3D%vn_dp size=3D0 index=3D%vmov_idx_b +VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \ + vn=3D%vn_dp size=3D1 index=3D%vmov_idx_h +VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \ + vn=3D%vn_dp size=3D2 + +VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ + vn=3D%vn_dp --=20 2.20.1