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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id l63sm9749013pfl.181.2019.06.09.19.02.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 09 Jun 2019 19:02:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BPOSGSRwnnlDmzKutwLcU2dnjTQ5x21/pJ7MvOt5Ozw=; b=x1A/kUQIngeKgk36aOdH4fmlltdYL1O9WmCzSkuZhwe/iMfR1K+wj4glBCz6iAo9Lb 6T0VG7NiU0xZ9LLS+UsfzlYsd1E3/cwyitxbWVuQW1Rw94dw2BAy9aUVgE4UJsknS0kR SpVCCd/Xf+hA3ilANcIcKV3HgNIUavXVrAqFX06VRp8Q+2NlE0xeoT4Z3hOQdawxnXdj XUiZlL4TMWcQ1Gs5twCjtcFxbpZPSblE/2c/jKmpOUJ0lGEiQRX1CH6gUW1zptSZ9eJg LkXhfWsUNA3+eM8CjtnGLUj2ubW2CHzVtHKPoxTLwrrm7aYrbgT0U7GWZxz0gI3AV9iI cxVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BPOSGSRwnnlDmzKutwLcU2dnjTQ5x21/pJ7MvOt5Ozw=; b=lLrvHL35sHSTQfPOrNT8ctggOmllGjGx8JrOWT4w80BlRS38NAJAMOdewvJevS7en7 EpLASMKFyMoCKxd/CmAKEz+XqLiFmLNnN6WDRhkwXUtcEzQC/PGaJnIUNNFL7iaQq86k eYLtNn8tN9V8DY0QeOaXRCLMw/wYZm0SsNaCUme1OOA/1tqmoR/FLiLxYQmyCOvajLwS VtR2tlUvPuTYqA5tP8ru2JD7LSkn41qDh37K6M3e034vclHkbyW0/WI+ST+rLgijco0p 0xNpOl5Ima9pYvb28BOe6ylVvNveJwuZ8q6Jw+aOnvos/10/1mBsn05DVwV/0RLeJ0FE MJxg== X-Gm-Message-State: APjAAAWimA9UDuE1WtW2Ht7Kwm4GatpJw1GvpdIHGI+RMvILm0ciZM8Q AO8iVDsULas9THc97PPov/1ENvaVbzw= X-Google-Smtp-Source: APXvYqzRUfAznsSCLKJTl0m2Ehwb4xgnrYHATo9CGTL2mjbfiJ6rv1aWh6RjfnKaSoKzsWVVYOd6yQ== X-Received: by 2002:a63:dc4d:: with SMTP id f13mr13361295pgj.417.1560132168830; Sun, 09 Jun 2019 19:02:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Jun 2019 19:02:02 -0700 Message-Id: <20190610020218.9228-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190610020218.9228-1-richard.henderson@linaro.org> References: <20190610020218.9228-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PULL 23/39] target/riscv: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 ----- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu_helper.c | 10 ++++------ target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 7 +++---- 5 files changed, 14 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ab038bac3..29a1e08f03 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -221,11 +221,6 @@ typedef struct RISCVCPU { } cfg; } RISCVCPU; =20 -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) !=3D 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ =20 void cpu_loop(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c577a262b8..8b6754b917 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -89,14 +89,12 @@ struct CpuAsyncInfo { static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, run_on_cpu_data data) { - CPURISCVState *env =3D &RISCV_CPU(target_cpu_state)->env; - RISCVCPU *cpu =3D riscv_env_get_cpu(env); struct CpuAsyncInfo *info =3D (struct CpuAsyncInfo *) data.host_ptr; =20 if (info->new_mip) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } =20 g_free(info); @@ -212,7 +210,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } =20 - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits; target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; @@ -341,7 +339,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int page_fault_exceptions =3D (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9e2910643..c67d29e206 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) =20 /* flush translation cache */ if (val !=3D env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 env->misa =3D val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno= , target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); + RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return 0; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr =3D val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -724,7 +724,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return -1; } else { if((val ^ env->satp) & SATP_ASID) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } env->satp =3D val; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb35f..331cc36232 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index =3D exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 void helper_wfi(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && @@ -143,8 +143,7 @@ void helper_wfi(CPURISCVState *env) =20 void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && --=20 2.17.1