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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKYt9IdR9p04yclzZJ7NN0tuSnfOmYMB2x4KhMTCD0Y=; b=Xf1bqLviV2uyjpMBVugSD+hc5B7uuH338ROF0FBMDIuwPJ+MTKTyg8Lw/S/Sw5oyMu DE4eYYUaiQdhn00F7LIVnTUgyXIMD3Zza/Iob/bUrOyaehNrpdf4atTHVxRmcsm1+5qb nrkww3eBtg9fXLlbmZUVnSB78QoDAhgPseQMCtW5AcDXqmFS/zPurEaXZuaUiMkFazBB Awu5v6Irmdo3I7KwZpXFlIJ4Z1TVEVAmcKQ6KEwJRYBzUwOakyt9U9jIVw2bh5G3GgyB 5fa9eUaYxvOKg4bhVr/ID/zf+59BcUVUHd9FArT8lJsQ65/sPQpA24XN2XUVFnl6uD6c jPRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IKYt9IdR9p04yclzZJ7NN0tuSnfOmYMB2x4KhMTCD0Y=; b=cGoKAGTknV3Mel+abEJvSCvjlP+R5PAoKTL+XC5iV3Xj5pdyJN4/cLop2OU0vcSUhR TUgye7eZ9uL+HcecEOqZxSuzQE0K67U9USwesNrIZpKkhuyVOhD7u/uyYfKBeTouPLyr 3LYOQmeFCfvwIWOY01X6xeiiSRSAmI/S4+kzv4Dp9lMLXSKoovqPEiyhLBOb8ewQ0m2/ O4Fj3MBWh0QpLPS12jYtNn/sr0WnvitRf65P0Gn2PUGjLLzpRLF7ojQdSPQ8N86237Gn qf8utip5h1i22owvvrRWzlyIbInBRlI8rDjjWYnruddX9klqFsdzjH+OnNrZ6LYWCOXI iZsg== X-Gm-Message-State: APjAAAWNyQmYuyb5UKMBJEFKfxkfBZok/y0MDo16SUzPLWbpj/XnxQGQ AwTEjGSD8bGknqh8W0WlANpfoQ== X-Google-Smtp-Source: APXvYqwjaS1jA8UHMKkOo99Gq9IfwTwZhEJVkk2xDB3iaKFw8NSMJvcRJrrv5hsZSZ+f2R4GFQazkA== X-Received: by 2002:a7b:c189:: with SMTP id y9mr870188wmi.116.1559843180246; Thu, 06 Jun 2019 10:46:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:35 +0100 Message-Id: <20190606174609.20487-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree. Again, trans_VRINT() is temporarily left in translate.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++------------- target/arm/vfp-uncond.decode | 5 +++ 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 312ec455c28..91e3e3680b2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3270,11 +3270,43 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VM= INMAXNM *a) return true; } =20 -static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t = dp, - int rounding) +/* + * Table for converting the most common AArch32 encoding of + * rounding mode to arm_fprounding order (which matches the + * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). + */ +static const uint8_t fp_decode_rm[] =3D { + FPROUNDING_TIEAWAY, + FPROUNDING_TIEEVEN, + FPROUNDING_POSINF, + FPROUNDING_NEGINF, +}; + +static bool trans_VRINT(DisasContext *s, arg_VRINT *a) { - TCGv_ptr fpst =3D get_fpstatus_ptr(0); + uint32_t rd, rm; + bool dp =3D a->dp; + TCGv_ptr fpst; TCGv_i32 tcg_rmode; + int rounding =3D fp_decode_rm[a->rm]; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -3305,7 +3337,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_ptr(fpst); - return 0; + return true; } =20 static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t d= p, @@ -3366,17 +3398,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, return 0; } =20 -/* Table for converting the most common AArch32 encoding of - * rounding mode to arm_fprounding order (which matches the - * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). - */ -static const uint8_t fp_decode_rm[] =3D { - FPROUNDING_TIEAWAY, - FPROUNDING_TIEEVEN, - FPROUNDING_POSINF, - FPROUNDING_NEGINF, -}; - static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) { uint32_t rd, rm, dp =3D extract32(insn, 8, 1); @@ -3389,13 +3410,8 @@ static int disas_vfp_misc_insn(DisasContext *s, uint= 32_t insn) rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && - dc_isar_feature(aa32_vrint, s)) { - /* VRINTA, VRINTN, VRINTP, VRINTM */ - int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; - return handle_vrint(insn, rd, rm, dp, rounding); - } else if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && - dc_isar_feature(aa32_vcvt_dr, s)) { + if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && + dc_isar_feature(aa32_vcvt_dr, s)) { /* VCVTA, VCVTN, VCVTP, VCVTM */ int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; return handle_vcvt(insn, rd, rm, dp, rounding); diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 8ab201fa058..0aa83285de2 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -50,3 +50,8 @@ VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 + +VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ + vm=3D%vm_sp vd=3D%vd_sp dp=3D0 +VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ + vm=3D%vm_dp vd=3D%vd_dp dp=3D1 --=20 2.20.1