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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sfcSfieW8Ddeo0hEC2vM6Cq6H+ydZkZrWTeso5fNmQk=; b=omsel48Lb+6uuwQEsB9Gpvke64DQJnGVuVtN5TQUFlXtjNRMSudslszzDfgEQOPjhH PopwCX73f0SDuF3bf+mLhaxzwOurwz0nczl5aI7N4dqBe0wKnqYkLjazpKC8xwH6xIOX sf/umB7VuziIeLbAMstgvaFDUVQsTqOt1OZ8dWXmrISRhnDKF0pdSIEnfv72xv/SklMh ZxEgcAjOY++Q7YZhfcKqkQud5rBQFj/3wF1rirnZ+6Qe2CbY0hV6S283tv62AkuIw1Od mSRwtSAPH0UjJiYUFR3JcXhnIFHDqXdhMf16IW2p8b4vTzCzdbEEhHid5LAdeflf+KCR XqJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfcSfieW8Ddeo0hEC2vM6Cq6H+ydZkZrWTeso5fNmQk=; b=gPG47/E3gl2HwrYEGNIhTm3zjEQWz6NgCKC0AXwIm5cgrbj73S5CLJpv2EUN65KIku AyhgpimuecPrRsjOUaiDg3nGwYTDwFaJXXGbD2bo5CXKoCe2u/jmOOASUShA8/O2Ahen aBUhfiZkCkDNp28KpJq9q7SEn0rNBOWYQmU0bV3Zq2xYidTDXsS+S+xFzG5/20eSvpT1 P0YI931fN7g2KpP3Ixcz8Bg+/r9JzhftbhRhoby+5Ebd8uXYlY4Rusew3cHUjQpHsPfx g4ZyptlLrVdyKBclj3fqtHPu0qlKzEaR/c+EU5xgLqHgtaxyCS00lsWPdUTsU4XxSnAn cglA== X-Gm-Message-State: APjAAAVpDr70cHWH6fInbZfBVGjmy1D6PmWqD1Sk2vPxZmj3pJ5TVRkF qNbZU8St3d/ZIfloVKeItrb0jg== X-Google-Smtp-Source: APXvYqyHaUCmU9wzxmzfFh+DvZSO75ADUQZmZhzCng2eknOhjyNdb5gA8uEFjurqrD6+Do5L+d7Jiw== X-Received: by 2002:a7b:cc97:: with SMTP id p23mr867964wma.120.1559843177622; Thu, 06 Jun 2019 10:46:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:33 +0100 Message-Id: <20190606174609.20487-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 06/42] target/arm: Convert the VSEL instructions to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VSEL instructions to decodetree. We leave trans_VSEL() in translate.c for now as this allows the patch to show just the changes from the old handle_vsel(). In the old code the check for "do D16-D31 exist" was hidden in the VFP_DREG macro, and assumed that VFPv3 always implied that D16-D31 exist. In the new code we do the correct ID register test. This gives identical behaviour for most of our CPUs, and fixes previously incorrect handling for Cortex-R5F, Cortex-M4 and Cortex-M33, which all implement VFPv3 or better with only 16 double-precision registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/translate-vfp.inc.c | 9 +++++++++ target/arm/translate.c | 35 ++++++++++++++++++++++++---------- target/arm/vfp-uncond.decode | 19 ++++++++++++++++++ 4 files changed, 59 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c34207611ba..30fb107c605 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3408,6 +3408,12 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) +{ + /* Return true if D16-D31 are implemented */ + return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index cf3d7febaa7..f7535138d0f 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -129,3 +129,12 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) =20 return true; } + +/* + * The most usual kind of VFP access check, for everything except + * FMXR/FMRX to the always-available special registers. + */ +static bool vfp_access_check(DisasContext *s) +{ + return full_vfp_access_check(s, false); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 6088ffdc6ee..50545062195 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3076,10 +3076,27 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t r= m, - uint32_t dp) +static bool trans_VSEL(DisasContext *s, arg_VSEL *a) { - uint32_t cc =3D extract32(insn, 20, 2); + uint32_t rd, rn, rm; + bool dp =3D a->dp; + + if (!dc_isar_feature(aa32_vsel, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rn =3D a->vn; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } =20 if (dp) { TCGv_i64 frn, frm, dest; @@ -3101,7 +3118,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, =20 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (cc) { + switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, frn, frm); @@ -3148,7 +3165,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, dest =3D tcg_temp_new_i32(); tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (cc) { + switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm); @@ -3182,7 +3199,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, tcg_temp_free_i32(zero); } =20 - return 0; + return true; } =20 static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn, @@ -3354,10 +3371,8 @@ static int disas_vfp_misc_insn(DisasContext *s, uint= 32_t insn) rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0f800e50) =3D=3D 0x0e000a00 && dc_isar_feature(aa32_vsel= , s)) { - return handle_vsel(insn, rd, rn, rm, dp); - } else if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && - dc_isar_feature(aa32_vminmaxnm, s)) { + if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && + dc_isar_feature(aa32_vminmaxnm, s)) { return handle_vminmaxnm(insn, rd, rn, rm, dp); } else if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && dc_isar_feature(aa32_vrint, s)) { diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index b1d9dc507c2..b7f7c27fe86 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -26,3 +26,22 @@ # 1111 1110 .... .... .... 101. .... .... # (but those patterns might also cover some Neon instructions, # which do not live in this file.) + +# VFP registers have an odd encoding with a four-bit field +# and a one-bit field which are assembled in different orders +# depending on whether the register is double or single precision. +# Each individual instruction function must do the checks for +# "double register selected but CPU does not have double support" +# and "double register number has bit 4 set but CPU does not +# support D16-D31" (which should UNDEF). +%vm_dp 5:1 0:4 +%vm_sp 0:4 5:1 +%vn_dp 7:1 16:4 +%vn_sp 16:4 7:1 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + +VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 +VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 --=20 2.20.1