From nobody Wed Dec 17 06:11:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844967; cv=none; d=zoho.com; s=zohoarc; b=ELjM38QBytv+tKNVA3kT/dYWccA5S/ovn26XhFEeOZXih9IXiG41l1cCeZxHT8PFeqr17tpXkrngO8Zj2mRagfojuJuGbGRCwl1lN77+/ru4EZehekjuH3fkzmCNHnN9tQSW39IUQv64VY/2Sb5s5BvcaS/S+wHCspLxoOP8nNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844967; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=OPmJIDS5EQ/XYTrJS7IKfgCnnuP6L+oh/wc5ZioeaMA=; b=gTNUc2ItbvoDrc0oIhfFYoWV1bZ1J5o4bxBVFGcdvuSf+MwFV740v1qjwpFovs4DboBQV+ug9H/3DOm+8Slm6YTCkac5gzykuEHHpWs78RtrRZfoBt8EV/HCXS1vkrbODEAn+s0A6VzJOh2c+1Ekn1d8AAnX+SSppjlXlM9x3vI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559844967059485.7089689763378; Thu, 6 Jun 2019 11:16:07 -0700 (PDT) Received: from localhost ([127.0.0.1]:36400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwvj-0007tl-Mc for importer@patchew.org; Thu, 06 Jun 2019 14:16:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwUG-0004fj-4x for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU8-0004Gd-Lm for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:40 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43863) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU8-0003Qo-9L for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:32 -0400 Received: by mail-wr1-x441.google.com with SMTP id r18so3320247wrm.10 for ; Thu, 06 Jun 2019 10:46:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OPmJIDS5EQ/XYTrJS7IKfgCnnuP6L+oh/wc5ZioeaMA=; b=YAP0P6+0NIZjQep8hUx2ZRVvPOX2BPiGfh5a2k2s2Rq1di8HrpM1voHArcgjT/rBC+ qCbD1EsmKp1/o0lwtRemDDiREMl5QiQOYdk3BXunLB70qF7j7yH+L+MYQ6JQOH0QbC+w l9Su/02YGlOrQ5HiGMLupJgdc2OmG4cPOC7SOVv1ce6F3ORESdL+3DVhAy8AxDCJNKBc A9ezFuJwmtXzPX/OnA/0o9rmruy58t7D9Iz3TNxu0LffXhnUitufChLesfZK/O9n5UDL RGSqeNVHZaqPL/QU/aU4YKDwn3iace2pNlGXThMROUC7Wr4lRriQZeEVa5HYrLrUl7bu bNVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OPmJIDS5EQ/XYTrJS7IKfgCnnuP6L+oh/wc5ZioeaMA=; b=nc3L/JNYoK2p1H0WdEm23zaNQucUVGCbUe9v2EchTxT5aoj/t13nxtQyeIIFDEQ/SI Xj0ZjgjamDz6WoKHrGtDI9o/c51CRJsKw058fYUhOBEk7WM1jBPgVbCOUEBOrrmJMm5C vJNLBkU9bRFoAmkNLGPgmM1WjduKf5nGtLVk1k44SvVcPkMYZRYyY0NWR+Ci09ApoUWo cdbP6BVmmNSkkQ9y9JF2ofqJMdcVz6NSPduwMI4RCtbtQZpboBjhz3Y1Te1vHLwyXdMf ceBwFonDwQJR0hJa9T+QSWFA6OGxLQgvCyGzxx49gT6HV3NBN/PcqmShB1ByC7AFQAg1 JLuw== X-Gm-Message-State: APjAAAXkg6Gx7u2MO8pKtJ8BYLa4H7U8eCJzJwTKQNhSvJ9QsnRjOt7z Qo6dPrJy5GKIjdYM/q/4w2rS3g== X-Google-Smtp-Source: APXvYqza78vRv1VdlV46zO8iPVj8g7XFAy1jZDRndXnGI90mLGZpQp40V+OIYKyhkv1gjtRt+nwcgg== X-Received: by 2002:a5d:6b03:: with SMTP id v3mr10985542wrw.309.1559843218047; Thu, 06 Jun 2019 10:46:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:09 +0100 Message-Id: <20190606174609.20487-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 42/42] target/arm: Fix short-vector increment behaviour X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask =3D 0xc), if we start with vd =3D 6 and delta_d =3D 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 100 ++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 90bc23ef773..baeea14d56f 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1139,6 +1139,42 @@ typedef void VFPGen3OpDPFn(TCGv_i64 vd, typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); =20 +/* + * Return true if the specified S reg is in a scalar bank + * (ie if it is s0..s7) + */ +static inline bool vfp_sreg_is_scalar(int reg) +{ + return (reg & 0x18) =3D=3D 0; +} + +/* + * Return true if the specified D reg is in a scalar bank + * (ie if it is d0..d3 or d16..d19) + */ +static inline bool vfp_dreg_is_scalar(int reg) +{ + return (reg & 0xc) =3D=3D 0; +} + +/* + * Advance the S reg number forwards by delta within its bank + * (ie increment the low 3 bits but leave the rest the same) + */ +static inline int vfp_advance_sreg(int reg, int delta) +{ + return ((reg + delta) & 0x7) | (reg & ~0x7); +} + +/* + * Advance the D reg number forwards by delta within its bank + * (ie increment the low 2 bits but leave the rest the same) + */ +static inline int vfp_advance_dreg(int reg, int delta) +{ + return ((reg + delta) & 0x3) | (reg & ~0x3); +} + /* * Perform a 3-operand VFP data processing instruction. fn is the * callback to do the actual operation; this function deals with the @@ -1149,7 +1185,6 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpS= PFn *fn, { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 f0, f1, fd; TCGv_ptr fpst; @@ -1164,16 +1199,14 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, } =20 if (veclen > 0) { - bank_mask =3D 0x18; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D s->vec_stride + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1204,11 +1237,11 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); + vn =3D vfp_advance_sreg(vn, delta_d); neon_load_reg32(f0, vn); if (delta_m) { - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vm =3D vfp_advance_sreg(vm, delta_m); neon_load_reg32(f1, vm); } } @@ -1226,7 +1259,6 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 f0, f1, fd; TCGv_ptr fpst; @@ -1246,16 +1278,14 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, } =20 if (veclen > 0) { - bank_mask =3D 0xc; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D (s->vec_stride >> 1) + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1285,11 +1315,11 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, } /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + vd =3D vfp_advance_dreg(vd, delta_d); + vn =3D vfp_advance_dreg(vn, delta_d); neon_load_reg64(f0, vn); if (delta_m) { - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vm =3D vfp_advance_dreg(vm, delta_m); neon_load_reg64(f1, vm); } } @@ -1306,7 +1336,6 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 @@ -1320,16 +1349,14 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2O= pSPFn *fn, int vd, int vm) } =20 if (veclen > 0) { - bank_mask =3D 0x18; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D s->vec_stride + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1355,7 +1382,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) if (delta_m =3D=3D 0) { /* single source one-many */ while (veclen--) { - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + vd =3D vfp_advance_sreg(vd, delta_d); neon_store_reg32(fd, vd); } break; @@ -1363,8 +1390,8 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); + vm =3D vfp_advance_sreg(vm, delta_m); neon_load_reg32(f0, vm); } =20 @@ -1378,7 +1405,6 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 @@ -1397,16 +1423,14 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) } =20 if (veclen > 0) { - bank_mask =3D 0xc; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D (s->vec_stride >> 1) + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1432,7 +1456,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) if (delta_m =3D=3D 0) { /* single source one-many */ while (veclen--) { - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + vd =3D vfp_advance_dreg(vd, delta_d); neon_store_reg64(fd, vd); } break; @@ -1440,8 +1464,8 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vd =3D vfp_advance_dreg(vd, delta_d); + vd =3D vfp_advance_dreg(vm, delta_m); neon_load_reg64(f0, vm); } =20 @@ -1783,7 +1807,6 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp = *a) static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) { uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 fd; uint32_t n, i, vd; @@ -1804,9 +1827,8 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) } =20 if (veclen > 0) { - bank_mask =3D 0x18; /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { @@ -1835,7 +1857,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); } =20 tcg_temp_free_i32(fd); @@ -1845,7 +1867,6 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) { uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 fd; uint32_t n, i, vd; @@ -1871,9 +1892,8 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) } =20 if (veclen > 0) { - bank_mask =3D 0xc; /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { @@ -1902,7 +1922,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vfp_advance_dreg(vd, delta_d); } =20 tcg_temp_free_i64(fd); --=20 2.20.1