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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KtIfSIKYeaE77uLCULn8mRdtcD4iWxd4JC2TjSFb1R8=; b=SiFVQbaorp/ryzAfQvS9FdhoS3ZlfB/R7KNWo22KXM5RnAbfpAQzuVedj9rm29reWX Odpz2vu1fthyMOZtAktNuQVfn7MvDNHRIub81oqb9mMwfyoUiyBEVmx1otGtj2eUMrx0 O/5Uv+pnwe9L30Qg3kWlilCr+wVaDmgK9vU6Up9X1K0OcH5t9pd+JI+Oamg49eMcRO45 pAjhZI3T509giCCdxmrhOhA1YuKE9Zpr/W35+PDFLLInRnfG2ULB5cJ8HQWOwv9zWKsm xmok6zVVWJ9xxnMXSGR+f9icxays5c2xCsYCwl+/uEqZdk3Ivh1qLWYxBnADVsAGzFPR wnbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KtIfSIKYeaE77uLCULn8mRdtcD4iWxd4JC2TjSFb1R8=; b=iWPNnpBWcgeCfGidiSemg/QzFTSx1uVVsP5KXAEoWvQuFLSNtGCNtwMXfudGjLVxqy Rkzga9u2xrN6eqBnBmf3ctS+2eNYkSkjN1wiXVfGLADdsEQ1DS8/D0wlSV9Zz21jLGRt Apz8m1eQmPBJIp5XeHhUCxzdYHpXKMFqtzKz7ySlYwHwBEq3kFVt2vD8eFVtiuZItAnb t6JhtC054FPFUrgFvp5Rt9umHLkyMwbWWagVIH5JIv2PU7S2IDxquwhcyoERJmcZyG60 AEDbXfvoF/MeH3C7f1tkEVum2naZuL/jz3SH1ftmjhYH5PfHoikEnWdQk4+7AiPjJN+s zwIw== X-Gm-Message-State: APjAAAXZHnz05xhDZphynUrZMNkmRqjWRILh8y/WtuBJqDOLSCA+D+fG NJinQZwQMwh5DK8nWMs0mSVXSADivofigw== X-Google-Smtp-Source: APXvYqzXshMuRQGP88bBQ+eq4SsY5oa2Rnl05O4Z+qQEI8N9BgO06AkZtIQQFLu6eq9IcTPe2ZoZzQ== X-Received: by 2002:a1c:cfc3:: with SMTP id f186mr759827wmg.134.1559843172539; Thu, 06 Jun 2019 10:46:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:28 +0100 Message-Id: <20190606174609.20487-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 01/42] decodetree: Fix comparison of Field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Typo comparing the sign of the field, twice, instead of also comparing the mask of the field (which itself encodes both position and length). Reported-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190604154225.26992-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- scripts/decodetree.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 81874e22cc7..d7a59d63ac3 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -184,7 +184,7 @@ class Field: return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len) =20 def __eq__(self, other): - return self.sign =3D=3D other.sign and self.sign =3D=3D other.sign + return self.sign =3D=3D other.sign and self.mask =3D=3D other.mask =20 def __ne__(self, other): return not self.__eq__(other) --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559843765; cv=none; d=zoho.com; s=zohoarc; b=aHqVr1ITH09uuwUl70RwftfGWvAYfSXHx4txKxxZ58rlYu4wOyAipB+dQypumploi9OyyrCtP2yr9hKf99fwXn1F86XRuaV8ndCRW1fkqk7r4Mpzy8aRcIFW5qQJEigbW9G0eIGX/xbivSZ8uV0xKV0jCd24DVJQYvn/7/+4XCc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559843765; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=j5ydsVQQjlU+U9mkvBoHU9cgpy9nhwg90mny4tusCq8=; b=ekfLTCiquvQmNlEfT22+F7JEuDnQqvbG+xcuyvAFQZxjBwpBm0Ut+tOzbpRSqpeDY+QNnd6bUBradEzdsI8EvRb1xghIoOt5a555p8prxLDQQaFEC2XxTJ2NfYcqj14X+/E+Ar8SJDf3EqS72sp9kHHp8Az2ieMxhDAiMacFifI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559843764993547.3321826871794; Thu, 6 Jun 2019 10:56:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:36020 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwcH-0003Yb-LU for importer@patchew.org; Thu, 06 Jun 2019 13:55:57 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwTo-00048I-SA for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwTl-0003b3-6D for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:11 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:34258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwTj-0002nf-Ec for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:07 -0400 Received: by mail-wm1-x341.google.com with SMTP id w9so2345892wmd.1 for ; Thu, 06 Jun 2019 10:46:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j5ydsVQQjlU+U9mkvBoHU9cgpy9nhwg90mny4tusCq8=; b=JDSC3XoQRb0UdYw73cJW3jfkO++We1GFd7tVp3oGIRW3fNvDG6MBu0Kw0kvFPK4Z7/ b9j1vb14FZpYuT0riKCpvNesVTx7eCaBb7Ce+b7TN/S4fOgEP7uLZBun8HGxN9xEZcTB +PRGEklUn0S56LCYPvyR7DBOFkyaEIa411h68IS5TASdIKB674zncB+7Kzs71U0lL2wj wHNs4VWct5MI2rl18bXpKYVV9xjwbDRMI8pN4YsgMYZhV7CPgxiGLhZfvwnpcNXZI4xj ykYpgIlKms9N+ey+LK6BcNMCq+Ax82onpQlvGIK9Ng9qKGRCfokyTRtqsnCYdDlrcOjs VWtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j5ydsVQQjlU+U9mkvBoHU9cgpy9nhwg90mny4tusCq8=; b=tFfGthzG38+WEt7mhNpwe1Wmvl9xhT8+P1xDWD2udzp8kRppCGLplTDn6/2T+cBS5Z N7xIUSVwoGobYOMU+AAJ3qghEpQ0G7tHMdp07Qm2xM/nqDAaRmCzpNX93JlB9mUV2Efa 1eEGxbCOb4DPrRKbnipYjWRSch2vTzYW7dx4qoOW1YTpZInbv8tUyXlmT8FkNzqokPPB Xts5soaoaPYkNhwB+lzPfquLAp2Q4ABaUspijKzrngEkF/7tbHggez2vPo/dD0OXZ4yV GMUt+4T++nyCGQVyle8t/DDi3HVOsCLWRNXnP3LiDURvu/5iZgvuYwAGU9nWVo1Jt/Ok rdfg== X-Gm-Message-State: APjAAAVhE4i5nfzCFFwwA+yinN2tI3wpU1sPi7VR9riTPe2dRm9H4QMZ bip2us/zX/Ic5xyofICjxytQeg== X-Google-Smtp-Source: APXvYqwr6jpylUFNVlRiBg9G+D5AfmWXQXi8CRFjEJHptewK6c62NEYH2gwm6O/dbemILJ7v5VMDew== X-Received: by 2002:a1c:730d:: with SMTP id d13mr806883wmb.88.1559843173672; Thu, 06 Jun 2019 10:46:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:29 +0100 Message-Id: <20190606174609.20487-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 02/42] target/arm: Add stubs for AArch32 VFP decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the infrastructure for building and invoking a decodetree decoder for the AArch32 VFP encodings. At the moment the new decoder covers nothing, so we always fall back to the existing hand-written decode. We need to have one decoder for the unconditional insns and one for the conditional insns, as otherwise the patterns for conditional insns would incorrectly match against the unconditional ones too. Since translate.c is over 14,000 lines long and we're going to be touching pretty much every line of the VFP code as part of the decodetree conversion, we create a new translate-vfp.inc.c to hold the code which deals with VFP in the new scheme. It should be possible to convert this into a standalone translation unit eventually, but the conversion process will be much simpler if we simply #include it midway through translate.c to start with. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/Makefile.objs | 13 +++++++++++++ target/arm/translate-vfp.inc.c | 31 +++++++++++++++++++++++++++++++ target/arm/translate.c | 19 +++++++++++++++++++ target/arm/vfp-uncond.decode | 28 ++++++++++++++++++++++++++++ target/arm/vfp.decode | 28 ++++++++++++++++++++++++++++ 5 files changed, 119 insertions(+) create mode 100644 target/arm/translate-vfp.inc.c create mode 100644 target/arm/vfp-uncond.decode create mode 100644 target/arm/vfp.decode diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 6bdcc65c2c8..dfa736a3752 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -19,5 +19,18 @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.= decode $(DECODETREE) $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.deco= de $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c +target/arm/translate.o: target/arm/decode-vfp.inc.c +target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c + obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c new file mode 100644 index 00000000000..3447b3e6466 --- /dev/null +++ b/target/arm/translate-vfp.inc.c @@ -0,0 +1,31 @@ +/* + * ARM translation: AArch32 VFP instructions + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2005-2007 CodeSourcery + * Copyright (c) 2007 OpenedHand, Ltd. + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * This file is intended to be included from translate.c; it uses + * some macros and definitions provided by that file. + * It might be possible to convert it to a standalone .c file eventually. + */ + +/* Include the generated VFP decoder */ +#include "decode-vfp.inc.c" +#include "decode-vfp-uncond.inc.c" diff --git a/target/arm/translate.c b/target/arm/translate.c index d240c1b7144..ca9e0bfd99e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1727,6 +1727,9 @@ static inline void gen_mov_vreg_F0(int dp, int reg) =20 #define ARM_CP_RW_BIT (1 << 20) =20 +/* Include the VFP decoder */ +#include "translate-vfp.inc.c" + static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); @@ -3384,6 +3387,22 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) return 1; } =20 + /* + * If the decodetree decoder handles this insn it will always + * emit code to either execute the insn or generate an appropriate + * exception; so we don't need to ever return non-zero to tell + * the calling code to emit an UNDEF exception. + */ + if (extract32(insn, 28, 4) =3D=3D 0xf) { + if (disas_vfp_uncond(s, insn)) { + return 0; + } + } else { + if (disas_vfp(s, insn)) { + return 0; + } + } + /* FIXME: this access check should not take precedence over UNDEF * for invalid encodings; we will generate incorrect syndrome informat= ion * for attempts to execute invalid vfp/neon encodings with FP disabled. diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode new file mode 100644 index 00000000000..b1d9dc507c2 --- /dev/null +++ b/target/arm/vfp-uncond.decode @@ -0,0 +1,28 @@ +# AArch32 VFP instruction descriptions (unconditional insns) +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# Encodings for the unconditional VFP instructions are here: +# generally anything matching A32 +# 1111 1110 .... .... .... 101. ...0 .... +# and T32 +# 1111 110. .... .... .... 101. .... .... +# 1111 1110 .... .... .... 101. .... .... +# (but those patterns might also cover some Neon instructions, +# which do not live in this file.) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode new file mode 100644 index 00000000000..28ee664d8c3 --- /dev/null +++ b/target/arm/vfp.decode @@ -0,0 +1,28 @@ +# AArch32 VFP instruction descriptions (conditional insns) +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# Encodings for the conditional VFP instructions are here: +# generally anything matching A32 +# cccc 11.. .... .... .... 101. .... .... +# and T32 +# 1110 110. .... .... .... 101. .... .... +# 1110 1110 .... .... .... 101. .... .... +# (but those patterns might also cover some Neon instructions, +# which do not live in this file.) --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559843959; cv=none; d=zoho.com; s=zohoarc; b=balFKRuHxP9J9zJ1H2b4RzqhDqYTWZA2JsrnV4eZ2Al5b1Q3UrJ/rAoBTwpxUEQ+Ci/1+SI+EgI/i+lGmzg6zKtzOaNlg/5p3NgxLwIzEACTMhh+NrUe/oOM67cG5+1IaWNY5fxNgMb5LwTQ5tThw1prNbtQidCKK1v9zflbQNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559843959; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YpYRRdgRhzNXtTHb+mlZtWZev3S3aQYGhaPt/SJ1b1I=; b=T3CMWIH5cjko1myHtVkeUWivWn5QxL8q5L0ACmGXUxsqRYQbUU+TCfig6mtT0siheag2xh9hafRgvMUlQd5OCoVsxc5mDwEB9+rWTWH/XCFHvLDx8wX9hJegJLOD2XrX77dLk1dcZqCueEQBbfU33MO6eHaE2SiASJ7FkpgeRZk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559843959395995.943104259641; Thu, 6 Jun 2019 10:59:19 -0700 (PDT) Received: from localhost ([127.0.0.1]:36061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwfU-0006UV-98 for importer@patchew.org; Thu, 06 Jun 2019 13:59:16 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwU6-0004Sl-L8 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU3-000456-Ki for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:29 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:45601) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU2-0002o5-9k for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:26 -0400 Received: by mail-wr1-x444.google.com with SMTP id f9so3304478wre.12 for ; Thu, 06 Jun 2019 10:46:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YpYRRdgRhzNXtTHb+mlZtWZev3S3aQYGhaPt/SJ1b1I=; b=gKi1snmKy4Du8yZDDRmsAPTqxKvAbH4j66UKxuqbpP0XrRL2VbyXez1X0eNijJ3sDA AHlTREQaLlHL+KI+v21xQs5Wj5PXgk1vV1DKLB/BCiW/1t+V1PhG0okrXjCwvO3YgRZJ uXkM4Dxm9bCXDUdmJtJQpzsJiuT9CPGAyQV35sAiXUE6lgkNsktx33PtjkEgIc3hf+kO qq6v/55NcRzuHWnx0itBEcvRl0TPi2kEGtoTjEPrH7yfB134f7RXVMUyuks0ZOHrNZz+ xGN8GWnWajI2lYlfWahdEnQGyujFxYHeCE3qlntVczegbxZ9g7/v6+FvRPCKmHzC1c0W 42Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YpYRRdgRhzNXtTHb+mlZtWZev3S3aQYGhaPt/SJ1b1I=; b=D8zFLEmSRU4EsXEIBvXuRAzyBLZj9QYXmaVm8pLTaRI9goPxYEQZ0aseQzg5lHColc KmKhimlG9G1Dz5TTcbD0WDLAjLz5AqobtNSCw0A3zpkKm6o5Ww8sTCpXx3nM8i8k32eT //EtXU9Jk1ChmbQTd1axIur0IhwGg+oc2q59JJEZ4/SXscvoth92fQNmpAzMtjnrQGYQ zUJQ+VXhfxx5oYhj4ma+wAZWI2U9e2V72YPnVQDQ2F0L/aPcsoXuG88NGnvzfIcsvrId s3DCwzMDYAtgGMyi/3cxUJHMrJSTytGjg1N/pf7iVNZOTgJoJDkrsP+oCo/f72o1KjD/ EmEQ== X-Gm-Message-State: APjAAAVOuopKciUHbVhy1M1vjOxRxIfMTbIJfWINOQdUo9NCIYz9VT4E nmggS6fHrIB+ucWQo8vdZcbUXg== X-Google-Smtp-Source: APXvYqwtaUfxCvQq5eW/5WYzq20VtJfbpdRYWJ46oFBxm2Pm/r3HFC19j64qjgPZdH+0Td4hgc/Afw== X-Received: by 2002:a5d:53d2:: with SMTP id a18mr3579999wrw.98.1559843174729; Thu, 06 Jun 2019 10:46:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:30 +0100 Message-Id: <20190606174609.20487-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 03/42] target/arm: Factor out VFP access checking code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 100 ++++++++++++++++++++++++++++++++ target/arm/translate.c | 101 +++++---------------------------- 2 files changed, 113 insertions(+), 88 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3447b3e6466..cf3d7febaa7 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -29,3 +29,103 @@ /* Include the generated VFP decoder */ #include "decode-vfp.inc.c" #include "decode-vfp-uncond.inc.c" + +/* + * Check that VFP access is enabled. If it is, do the necessary + * M-profile lazy-FP handling and then return true. + * If not, emit code to generate an appropriate exception and + * return false. + * The ignore_vfp_enabled argument specifies that we should ignore + * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX + * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other = insns. + */ +static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) +{ + if (s->fp_excp_el) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + s->fp_excp_el); + } else { + gen_exception_insn(s, 4, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } + return false; + } + + if (!s->vfp_enabled && !ignore_vfp_enabled) { + assert(!arm_dc_feature(s, ARM_FEATURE_M)); + gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); + return false; + } + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* Handle M-profile lazy FP state mechanics */ + + /* Trigger lazy-state preservation if necessary */ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount. + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact =3D false; + } + + /* Update ownership of FP context: set FPCCR.S to match current st= ate */ + if (s->v8m_fpccr_s_wrong) { + TCGv_i32 tmp; + + tmp =3D load_cpu_field(v7m.fpccr[M_REG_S]); + if (s->v8m_secure) { + tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); + } else { + tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); + } + store_cpu_field(tmp, v7m.fpccr[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v8m_fpccr_s_wrong =3D false; + } + + if (s->v7m_new_fp_ctxt_needed) { + /* + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA + * and the FPSCR. + */ + TCGv_i32 control, fpscr; + uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK; + + fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + /* + * We don't need to arrange to end the TB, because the only + * parts of FPSCR which we cache in the TB flags are the VECLEN + * and VECSTRIDE, and those don't exist for M-profile. + */ + + if (s->v8m_secure) { + bits |=3D R_V7M_CONTROL_SFPA_MASK; + } + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_ori_i32(control, control, bits); + store_cpu_field(control, v7m.control[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v7m_new_fp_ctxt_needed =3D false; + } + } + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index ca9e0bfd99e..6088ffdc6ee 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3373,8 +3373,10 @@ static int disas_vfp_misc_insn(DisasContext *s, uint= 32_t insn) return 1; } =20 -/* Disassemble a VFP instruction. Returns nonzero if an error occurred - (ie. an undefined instruction). */ +/* + * Disassemble a VFP instruction. Returns nonzero if an error occurred + * (ie. an undefined instruction). + */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; @@ -3382,6 +3384,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; + bool ignore_vfp_enabled =3D false; =20 if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { return 1; @@ -3403,98 +3406,20 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) } } =20 - /* FIXME: this access check should not take precedence over UNDEF + /* + * FIXME: this access check should not take precedence over UNDEF * for invalid encodings; we will generate incorrect syndrome informat= ion * for attempts to execute invalid vfp/neon encodings with FP disabled. */ - if (s->fp_excp_el) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), - s->fp_excp_el); - } else { - gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); - } - return 0; - } - - if (!s->vfp_enabled) { - /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. = */ - if ((insn & 0x0fe00fff) !=3D 0x0ee00a10) - return 1; + if ((insn & 0x0fe00fff) =3D=3D 0x0ee00a10) { rn =3D (insn >> 16) & 0xf; - if (rn !=3D ARM_VFP_FPSID && rn !=3D ARM_VFP_FPEXC && rn !=3D ARM_= VFP_MVFR2 - && rn !=3D ARM_VFP_MVFR1 && rn !=3D ARM_VFP_MVFR0) { - return 1; + if (rn =3D=3D ARM_VFP_FPSID || rn =3D=3D ARM_VFP_FPEXC || rn =3D= =3D ARM_VFP_MVFR2 + || rn =3D=3D ARM_VFP_MVFR1 || rn =3D=3D ARM_VFP_MVFR0) { + ignore_vfp_enabled =3D true; } } - - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* Handle M-profile lazy FP state mechanics */ - - /* Trigger lazy-state preservation if necessary */ - if (s->v7m_lspact) { - /* - * Lazy state saving affects external memory and also the NVIC, - * so we must mark it as an IO operation for icount. - */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_v7m_preserve_fp_state(cpu_env); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } - /* - * If the preserve_fp_state helper doesn't throw an exception - * then it will clear LSPACT; we don't need to repeat this for - * any further FP insns in this TB. - */ - s->v7m_lspact =3D false; - } - - /* Update ownership of FP context: set FPCCR.S to match current st= ate */ - if (s->v8m_fpccr_s_wrong) { - TCGv_i32 tmp; - - tmp =3D load_cpu_field(v7m.fpccr[M_REG_S]); - if (s->v8m_secure) { - tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); - } else { - tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); - } - store_cpu_field(tmp, v7m.fpccr[M_REG_S]); - /* Don't need to do this for any further FP insns in this TB */ - s->v8m_fpccr_s_wrong =3D false; - } - - if (s->v7m_new_fp_ctxt_needed) { - /* - * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA - * and the FPSCR. - */ - TCGv_i32 control, fpscr; - uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK; - - fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); - gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(fpscr); - /* - * We don't need to arrange to end the TB, because the only - * parts of FPSCR which we cache in the TB flags are the VECLEN - * and VECSTRIDE, and those don't exist for M-profile. - */ - - if (s->v8m_secure) { - bits |=3D R_V7M_CONTROL_SFPA_MASK; - } - control =3D load_cpu_field(v7m.control[M_REG_S]); - tcg_gen_ori_i32(control, control, bits); - store_cpu_field(control, v7m.control[M_REG_S]); - /* Don't need to do this for any further FP insns in this TB */ - s->v7m_new_fp_ctxt_needed =3D false; - } + if (!full_vfp_access_check(s, ignore_vfp_enabled)) { + return 0; } =20 if (extract32(insn, 28, 4) =3D=3D 0xf) { --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844298; cv=none; d=zoho.com; s=zohoarc; b=LE/WlJAbHhCdueoSp56C8aikIrdlLBGmhPN+ssa3QwwV2fSG0BUmLSB0z8B52K2qtiqJxlihZNo+xDbepJCzVBfLHqwlou5/MEY1dM994/Yk+H7yGlRHh7Y6qMyA3j1FttRbuP4VJsU2jyFm3neoFXWewEDYr3mSlpCkB5HDZcE= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pYfiMlZ410Gu/yfJlg4smSlx90e446JdIiRcC7Wt8I8=; b=N/5VKgXJeJgKaBkyidWHeRwTXUGH+kCReU1OdaXezEzQylde7mvNxNYq9ewGJqWN/b Qssd6wWbuEd/kOq9FrEeCUqNl5MlItnGRo5OgfLREYpOqyxKX39sc4gBDue6kIzDmWQi ddKHw2lo3jQekv8aE4+bOXpihzXtfAOSKlZ22xFVOjYznI8cid0O1FqVIhzCAdqcf+sO GhDZyudLN2KiwzNMmoVS0J4aRZ2YtckDmqMlAzcItHfCt+9HqM4jPy81Mdg7tbRZ+4Ml Tvg32iEPjWLmJV8s/xSNeGYGd+zJYDs/jgBQrH5NjzBZLv97zsGGMhbRqXO72AL7MgGD TpqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pYfiMlZ410Gu/yfJlg4smSlx90e446JdIiRcC7Wt8I8=; b=HCB+/ptL4A7bs/LHJ4LLIPBveXYB4YGL7qPN8IGw+oQTZFCua+OJV0GCxIk2rqUcoZ SqeB48TZJ6qI6Vp/O8AK/95+si6xUjQIlyTA5di5BHDaIDT3EcmQIX0qAO54ld/ZgPez C5jm8ZuG1Eq7ME4sVkF/C+vTury9iTcGZGEUh17umus28G7l5C2bqikALloYe564TBKt /Sf6OGh9sDCQaBtPfADkQPrr8HKuNp2XJHjt6CcNplJtpjibZyIcuZT3uZDirxbqGR6A IWhXRvxMoYOal45EuQJaTIQ3xywo8EmpKU/90a6PybbQy/q37gFt9pZeKMfYBKD01YO+ AEYg== X-Gm-Message-State: APjAAAXslTuT9GCOhZFQRQV1KAlK6NIneOJcJGHdtkRggzG36Ra92r7Q L/p8ynrh+YowEY52y4xFo/n84Q== X-Google-Smtp-Source: APXvYqyC86SQAX8n8+Ua7px2+ong1PVIu8wgAMIYuaDsmtLEbN2Mvgcpl2x/Vr7I0FSudq9bj6g4PA== X-Received: by 2002:a5d:4603:: with SMTP id t3mr7682237wrq.315.1559843175592; Thu, 06 Jun 2019 10:46:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:31 +0100 Message-Id: <20190606174609.20487-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 04/42] target/arm: Fix Cortex-R5F MVFR values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Cortex-R5F initfn was not correctly setting up the MVFR ID register values. Fill these in, since some subsequent patches will use ID register checks rather than CPU feature bit checks. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b23ac2c935..044c4dd738b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1608,6 +1608,8 @@ static void cortex_r5f_initfn(Object *obj) =20 cortex_r5_initfn(obj); set_feature(&cpu->env, ARM_FEATURE_VFP3); + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x00000011; } =20 static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844092; cv=none; d=zoho.com; s=zohoarc; b=aMwqFTAnZU5NICbWwM1y84Okx5miyWD5mjLECtKl3CMPSBEt5esFSvkFB50tzP1zPuUzsF+rjRXKCcYpjIKT53lAC+j+0XUAvGW4s70UMvz2SN0CY2dFZcCAXp9zldDO2GnQAwzLDvMbFBbgQD18bihbILSbiLe/KKjyVW9BRfs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844092; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wNEHwgukf5WI/ZuQacjhcTdXxd4lEFqyWVkk+y0IZC0=; b=MIazC34KVDUegYs3ZE3dttMmjrtoeokAuBfQbjQ3x8Cx/iUPvqCaF/Ol5Cbwu01fVNFVXeObER968wQv/O4tVzENNBMVz+31G68t3CH0UGUQSTQaPQ/18Rw6t9AkNpsf7fupv34drXf8g11vGZB1aAGyAGy/NecUd3pww86d/3k= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155984409280526.20274154702463; Thu, 6 Jun 2019 11:01:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:36114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwhf-00008i-As for importer@patchew.org; Thu, 06 Jun 2019 14:01:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44790) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwU4-0004QQ-T1 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU2-000424-H8 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:27 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45600) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwTz-0002pT-St for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:25 -0400 Received: by mail-wr1-x442.google.com with SMTP id f9so3304550wre.12 for ; Thu, 06 Jun 2019 10:46:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wNEHwgukf5WI/ZuQacjhcTdXxd4lEFqyWVkk+y0IZC0=; b=j9EMf2NwkPeJmzEgzfvuUyB51g/EJRMPiYpORuQDdq4eCbShcS3tBMtCovlpMX3uYj CW/sDksKFru9nMLdeUWqOBIrzYSqLF1NOPi3tZUXWfs71wCVB3Ih4Uro84UJwLSrSbAz orZdxzqwRo8OXpoCobCBz59SJRJMRTV99ONa7kxnBacTVh8TkNkiae5PLb8CyjZw+l2P xcO0aUexzpSMsobGwiLudksQYHwtPrz651pFkd9ST/5Wdv/KTP+gNFHg2UXA3dopWIyz 4T4xhRSS7FB6hSGZ/KYUCvGEISQK7tBQ64OrdaynenVLa+c70joe2nEQ/TMdeDMib3dY eYWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wNEHwgukf5WI/ZuQacjhcTdXxd4lEFqyWVkk+y0IZC0=; b=fG0diqsQVqBqjVIWJy2jf92IRELsWX6bw+u4fxHD/Lku8gio2F2eECB6X7U03hl6u3 KBH/wyQ9138DnhYyFHkDAP4jZgpSX1FzvVg3RDGpeRk3RePd5wa+AJDIKRJfAzj7eTND bt+MjtuaFwrCAEVw5RCdFs6NGGRe7YLRVD1GoXSoc4m4twVPFDc6x35sbu7XGr2Ln3mS 08Y41IxmSdeHojQge8Uv0X5to+0FVbt5cozRzzbu28lD23puQX/DngZGMYCc684IoEjF l9S3N3aFMr/9aAQAQk9hJICi43M9AqZjTxNHv6cfOiHR0ekxnc2GaabdhCeX9yRzILU6 qs+Q== X-Gm-Message-State: APjAAAWeaIMf1CZ+JVnLjwemfAwbUv79smPasA0Y6iyDko+RK7/DdRxu NjGHkKvvxz67bAv2C/IMYgfCWiyVDAJxYA== X-Google-Smtp-Source: APXvYqwChzrIVQbVxudiR0nyWL6jb8rGmguMxUAh+binptojfe4/ERTcCqjJWXtDnsUZ+MA7gOf8LQ== X-Received: by 2002:a5d:6949:: with SMTP id r9mr15934727wrw.73.1559843176537; Thu, 06 Jun 2019 10:46:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:32 +0100 Message-Id: <20190606174609.20487-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the moment our -cpu max for AArch32 supports VFP short-vectors because we always implement them, even for CPUs which should not have them. The following commits are going to switch to using the correct ID-register-check to enable or disable short vector support, so we need to turn it on explicitly for -cpu max, because Cortex-A15 doesn't implement it. We don't enable this for the AArch64 -cpu max, because the v8A architecture never supports short-vectors. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 044c4dd738b..3f06f6d1a20 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2022,6 +2022,10 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set (all of) the ID registers to --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844834; cv=none; d=zoho.com; s=zohoarc; b=D0GgnmjnmaINrmEwZtLYf7+tSESzDgwDnK0TbRv6fa4bxOYfoPbWus37bgMZTZ4jqpHEv/CxgFKOe8gPqywO5uBcH+mrDir3LjqyzYnbsBVI2SP+tCpphmLCbNVn4o8bVxK9rCN6/uF0LbwR2JyR3nK6OxGpX03mfD/B9yBWlG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844834; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sfcSfieW8Ddeo0hEC2vM6Cq6H+ydZkZrWTeso5fNmQk=; b=SAOFqJJNBpm3VEx4pggQM4f7E88MnPkzIbcJVdf5/jTMeeFvZj+KTGlRLLAGFy/zyYBukz8Kb/34hR9klMJa2Zt+bXKvrKznSMgfMdNShOzItSBM5mZtoGfo91EdeU9KHvzTLw3Q/yd7S56swB9XLEEmyy3BSexwG/MLGUeJ0ZI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155984483435380.8735623439701; Thu, 6 Jun 2019 11:13:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:36330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwtV-0005pI-7L for importer@patchew.org; Thu, 06 Jun 2019 14:13:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwU9-0004Xu-MT for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU7-0004BQ-44 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:33 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:32819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU6-0002q6-Pe for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:30 -0400 Received: by mail-wm1-x342.google.com with SMTP id h19so2352194wme.0 for ; Thu, 06 Jun 2019 10:46:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sfcSfieW8Ddeo0hEC2vM6Cq6H+ydZkZrWTeso5fNmQk=; b=omsel48Lb+6uuwQEsB9Gpvke64DQJnGVuVtN5TQUFlXtjNRMSudslszzDfgEQOPjhH PopwCX73f0SDuF3bf+mLhaxzwOurwz0nczl5aI7N4dqBe0wKnqYkLjazpKC8xwH6xIOX sf/umB7VuziIeLbAMstgvaFDUVQsTqOt1OZ8dWXmrISRhnDKF0pdSIEnfv72xv/SklMh ZxEgcAjOY++Q7YZhfcKqkQud5rBQFj/3wF1rirnZ+6Qe2CbY0hV6S283tv62AkuIw1Od mSRwtSAPH0UjJiYUFR3JcXhnIFHDqXdhMf16IW2p8b4vTzCzdbEEhHid5LAdeflf+KCR XqJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sfcSfieW8Ddeo0hEC2vM6Cq6H+ydZkZrWTeso5fNmQk=; b=gPG47/E3gl2HwrYEGNIhTm3zjEQWz6NgCKC0AXwIm5cgrbj73S5CLJpv2EUN65KIku AyhgpimuecPrRsjOUaiDg3nGwYTDwFaJXXGbD2bo5CXKoCe2u/jmOOASUShA8/O2Ahen aBUhfiZkCkDNp28KpJq9q7SEn0rNBOWYQmU0bV3Zq2xYidTDXsS+S+xFzG5/20eSvpT1 P0YI931fN7g2KpP3Ixcz8Bg+/r9JzhftbhRhoby+5Ebd8uXYlY4Rusew3cHUjQpHsPfx g4ZyptlLrVdyKBclj3fqtHPu0qlKzEaR/c+EU5xgLqHgtaxyCS00lsWPdUTsU4XxSnAn cglA== X-Gm-Message-State: APjAAAVpDr70cHWH6fInbZfBVGjmy1D6PmWqD1Sk2vPxZmj3pJ5TVRkF qNbZU8St3d/ZIfloVKeItrb0jg== X-Google-Smtp-Source: APXvYqyHaUCmU9wzxmzfFh+DvZSO75ADUQZmZhzCng2eknOhjyNdb5gA8uEFjurqrD6+Do5L+d7Jiw== X-Received: by 2002:a7b:cc97:: with SMTP id p23mr867964wma.120.1559843177622; Thu, 06 Jun 2019 10:46:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:33 +0100 Message-Id: <20190606174609.20487-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 06/42] target/arm: Convert the VSEL instructions to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VSEL instructions to decodetree. We leave trans_VSEL() in translate.c for now as this allows the patch to show just the changes from the old handle_vsel(). In the old code the check for "do D16-D31 exist" was hidden in the VFP_DREG macro, and assumed that VFPv3 always implied that D16-D31 exist. In the new code we do the correct ID register test. This gives identical behaviour for most of our CPUs, and fixes previously incorrect handling for Cortex-R5F, Cortex-M4 and Cortex-M33, which all implement VFPv3 or better with only 16 double-precision registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/translate-vfp.inc.c | 9 +++++++++ target/arm/translate.c | 35 ++++++++++++++++++++++++---------- target/arm/vfp-uncond.decode | 19 ++++++++++++++++++ 4 files changed, 59 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c34207611ba..30fb107c605 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3408,6 +3408,12 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) +{ + /* Return true if D16-D31 are implemented */ + return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index cf3d7febaa7..f7535138d0f 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -129,3 +129,12 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) =20 return true; } + +/* + * The most usual kind of VFP access check, for everything except + * FMXR/FMRX to the always-available special registers. + */ +static bool vfp_access_check(DisasContext *s) +{ + return full_vfp_access_check(s, false); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 6088ffdc6ee..50545062195 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3076,10 +3076,27 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t r= m, - uint32_t dp) +static bool trans_VSEL(DisasContext *s, arg_VSEL *a) { - uint32_t cc =3D extract32(insn, 20, 2); + uint32_t rd, rn, rm; + bool dp =3D a->dp; + + if (!dc_isar_feature(aa32_vsel, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rn =3D a->vn; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } =20 if (dp) { TCGv_i64 frn, frm, dest; @@ -3101,7 +3118,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, =20 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (cc) { + switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, frn, frm); @@ -3148,7 +3165,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, dest =3D tcg_temp_new_i32(); tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (cc) { + switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm); @@ -3182,7 +3199,7 @@ static int handle_vsel(uint32_t insn, uint32_t rd, ui= nt32_t rn, uint32_t rm, tcg_temp_free_i32(zero); } =20 - return 0; + return true; } =20 static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn, @@ -3354,10 +3371,8 @@ static int disas_vfp_misc_insn(DisasContext *s, uint= 32_t insn) rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0f800e50) =3D=3D 0x0e000a00 && dc_isar_feature(aa32_vsel= , s)) { - return handle_vsel(insn, rd, rn, rm, dp); - } else if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && - dc_isar_feature(aa32_vminmaxnm, s)) { + if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && + dc_isar_feature(aa32_vminmaxnm, s)) { return handle_vminmaxnm(insn, rd, rn, rm, dp); } else if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && dc_isar_feature(aa32_vrint, s)) { diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index b1d9dc507c2..b7f7c27fe86 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -26,3 +26,22 @@ # 1111 1110 .... .... .... 101. .... .... # (but those patterns might also cover some Neon instructions, # which do not live in this file.) + +# VFP registers have an odd encoding with a four-bit field +# and a one-bit field which are assembled in different orders +# depending on whether the register is double or single precision. +# Each individual instruction function must do the checks for +# "double register selected but CPU does not have double support" +# and "double register number has bit 4 set but CPU does not +# support D16-D31" (which should UNDEF). +%vm_dp 5:1 0:4 +%vm_sp 0:4 5:1 +%vn_dp 7:1 16:4 +%vn_sp 16:4 7:1 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + +VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 +VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MfHjpfcV8rDRbagZf+maajLYmXP1fuWCMssnWt0JYC0=; b=yTg68OceOZ38PgiDkMW5TtwPXHzi65k/HC4f8vFpSstOQMU3uB75wWeANhx4ukGQ6e 7M1U48n8ZH29oHS2U1aRF4yuAbqPjzN7veq65Cxhq94CRMcaitGMm8vVpkNfpbijb1X6 ZxEPULqE1Kf36LgAhugozeyYEWYX/oXlHakwUUtdVGEhPrNpzo9P9YKFHDuwTM2pDD5+ IoIDbVqtRT0rBmnUVa88Dk5SQk/cui4LRD79p8HgJuTFLKnc+ptV8B2EvS0JquU+yEtH ke1ljXj385TQjdKVr4sA8vGe8JUlLh5PyVR903T4cZdABZrYOw3efCm98JG/pZCPShdW w5cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MfHjpfcV8rDRbagZf+maajLYmXP1fuWCMssnWt0JYC0=; b=HrDj6BlOJGZ59rUdYJdYhEDQtoF0FvG6OrgOYms1Uw+QLUR3A4oVn/V7OZIQIG4FdS Yb46220xV6W330e9eocXYU4qy9NlJhdTjLUptB2cnoyN0Z/EaZQdzRrKzsLsLAxuxK8f 2qNjLdCaNcV0rDdw7IaZKOTyjWZdBhRbidXWQnF95vKUzTb6dcR/7WeBPvyvE6tVxENU P4QIBXvK/c926D3H5NrJUJ58pnausEYT5MwyCbPtHjjG8mW/gia5HABI0JijD/HZkMPV D1f6cof//lpgmwKtc+bQYso6QZHDKronDMhWL8xJNx1xqi/6vv80Qeeei2w9ouo4TmnQ B9Sw== X-Gm-Message-State: APjAAAXo1gnbrz7HidAkdAhCFXz2rVETXZVAlxDlHkdbgyQHGluCnVoh W/S9Z1z84NQpSauYEDS368pFKA== X-Google-Smtp-Source: APXvYqzUmeifAIs1M30aJFuT1Z1qG8hKmTQQGjwFDCuTabautDZBCt698ME0MkGtcoCb/MDslw+ACA== X-Received: by 2002:adf:db12:: with SMTP id s18mr6005707wri.335.1559843179086; Thu, 06 Jun 2019 10:46:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:34 +0100 Message-Id: <20190606174609.20487-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 07/42] target/arm: Convert VMINNM, VMAXNM to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VMINNM and VMAXNM instructions to decodetree. As with VSEL, we leave the trans_VMINMAXNM() function in translate.c for the moment. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 41 ++++++++++++++++++++++++------------ target/arm/vfp-uncond.decode | 5 +++++ 2 files changed, 33 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 50545062195..312ec455c28 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3202,11 +3202,31 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return true; } =20 -static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn, - uint32_t rm, uint32_t dp) +static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) { - uint32_t vmin =3D extract32(insn, 6, 1); - TCGv_ptr fpst =3D get_fpstatus_ptr(0); + uint32_t rd, rn, rm; + bool dp =3D a->dp; + bool vmin =3D a->op; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rn =3D a->vn; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); =20 if (dp) { TCGv_i64 frn, frm, dest; @@ -3247,7 +3267,7 @@ static int handle_vminmaxnm(uint32_t insn, uint32_t r= d, uint32_t rn, } =20 tcg_temp_free_ptr(fpst); - return 0; + return true; } =20 static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t = dp, @@ -3359,23 +3379,18 @@ static const uint8_t fp_decode_rm[] =3D { =20 static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, dp =3D extract32(insn, 8, 1); + uint32_t rd, rm, dp =3D extract32(insn, 8, 1); =20 if (dp) { VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); VFP_DREG_M(rm, insn); } else { rd =3D VFP_SREG_D(insn); - rn =3D VFP_SREG_N(insn); rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0fb00e10) =3D=3D 0x0e800a00 && - dc_isar_feature(aa32_vminmaxnm, s)) { - return handle_vminmaxnm(insn, rd, rn, rm, dp); - } else if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && - dc_isar_feature(aa32_vrint, s)) { + if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && + dc_isar_feature(aa32_vrint, s)) { /* VRINTA, VRINTN, VRINTP, VRINTM */ int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; return handle_vrint(insn, rd, rm, dp, rounding); diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index b7f7c27fe86..8ab201fa058 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -45,3 +45,8 @@ VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 + +VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 +VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKYt9IdR9p04yclzZJ7NN0tuSnfOmYMB2x4KhMTCD0Y=; b=Xf1bqLviV2uyjpMBVugSD+hc5B7uuH338ROF0FBMDIuwPJ+MTKTyg8Lw/S/Sw5oyMu DE4eYYUaiQdhn00F7LIVnTUgyXIMD3Zza/Iob/bUrOyaehNrpdf4atTHVxRmcsm1+5qb nrkww3eBtg9fXLlbmZUVnSB78QoDAhgPseQMCtW5AcDXqmFS/zPurEaXZuaUiMkFazBB Awu5v6Irmdo3I7KwZpXFlIJ4Z1TVEVAmcKQ6KEwJRYBzUwOakyt9U9jIVw2bh5G3GgyB 5fa9eUaYxvOKg4bhVr/ID/zf+59BcUVUHd9FArT8lJsQ65/sPQpA24XN2XUVFnl6uD6c jPRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IKYt9IdR9p04yclzZJ7NN0tuSnfOmYMB2x4KhMTCD0Y=; b=cGoKAGTknV3Mel+abEJvSCvjlP+R5PAoKTL+XC5iV3Xj5pdyJN4/cLop2OU0vcSUhR TUgye7eZ9uL+HcecEOqZxSuzQE0K67U9USwesNrIZpKkhuyVOhD7u/uyYfKBeTouPLyr 3LYOQmeFCfvwIWOY01X6xeiiSRSAmI/S4+kzv4Dp9lMLXSKoovqPEiyhLBOb8ewQ0m2/ O4Fj3MBWh0QpLPS12jYtNn/sr0WnvitRf65P0Gn2PUGjLLzpRLF7ojQdSPQ8N86237Gn qf8utip5h1i22owvvrRWzlyIbInBRlI8rDjjWYnruddX9klqFsdzjH+OnNrZ6LYWCOXI iZsg== X-Gm-Message-State: APjAAAWNyQmYuyb5UKMBJEFKfxkfBZok/y0MDo16SUzPLWbpj/XnxQGQ AwTEjGSD8bGknqh8W0WlANpfoQ== X-Google-Smtp-Source: APXvYqwjaS1jA8UHMKkOo99Gq9IfwTwZhEJVkk2xDB3iaKFw8NSMJvcRJrrv5hsZSZ+f2R4GFQazkA== X-Received: by 2002:a7b:c189:: with SMTP id y9mr870188wmi.116.1559843180246; Thu, 06 Jun 2019 10:46:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:35 +0100 Message-Id: <20190606174609.20487-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree. Again, trans_VRINT() is temporarily left in translate.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++------------- target/arm/vfp-uncond.decode | 5 +++ 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 312ec455c28..91e3e3680b2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3270,11 +3270,43 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VM= INMAXNM *a) return true; } =20 -static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t = dp, - int rounding) +/* + * Table for converting the most common AArch32 encoding of + * rounding mode to arm_fprounding order (which matches the + * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). + */ +static const uint8_t fp_decode_rm[] =3D { + FPROUNDING_TIEAWAY, + FPROUNDING_TIEEVEN, + FPROUNDING_POSINF, + FPROUNDING_NEGINF, +}; + +static bool trans_VRINT(DisasContext *s, arg_VRINT *a) { - TCGv_ptr fpst =3D get_fpstatus_ptr(0); + uint32_t rd, rm; + bool dp =3D a->dp; + TCGv_ptr fpst; TCGv_i32 tcg_rmode; + int rounding =3D fp_decode_rm[a->rm]; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -3305,7 +3337,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_ptr(fpst); - return 0; + return true; } =20 static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t d= p, @@ -3366,17 +3398,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, return 0; } =20 -/* Table for converting the most common AArch32 encoding of - * rounding mode to arm_fprounding order (which matches the - * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). - */ -static const uint8_t fp_decode_rm[] =3D { - FPROUNDING_TIEAWAY, - FPROUNDING_TIEEVEN, - FPROUNDING_POSINF, - FPROUNDING_NEGINF, -}; - static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) { uint32_t rd, rm, dp =3D extract32(insn, 8, 1); @@ -3389,13 +3410,8 @@ static int disas_vfp_misc_insn(DisasContext *s, uint= 32_t insn) rm =3D VFP_SREG_M(insn); } =20 - if ((insn & 0x0fbc0ed0) =3D=3D 0x0eb80a40 && - dc_isar_feature(aa32_vrint, s)) { - /* VRINTA, VRINTN, VRINTP, VRINTM */ - int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; - return handle_vrint(insn, rd, rm, dp, rounding); - } else if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && - dc_isar_feature(aa32_vcvt_dr, s)) { + if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && + dc_isar_feature(aa32_vcvt_dr, s)) { /* VCVTA, VCVTN, VCVTP, VCVTM */ int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; return handle_vcvt(insn, rd, rm, dp, rounding); diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 8ab201fa058..0aa83285de2 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -50,3 +50,8 @@ VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 + +VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ + vm=3D%vm_sp vd=3D%vd_sp dp=3D0 +VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ + vm=3D%vm_dp vd=3D%vd_dp dp=3D1 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree. trans_VCVT() is temporarily left in translate.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 72 +++++++++++++++++------------------- target/arm/vfp-uncond.decode | 6 +++ 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 91e3e3680b2..2cf8fd99404 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3340,12 +3340,31 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT = *a) return true; } =20 -static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t d= p, - int rounding) +static bool trans_VCVT(DisasContext *s, arg_VCVT *a) { - bool is_signed =3D extract32(insn, 7, 1); - TCGv_ptr fpst =3D get_fpstatus_ptr(0); + uint32_t rd, rm; + bool dp =3D a->dp; + TCGv_ptr fpst; TCGv_i32 tcg_rmode, tcg_shift; + int rounding =3D fp_decode_rm[a->rm]; + bool is_signed =3D a->op; + + if (!dc_isar_feature(aa32_vcvt_dr, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + rd =3D a->vd; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); =20 tcg_shift =3D tcg_const_i32(0); =20 @@ -3355,10 +3374,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, if (dp) { TCGv_i64 tcg_double, tcg_res; TCGv_i32 tcg_tmp; - /* Rd is encoded as a single precision register even when the sour= ce - * is double precision. - */ - rd =3D ((rd << 1) & 0x1e) | ((rd >> 4) & 0x1); tcg_double =3D tcg_temp_new_i64(); tcg_res =3D tcg_temp_new_i64(); tcg_tmp =3D tcg_temp_new_i32(); @@ -3395,28 +3410,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, =20 tcg_temp_free_ptr(fpst); =20 - return 0; -} - -static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) -{ - uint32_t rd, rm, dp =3D extract32(insn, 8, 1); - - if (dp) { - VFP_DREG_D(rd, insn); - VFP_DREG_M(rm, insn); - } else { - rd =3D VFP_SREG_D(insn); - rm =3D VFP_SREG_M(insn); - } - - if ((insn & 0x0fbc0e50) =3D=3D 0x0ebc0a40 && - dc_isar_feature(aa32_vcvt_dr, s)) { - /* VCVTA, VCVTN, VCVTP, VCVTM */ - int rounding =3D fp_decode_rm[extract32(insn, 16, 2)]; - return handle_vcvt(insn, rd, rm, dp, rounding); - } - return 1; + return true; } =20 /* @@ -3452,6 +3446,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) } } =20 + if (extract32(insn, 28, 4) =3D=3D 0xf) { + /* + * Encodings with T=3D1 (Thumb) or unconditional (ARM): these + * were all handled by the decodetree decoder, so any insn + * patterns which get here must be UNDEF. + */ + return 1; + } + /* * FIXME: this access check should not take precedence over UNDEF * for invalid encodings; we will generate incorrect syndrome informat= ion @@ -3468,15 +3471,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) return 0; } =20 - if (extract32(insn, 28, 4) =3D=3D 0xf) { - /* - * Encodings with T=3D1 (Thumb) or unconditional (ARM): - * only used for the "miscellaneous VFP features" added in v8A - * and v7M (and gated on the MVFR2.FPMisc field). - */ - return disas_vfp_misc_insn(s, insn); - } - dp =3D ((insn & 0xf00) =3D=3D 0xb00); switch ((insn >> 24) & 0xf) { case 0xe: diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 0aa83285de2..5af1f2ee664 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -55,3 +55,9 @@ VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ vm=3D%vm_sp vd=3D%vd_sp dp=3D0 VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ vm=3D%vm_dp vd=3D%vd_dp dp=3D1 + +# VCVT float to int with specified rounding mode; Vd is always single-prec= ision +VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ + vm=3D%vm_sp vd=3D%vd_sp dp=3D0 +VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ + vm=3D%vm_dp vd=3D%vd_sp dp=3D1 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559843767; cv=none; d=zoho.com; s=zohoarc; b=jsZhXyzIj87u6ABn3g9BE5o6yJos9RE6PXvCMHYlcFBc/03ir6E9s1t7sEnKHH8sHW8byR0UW7KdATW6NJnCpf+doC2ErxflohAaNYzk7EWv6B14Ab5xAkdeADhpwFRufrkF3ZP2JajZIVJJcpdV2CDuqFPnUeivZ0IbcskoO4o= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UGVcH6sTteiHDcjJBr1jYE8bG2UG4UEyZfFmVaer4Is=; b=zj0gt/M5Yh8lPRCCaoEmD4iNVjGV5/YDdjOuUO0kytFgfZo2sH/VlFV028cXWaLz/k lecknrakCfEPBQPeT09BXaA+XSpnaJxCyy8dJTVnkVIasjUP8lzdF3wK6RAwbEh+2Evv qIjt8PF+gecKg9sg7DZSAOnSP4B85LyJxGyD57InQk4fUkwlTfse6pCcIOd9lDt1I1Jl gcDEUboB5f/IMKkE3zv09eRPKYXt4Cem8CfiGJ//iuHnBUKlTghIrjilpYriOGFAVAtk PrKXLzRTlG3AEA/duvs1S7k4F5q/3mCj+HzkltUO8ldUMm/qxPGxwyHxGo4t/CIoiHk9 zFLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UGVcH6sTteiHDcjJBr1jYE8bG2UG4UEyZfFmVaer4Is=; b=mFb9GcTLQ99UMmjfc7Qmpxnms77cWmt4N2kx02juwCLmhdTUeqBC4GrL4+zUDbTqV0 U8k3OvdbD0YDNjNTg2f3Xo+MgF+FuTaaZpIlNzN2s8VvRTZvK4KBN2DE4mtMUgLIYsNQ P2OlV56Ri2Qt4N11VkC4uh/UWDclB5P+fbLNQWUoelxxHFwNIO+vXbXgtiY/x+xgPHx7 iRC+TY41PoHngv8iq/MLIJsCbJOy0ShICAGvU8z6wl+ST72z2XcqdNmp/NRnSW707d0L jqXW1gAQJBbgAlsq0ZzrzgO94EX7OsRKbExp3rlk/rQ20Yx5xuQbyiZwjUmgQwKqVeW9 GTyA== X-Gm-Message-State: APjAAAXPTifnSmhGf05i2/FwvVZE8mirPRHkr85ielA3FvWJYpU6emB5 n2NyA6f8c3bnWT/LRdRGRu9QNQ== X-Google-Smtp-Source: APXvYqxb3ZWmgxh2KbJMWlxiaC1sbYF85AK3xtV5HyeCNC1jsd0lzGm9oqWtfw/Jxv1qR8gEhQq/Tg== X-Received: by 2002:a1c:b4d4:: with SMTP id d203mr905782wmf.34.1559843182806; Thu, 06 Jun 2019 10:46:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:37 +0100 Message-Id: <20190606174609.20487-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 10/42] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 337 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 337 --------------------------------- 2 files changed, 337 insertions(+), 337 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f7535138d0f..2f070a6e0d9 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -138,3 +138,340 @@ static bool vfp_access_check(DisasContext *s) { return full_vfp_access_check(s, false); } + +static bool trans_VSEL(DisasContext *s, arg_VSEL *a) +{ + uint32_t rd, rn, rm; + bool dp =3D a->dp; + + if (!dc_isar_feature(aa32_vsel, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rn =3D a->vn; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + if (dp) { + TCGv_i64 frn, frm, dest; + TCGv_i64 tmp, zero, zf, nf, vf; + + zero =3D tcg_const_i64(0); + + frn =3D tcg_temp_new_i64(); + frm =3D tcg_temp_new_i64(); + dest =3D tcg_temp_new_i64(); + + zf =3D tcg_temp_new_i64(); + nf =3D tcg_temp_new_i64(); + vf =3D tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(zf, cpu_ZF); + tcg_gen_ext_i32_i64(nf, cpu_NF); + tcg_gen_ext_i32_i64(vf, cpu_VF); + + tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + switch (a->cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, + frn, frm); + break; + case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ + tmp =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i64(tmp); + break; + case 3: /* gt: !Z && N =3D=3D V */ + tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, + frn, frm); + tmp =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i64(tmp); + break; + } + tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(frn); + tcg_temp_free_i64(frm); + tcg_temp_free_i64(dest); + + tcg_temp_free_i64(zf); + tcg_temp_free_i64(nf); + tcg_temp_free_i64(vf); + + tcg_temp_free_i64(zero); + } else { + TCGv_i32 frn, frm, dest; + TCGv_i32 tmp, zero; + + zero =3D tcg_const_i32(0); + + frn =3D tcg_temp_new_i32(); + frm =3D tcg_temp_new_i32(); + dest =3D tcg_temp_new_i32(); + tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + switch (a->cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, + frn, frm); + break; + case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ + tmp =3D tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N =3D=3D V */ + tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, + frn, frm); + tmp =3D tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i32(tmp); + break; + } + tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(frn); + tcg_temp_free_i32(frm); + tcg_temp_free_i32(dest); + + tcg_temp_free_i32(zero); + } + + return true; +} + +static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) +{ + uint32_t rd, rn, rm; + bool dp =3D a->dp; + bool vmin =3D a->op; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rn =3D a->vn; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); + + if (dp) { + TCGv_i64 frn, frm, dest; + + frn =3D tcg_temp_new_i64(); + frm =3D tcg_temp_new_i64(); + dest =3D tcg_temp_new_i64(); + + tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + if (vmin) { + gen_helper_vfp_minnumd(dest, frn, frm, fpst); + } else { + gen_helper_vfp_maxnumd(dest, frn, frm, fpst); + } + tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(frn); + tcg_temp_free_i64(frm); + tcg_temp_free_i64(dest); + } else { + TCGv_i32 frn, frm, dest; + + frn =3D tcg_temp_new_i32(); + frm =3D tcg_temp_new_i32(); + dest =3D tcg_temp_new_i32(); + + tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + if (vmin) { + gen_helper_vfp_minnums(dest, frn, frm, fpst); + } else { + gen_helper_vfp_maxnums(dest, frn, frm, fpst); + } + tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(frn); + tcg_temp_free_i32(frm); + tcg_temp_free_i32(dest); + } + + tcg_temp_free_ptr(fpst); + return true; +} + +/* + * Table for converting the most common AArch32 encoding of + * rounding mode to arm_fprounding order (which matches the + * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). + */ +static const uint8_t fp_decode_rm[] =3D { + FPROUNDING_TIEAWAY, + FPROUNDING_TIEEVEN, + FPROUNDING_POSINF, + FPROUNDING_NEGINF, +}; + +static bool trans_VRINT(DisasContext *s, arg_VRINT *a) +{ + uint32_t rd, rm; + bool dp =3D a->dp; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode; + int rounding =3D fp_decode_rm[a->rm]; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && + ((a->vm | a->vd) & 0x10)) { + return false; + } + rd =3D a->vd; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); + + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + + if (dp) { + TCGv_i64 tcg_op; + TCGv_i64 tcg_res; + tcg_op =3D tcg_temp_new_i64(); + tcg_res =3D tcg_temp_new_i64(); + tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + gen_helper_rintd(tcg_res, tcg_op, fpst); + tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(tcg_op); + tcg_temp_free_i64(tcg_res); + } else { + TCGv_i32 tcg_op; + TCGv_i32 tcg_res; + tcg_op =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + gen_helper_rints(tcg_res, tcg_op, fpst); + tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(tcg_op); + tcg_temp_free_i32(tcg_res); + } + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT(DisasContext *s, arg_VCVT *a) +{ + uint32_t rd, rm; + bool dp =3D a->dp; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode, tcg_shift; + int rounding =3D fp_decode_rm[a->rm]; + bool is_signed =3D a->op; + + if (!dc_isar_feature(aa32_vcvt_dr, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + rd =3D a->vd; + rm =3D a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(0); + + tcg_shift =3D tcg_const_i32(0); + + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + + if (dp) { + TCGv_i64 tcg_double, tcg_res; + TCGv_i32 tcg_tmp; + tcg_double =3D tcg_temp_new_i64(); + tcg_res =3D tcg_temp_new_i64(); + tcg_tmp =3D tcg_temp_new_i32(); + tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm)); + if (is_signed) { + gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); + } else { + gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); + } + tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); + tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd)); + tcg_temp_free_i32(tcg_tmp); + tcg_temp_free_i64(tcg_res); + tcg_temp_free_i64(tcg_double); + } else { + TCGv_i32 tcg_single, tcg_res; + tcg_single =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm)); + if (is_signed) { + gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); + } else { + gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); + } + tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd)); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_single); + } + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + + tcg_temp_free_i32(tcg_shift); + + tcg_temp_free_ptr(fpst); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 2cf8fd99404..dc22b2aa7ff 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3076,343 +3076,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -static bool trans_VSEL(DisasContext *s, arg_VSEL *a) -{ - uint32_t rd, rn, rm; - bool dp =3D a->dp; - - if (!dc_isar_feature(aa32_vsel, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - rd =3D a->vd; - rn =3D a->vn; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - if (dp) { - TCGv_i64 frn, frm, dest; - TCGv_i64 tmp, zero, zf, nf, vf; - - zero =3D tcg_const_i64(0); - - frn =3D tcg_temp_new_i64(); - frm =3D tcg_temp_new_i64(); - dest =3D tcg_temp_new_i64(); - - zf =3D tcg_temp_new_i64(); - nf =3D tcg_temp_new_i64(); - vf =3D tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(zf, cpu_ZF); - tcg_gen_ext_i32_i64(nf, cpu_NF); - tcg_gen_ext_i32_i64(vf, cpu_VF); - - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (a->cc) { - case 0: /* eq: Z */ - tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, - frn, frm); - break; - case 1: /* vs: V */ - tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, - frn, frm); - break; - case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ - tmp =3D tcg_temp_new_i64(); - tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - frn, frm); - tcg_temp_free_i64(tmp); - break; - case 3: /* gt: !Z && N =3D=3D V */ - tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, - frn, frm); - tmp =3D tcg_temp_new_i64(); - tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - dest, frm); - tcg_temp_free_i64(tmp); - break; - } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - - tcg_temp_free_i64(zf); - tcg_temp_free_i64(nf); - tcg_temp_free_i64(vf); - - tcg_temp_free_i64(zero); - } else { - TCGv_i32 frn, frm, dest; - TCGv_i32 tmp, zero; - - zero =3D tcg_const_i32(0); - - frn =3D tcg_temp_new_i32(); - frm =3D tcg_temp_new_i32(); - dest =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); - switch (a->cc) { - case 0: /* eq: Z */ - tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, - frn, frm); - break; - case 1: /* vs: V */ - tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, - frn, frm); - break; - case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - frn, frm); - tcg_temp_free_i32(tmp); - break; - case 3: /* gt: !Z && N =3D=3D V */ - tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, - frn, frm); - tmp =3D tcg_temp_new_i32(); - tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - dest, frm); - tcg_temp_free_i32(tmp); - break; - } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - - tcg_temp_free_i32(zero); - } - - return true; -} - -static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) -{ - uint32_t rd, rn, rm; - bool dp =3D a->dp; - bool vmin =3D a->op; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - rd =3D a->vd; - rn =3D a->vn; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - if (dp) { - TCGv_i64 frn, frm, dest; - - frn =3D tcg_temp_new_i64(); - frm =3D tcg_temp_new_i64(); - dest =3D tcg_temp_new_i64(); - - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); - if (vmin) { - gen_helper_vfp_minnumd(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnumd(dest, frn, frm, fpst); - } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - } else { - TCGv_i32 frn, frm, dest; - - frn =3D tcg_temp_new_i32(); - frm =3D tcg_temp_new_i32(); - dest =3D tcg_temp_new_i32(); - - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); - if (vmin) { - gen_helper_vfp_minnums(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnums(dest, frn, frm, fpst); - } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - } - - tcg_temp_free_ptr(fpst); - return true; -} - -/* - * Table for converting the most common AArch32 encoding of - * rounding mode to arm_fprounding order (which matches the - * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). - */ -static const uint8_t fp_decode_rm[] =3D { - FPROUNDING_TIEAWAY, - FPROUNDING_TIEEVEN, - FPROUNDING_POSINF, - FPROUNDING_NEGINF, -}; - -static bool trans_VRINT(DisasContext *s, arg_VRINT *a) -{ - uint32_t rd, rm; - bool dp =3D a->dp; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode; - int rounding =3D fp_decode_rm[a->rm]; - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && - ((a->vm | a->vd) & 0x10)) { - return false; - } - rd =3D a->vd; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - - if (dp) { - TCGv_i64 tcg_op; - TCGv_i64 tcg_res; - tcg_op =3D tcg_temp_new_i64(); - tcg_res =3D tcg_temp_new_i64(); - tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); - gen_helper_rintd(tcg_res, tcg_op, fpst); - tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i64(tcg_op); - tcg_temp_free_i64(tcg_res); - } else { - TCGv_i32 tcg_op; - TCGv_i32 tcg_res; - tcg_op =3D tcg_temp_new_i32(); - tcg_res =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); - gen_helper_rints(tcg_res, tcg_op, fpst); - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); - } - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT(DisasContext *s, arg_VCVT *a) -{ - uint32_t rd, rm; - bool dp =3D a->dp; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode, tcg_shift; - int rounding =3D fp_decode_rm[a->rm]; - bool is_signed =3D a->op; - - if (!dc_isar_feature(aa32_vcvt_dr, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { - return false; - } - rd =3D a->vd; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - tcg_shift =3D tcg_const_i32(0); - - tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - - if (dp) { - TCGv_i64 tcg_double, tcg_res; - TCGv_i32 tcg_tmp; - tcg_double =3D tcg_temp_new_i64(); - tcg_res =3D tcg_temp_new_i64(); - tcg_tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm)); - if (is_signed) { - gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); - } else { - gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); - } - tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); - tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd)); - tcg_temp_free_i32(tcg_tmp); - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single, tcg_res; - tcg_single =3D tcg_temp_new_i32(); - tcg_res =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm)); - if (is_signed) { - gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); - } else { - gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); - } - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd)); - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_single); - } - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_i32(tcg_shift); - - tcg_temp_free_ptr(fpst); - - return true; -} - /* * Disassemble a VFP instruction. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NNiCFMrjCFikPCgvnRabtH7il5+OhUKvQr2Zj2YGfq0=; b=PNsPErVK1U1A9GzU6jPuzYMf02QpyUrpNpXL2vyTTuPdbbKffpBEPFjWUxTIJr4+Wx oVIwqvoe/F4tGCbHeehvKB+MfyfSvJEcNsswpuMABbsPvPBSJq0jLgUpnoGyppI7bDvy QSjY5hlpeH027ByqE2fjNp85WrKE6Dn36n6n6oNk4h2ljZRyoeHS1VnRyUJV+vOxZmoU oWEzw4zvc9tabmo6zCq64A6Dyvy9USVohcWIVoHFT3KT0vkUt/E0moe2GPb2jN7nRbvi sLQQrkb4LRPZmWl0yT5hnbg5giUidIKr1YUodpx/wIKxosfozH7F5Id7GMwKGVELYXNp MiQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NNiCFMrjCFikPCgvnRabtH7il5+OhUKvQr2Zj2YGfq0=; b=PiRl2FfnAeFgCZwntSAZ5VCIqyytQYpf1SoDjl46DCk/ryxU46HIBUq+ZgcgQRZzrX TFn/mRQZBl75Cj6nsqD4DpQcBvBbxF3dRUklGPz09JIumpirwhwnI/g/zXSTLrSJhKm8 DloJGRyXYkCCrp9+i1pb/GCofDAOka1b9/2rBU4JxSc5PAnzZwNKJzJuwd7UG5jgmaj+ Nlq4rh9qsQLZtYpYK205aIcNwvbkNgkMoMPHD4vaEPhoJeB2ANSjSYiTm/4Wl2O0NyUp C8s+FXIeb5QDT0nkq6iqjfZhUY0rbnbtej1cGmC6AgmkVBmuDWmj07ROEmV1WjNGV8pO z5ng== X-Gm-Message-State: APjAAAVM4111vaJ+m+dcM2iMPSWCjsAQ/BcT/EjU9/Tfb3/b3hROXfIl rO+QIITS9NOo6lYodqF/TMjS9sY2vUziKA== X-Google-Smtp-Source: APXvYqwQXaqXRSgkPeu+lwMjx9RoCspS2m9SNqNfPqTo3zvFFoGDAuMtVP7I3xnFSI4uZSZleSaKkQ== X-Received: by 2002:adf:a11d:: with SMTP id o29mr2086212wro.262.1559843183868; Thu, 06 Jun 2019 10:46:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:38 +0100 Message-Id: <20190606174609.20487-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 11/42] target/arm: Add helpers for VFP register loads and stores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- target/arm/translate.c | 10 +++++++++ 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 2f070a6e0d9..24358f3d3eb 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -179,8 +179,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_gen_ext_i32_i64(nf, cpu_NF); tcg_gen_ext_i32_i64(vf, cpu_VF); =20 - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(frn, rn); + neon_load_reg64(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, @@ -207,7 +207,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i64(tmp); break; } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(dest, rd); tcg_temp_free_i64(frn); tcg_temp_free_i64(frm); tcg_temp_free_i64(dest); @@ -226,8 +226,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) frn =3D tcg_temp_new_i32(); frm =3D tcg_temp_new_i32(); dest =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(frn, rn); + neon_load_reg32(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, @@ -254,7 +254,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i32(tmp); break; } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(dest, rd); tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); @@ -298,14 +298,14 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) frm =3D tcg_temp_new_i64(); dest =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(frn, rn); + neon_load_reg64(frm, rm); if (vmin) { gen_helper_vfp_minnumd(dest, frn, frm, fpst); } else { gen_helper_vfp_maxnumd(dest, frn, frm, fpst); } - tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(dest, rd); tcg_temp_free_i64(frn); tcg_temp_free_i64(frm); tcg_temp_free_i64(dest); @@ -316,14 +316,14 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) frm =3D tcg_temp_new_i32(); dest =3D tcg_temp_new_i32(); =20 - tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); - tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(frn, rn); + neon_load_reg32(frm, rm); if (vmin) { gen_helper_vfp_minnums(dest, frn, frm, fpst); } else { gen_helper_vfp_maxnums(dest, frn, frm, fpst); } - tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(dest, rd); tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); @@ -379,9 +379,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i64 tcg_res; tcg_op =3D tcg_temp_new_i64(); tcg_res =3D tcg_temp_new_i64(); - tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg64(tcg_op, rm); gen_helper_rintd(tcg_res, tcg_op, fpst); - tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg64(tcg_res, rd); tcg_temp_free_i64(tcg_op); tcg_temp_free_i64(tcg_res); } else { @@ -389,9 +389,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i32 tcg_res; tcg_op =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm)); + neon_load_reg32(tcg_op, rm); gen_helper_rints(tcg_res, tcg_op, fpst); - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd)); + neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_op); tcg_temp_free_i32(tcg_res); } @@ -440,14 +440,14 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) tcg_double =3D tcg_temp_new_i64(); tcg_res =3D tcg_temp_new_i64(); tcg_tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm)); + neon_load_reg64(tcg_double, rm); if (is_signed) { gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); } else { gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); } tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); - tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd)); + neon_store_reg32(tcg_tmp, rd); tcg_temp_free_i32(tcg_tmp); tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_double); @@ -455,13 +455,13 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) TCGv_i32 tcg_single, tcg_res; tcg_single =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm)); + neon_load_reg32(tcg_single, rm); if (is_signed) { gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); } else { gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); } - tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd)); + neon_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_single); } diff --git a/target/arm/translate.c b/target/arm/translate.c index dc22b2aa7ff..fd2abd87202 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1689,6 +1689,16 @@ static inline void neon_store_reg64(TCGv_i64 var, in= t reg) tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); } =20 +static inline void neon_load_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + +static inline void neon_store_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + static TCGv_ptr vfp_reg_ptr(bool dp, int reg) { TCGv_ptr ret =3D tcg_temp_new_ptr(); --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844024; cv=none; d=zoho.com; s=zohoarc; b=Nerry7mk1UrkssvD+NjvUQlbQ0EK0iDKPK+jrfswVawEZexXxCNk9fMXX+vCSI1TflzUJjjvzXML4Ji1MJIiKzvfIwaLtOPiE4iwkOVMKPtALx2RTsCCtjQIwDtPWe1sbQrIsxM+2Exgjwv2EYVlvLIjJJyayDVAh2iaKFFPcUE= ARC-Message-Signature: i=1; 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X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PATCH 12/42] target/arm: Convert "double-precision" register moves to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 =3D=3D 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 =3D=3D 0x10 * VDUP with B:E =3D=3D 11 * VDUP with Q =3D=3D 1 and Vn<0> =3D=3D 1 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. --- target/arm/translate-vfp.inc.c | 147 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 83 +------------------ target/arm/vfp.decode | 36 ++++++++ 3 files changed, 185 insertions(+), 81 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 24358f3d3eb..8b0899fa05c 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -475,3 +475,150 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) =20 return true; } + +static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) +{ + /* VMOV scalar to general purpose register */ + TCGv_i32 tmp; + int pass; + uint32_t offset; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + offset =3D a->index << a->size; + pass =3D extract32(offset, 2, 1); + offset =3D extract32(offset, 0, 2) * 8; + + if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D neon_load_reg(a->vn, pass); + switch (a->size) { + case 0: + if (offset) { + tcg_gen_shri_i32(tmp, tmp, offset); + } + if (a->u) { + gen_uxtb(tmp); + } else { + gen_sxtb(tmp); + } + break; + case 1: + if (a->u) { + if (offset) { + tcg_gen_shri_i32(tmp, tmp, 16); + } else { + gen_uxth(tmp); + } + } else { + if (offset) { + tcg_gen_sari_i32(tmp, tmp, 16); + } else { + gen_sxth(tmp); + } + } + break; + case 2: + break; + } + store_reg(s, a->rt, tmp); + + return true; +} + +static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) +{ + /* VMOV general purpose register to scalar */ + TCGv_i32 tmp, tmp2; + int pass; + uint32_t offset; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + offset =3D a->index << a->size; + pass =3D extract32(offset, 2, 1); + offset =3D extract32(offset, 0, 2) * 8; + + if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D load_reg(s, a->rt); + switch (a->size) { + case 0: + tmp2 =3D neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); + tcg_temp_free_i32(tmp2); + break; + case 1: + tmp2 =3D neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); + tcg_temp_free_i32(tmp2); + break; + case 2: + break; + } + neon_store_reg(a->vn, pass, tmp); + + return true; +} + +static bool trans_VDUP(DisasContext *s, arg_VDUP *a) +{ + /* VDUP (general purpose register) */ + TCGv_i32 tmp; + int size, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + return false; + } + + if (a->b && a->e) { + return false; + } + + if (a->q && (a->vn & 1)) { + return false; + } + + vec_size =3D a->q ? 16 : 8; + if (a->b) { + size =3D 0; + } else if (a->e) { + size =3D 1; + } else { + size =3D 2; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D load_reg(s, a->rt); + tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + vec_size, vec_size, tmp); + tcg_temp_free_i32(tmp); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index fd2abd87202..ff9c6a43d84 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3151,87 +3151,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) /* single register transfer */ rd =3D (insn >> 12) & 0xf; if (dp) { - int size; - int pass; - - VFP_DREG_N(rn, insn); - if (insn & 0xf) - return 1; - if (insn & 0x00c00060 - && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return 1; - } - - pass =3D (insn >> 21) & 1; - if (insn & (1 << 22)) { - size =3D 0; - offset =3D ((insn >> 5) & 3) * 8; - } else if (insn & (1 << 5)) { - size =3D 1; - offset =3D (insn & (1 << 6)) ? 16 : 0; - } else { - size =3D 2; - offset =3D 0; - } - if (insn & ARM_CP_RW_BIT) { - /* vfp->arm */ - tmp =3D neon_load_reg(rn, pass); - switch (size) { - case 0: - if (offset) - tcg_gen_shri_i32(tmp, tmp, offset); - if (insn & (1 << 23)) - gen_uxtb(tmp); - else - gen_sxtb(tmp); - break; - case 1: - if (insn & (1 << 23)) { - if (offset) { - tcg_gen_shri_i32(tmp, tmp, 16); - } else { - gen_uxth(tmp); - } - } else { - if (offset) { - tcg_gen_sari_i32(tmp, tmp, 16); - } else { - gen_sxth(tmp); - } - } - break; - case 2: - break; - } - store_reg(s, rd, tmp); - } else { - /* arm->vfp */ - tmp =3D load_reg(s, rd); - if (insn & (1 << 23)) { - /* VDUP */ - int vec_size =3D pass ? 16 : 8; - tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0), - vec_size, vec_size, tmp); - tcg_temp_free_i32(tmp); - } else { - /* VMOV */ - switch (size) { - case 0: - tmp2 =3D neon_load_reg(rn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); - tcg_temp_free_i32(tmp2); - break; - case 1: - tmp2 =3D neon_load_reg(rn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16= ); - tcg_temp_free_i32(tmp2); - break; - case 2: - break; - } - neon_store_reg(rn, pass, tmp); - } - } + /* already handled by decodetree */ + return 1; } else { /* !dp */ bool is_sysreg; =20 diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 28ee664d8c3..8286bdc0729 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -26,3 +26,39 @@ # 1110 1110 .... .... .... 101. .... .... # (but those patterns might also cover some Neon instructions, # which do not live in this file.) + +# VFP registers have an odd encoding with a four-bit field +# and a one-bit field which are assembled in different orders +# depending on whether the register is double or single precision. +# Each individual instruction function must do the checks for +# "double register selected but CPU does not have double support" +# and "double register number has bit 4 set but CPU does not +# support D16-D31" (which should UNDEF). +%vm_dp 5:1 0:4 +%vm_sp 0:4 5:1 +%vn_dp 7:1 16:4 +%vn_sp 16:4 7:1 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + +%vmov_idx_b 21:1 5:2 +%vmov_idx_h 21:1 6:1 + +# VMOV scalar to general-purpose register; note that this does +# include some Neon cases. +VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ + vn=3D%vn_dp size=3D0 index=3D%vmov_idx_b +VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \ + vn=3D%vn_dp size=3D1 index=3D%vmov_idx_h +VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \ + vn=3D%vn_dp size=3D2 u=3D0 + +VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \ + vn=3D%vn_dp size=3D0 index=3D%vmov_idx_b +VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \ + vn=3D%vn_dp size=3D1 index=3D%vmov_idx_h +VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \ + vn=3D%vn_dp size=3D2 + +VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ + vn=3D%vn_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559845153; cv=none; d=zoho.com; s=zohoarc; b=b0e8Y9o6o5ZD2iHkAJ+AiIcVmBhgDVzHKqCkZCzw+kuB8nn7vnm4eUkFiX6S6GrT4jDLgKlxXzFkKDLkuFfPC7YSp8JQNqS3NJmsS6Re4Eh1tCaKUYgoK4XTXoDmwETdf6Wo6wrrzyzpqQWZ0X4KJJgFszrAscQp2W1k8KRJGQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559845153; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Oys2pmEwthhvLTKh87xxlHkMEmLQ8kuIT4y6ZbF9A9o=; b=RO3I/gr2YmD1W60l+5CNTA5qKpaz5gZUUYdAF7lNhIjFQiEGR6X84Vf5fi76CuXACmU6r+TyDzWosSi8JtTyQ8UnGE/7eNnjcQubwAlj4HMG0kCiqBFJUMDJiPHZ/8UO8HcLwnVvDvyulncK+WZ/FdOiKihW4Tv4Hkm2HT5J8rc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155984515362444.363787387140405; Thu, 6 Jun 2019 11:19:13 -0700 (PDT) Received: from localhost ([127.0.0.1]:36437 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwyl-00029a-Ud for importer@patchew.org; Thu, 06 Jun 2019 14:19:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwUE-0004e3-CY for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU8-0004Er-A3 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:38 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40098) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU7-0002xe-OQ for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:32 -0400 Received: by mail-wr1-x444.google.com with SMTP id p11so3332834wre.7 for ; Thu, 06 Jun 2019 10:46:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oys2pmEwthhvLTKh87xxlHkMEmLQ8kuIT4y6ZbF9A9o=; b=rQXq/pPzKk6lpkJ675D2B4sG0B6tT8vQWkodAI3aqDNT87W02H8GYhP5PdhvuF9GxI 0JFYrX3dE7jIGiDkEQWuNKLHhBF+IRd19dWAnnn4d+apM8m2aTeSibSjsV5Cz/+MCUVz vww4UuIX2cJhgVwOsWmLAs5/mnbqFcYkH1Jk9u5z/7inaOuo3qW8sRwAS0lQbMtdP17e 06mxYwQj5KmBuvCZKVwiBz2W9Cxqr0UnlQ989TusColjFh3daQfqFUQoysnXh2QMLj+3 Q8ijiWfJNejTubOoJxHRAthOCEQ6NH6GRl9mOVdGInM7WaI3NFDr5Vn7cvM5IPae1Dyk bubA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oys2pmEwthhvLTKh87xxlHkMEmLQ8kuIT4y6ZbF9A9o=; b=cwj2EPDXD6Q4kKjdRxf7xnY597Le9QmLU0rbeSyVJ2S3FgFgB9/7uBG/DLe3vORlCq +SFHBjebY89qTfFhRUKAH4mRC0Pw7ldRocefbIG/dt3Gas29az4278eWZY2H+NtdT2mq 0agHVaUy4wX/0u7ukwOdd27e4tYTW7a3NUnOo0QcDNaCzCRahtWte/eSsIzhkaoatK/x 1HuZtVQVBSi+mrZnt1V+soh004mI2gHi5XDTH9Y3DhahIT7xVa8SzpkN3nvJ0u4P/Px6 Cpktzq9tg7cNhxKy7yLUAxRnny7mv/4P3ZAfii/nYMt/NGzCVTrl2lB01GiQULTmVa3U 4KzA== X-Gm-Message-State: APjAAAX958H/LQW2NZWz+juYqpBjScftOiyfM4hddbbLqz8a59zDcR0X Ru4+99w+Euo4di7FGto35Ef20A== X-Google-Smtp-Source: APXvYqx03sq03pfxYB2fzNTEGul8dAwnbN0HJvgr5XtdVEqpplegZdvs1wcb380VKy7xdEbXYj/m6w== X-Received: by 2002:a5d:4a0b:: with SMTP id m11mr21175588wrq.251.1559843186128; Thu, 06 Jun 2019 10:46:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:40 +0100 Message-Id: <20190606174609.20487-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 161 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 148 +----------------------------- target/arm/vfp.decode | 4 + 3 files changed, 168 insertions(+), 145 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8b0899fa05c..74c10f9024b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -622,3 +622,164 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) =20 return true; } + +static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) +{ + TCGv_i32 tmp; + bool ignore_vfp_enabled =3D false; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. + * Writes to R15 are UNPREDICTABLE; we choose to undef. + */ + if (a->rt =3D=3D 15 || a->reg !=3D ARM_VFP_FPSCR) { + return false; + } + } + + switch (a->reg) { + case ARM_VFP_FPSID: + /* + * VFPv2 allows access to FPSID from userspace; VFPv3 restricts + * all ID registers to privileged access only. + */ + if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + ignore_vfp_enabled =3D true; + break; + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) { + return false; + } + ignore_vfp_enabled =3D true; + break; + case ARM_VFP_MVFR2: + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + ignore_vfp_enabled =3D true; + break; + case ARM_VFP_FPSCR: + break; + case ARM_VFP_FPEXC: + if (IS_USER(s)) { + return false; + } + ignore_vfp_enabled =3D true; + break; + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + /* Not present in VFPv3 */ + if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + break; + default: + return false; + } + + if (!full_vfp_access_check(s, ignore_vfp_enabled)) { + return true; + } + + if (a->l) { + /* VMRS, move VFP special register to gp register */ + switch (a->reg) { + case ARM_VFP_FPSID: + case ARM_VFP_FPEXC: + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + tmp =3D load_cpu_field(vfp.xregs[a->reg]); + break; + case ARM_VFP_FPSCR: + if (a->rt =3D=3D 15) { + tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + } else { + tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + } + break; + default: + g_assert_not_reached(); + } + + if (a->rt =3D=3D 15) { + /* Set the 4 flag bits in the CPSR. */ + gen_set_nzcv(tmp); + tcg_temp_free_i32(tmp); + } else { + store_reg(s, a->rt, tmp); + } + } else { + /* VMSR, move gp register to VFP special register */ + switch (a->reg) { + case ARM_VFP_FPSID: + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + /* Writes are ignored. */ + break; + case ARM_VFP_FPSCR: + tmp =3D load_reg(s, a->rt); + gen_helper_vfp_set_fpscr(cpu_env, tmp); + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + break; + case ARM_VFP_FPEXC: + /* + * TODO: VFP subarchitecture support. + * For now, keep the EN bit only + */ + tmp =3D load_reg(s, a->rt); + tcg_gen_andi_i32(tmp, tmp, 1 << 30); + store_cpu_field(tmp, vfp.xregs[a->reg]); + gen_lookup_tb(s); + break; + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + tmp =3D load_reg(s, a->rt); + store_cpu_field(tmp, vfp.xregs[a->reg]); + break; + default: + g_assert_not_reached(); + } + } + + return true; +} + +static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) +{ + TCGv_i32 tmp; + + if (!vfp_access_check(s)) { + return true; + } + + if (a->l) { + /* VFP to general purpose register */ + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vn); + if (a->rt =3D=3D 15) { + /* Set the 4 flag bits in the CPSR. */ + gen_set_nzcv(tmp); + tcg_temp_free_i32(tmp); + } else { + store_reg(s, a->rt, tmp); + } + } else { + /* general purpose register to VFP */ + tmp =3D load_reg(s, a->rt); + neon_store_reg32(tmp, a->vn); + tcg_temp_free_i32(tmp); + } + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index ff9c6a43d84..6bb0e994cc5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3097,7 +3097,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; - bool ignore_vfp_enabled =3D false; =20 if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { return 1; @@ -3133,14 +3132,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) * for invalid encodings; we will generate incorrect syndrome informat= ion * for attempts to execute invalid vfp/neon encodings with FP disabled. */ - if ((insn & 0x0fe00fff) =3D=3D 0x0ee00a10) { - rn =3D (insn >> 16) & 0xf; - if (rn =3D=3D ARM_VFP_FPSID || rn =3D=3D ARM_VFP_FPEXC || rn =3D= =3D ARM_VFP_MVFR2 - || rn =3D=3D ARM_VFP_MVFR1 || rn =3D=3D ARM_VFP_MVFR0) { - ignore_vfp_enabled =3D true; - } - } - if (!full_vfp_access_check(s, ignore_vfp_enabled)) { + if (!vfp_access_check(s)) { return 0; } =20 @@ -3148,142 +3140,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) switch ((insn >> 24) & 0xf) { case 0xe: if (insn & (1 << 4)) { - /* single register transfer */ - rd =3D (insn >> 12) & 0xf; - if (dp) { - /* already handled by decodetree */ - return 1; - } else { /* !dp */ - bool is_sysreg; - - if ((insn & 0x6f) !=3D 0x00) - return 1; - rn =3D VFP_SREG_N(insn); - - is_sysreg =3D extract32(insn, 21, 1); - - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. - * Writes to R15 are UNPREDICTABLE; we choose to undef. - */ - if (is_sysreg && (rd =3D=3D 15 || (rn >> 1) !=3D ARM_V= FP_FPSCR)) { - return 1; - } - } - - if (insn & ARM_CP_RW_BIT) { - /* vfp->arm */ - if (is_sysreg) { - /* system register */ - rn >>=3D 1; - - switch (rn) { - case ARM_VFP_FPSID: - /* VFP2 allows access to FSID from userspace. - VFP3 restricts all id registers to privileg= ed - accesses. */ - if (IS_USER(s) - && arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return 1; - } - tmp =3D load_cpu_field(vfp.xregs[rn]); - break; - case ARM_VFP_FPEXC: - if (IS_USER(s)) - return 1; - tmp =3D load_cpu_field(vfp.xregs[rn]); - break; - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: - /* Not present in VFP3. */ - if (IS_USER(s) - || arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return 1; - } - tmp =3D load_cpu_field(vfp.xregs[rn]); - break; - case ARM_VFP_FPSCR: - if (rd =3D=3D 15) { - tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_F= PSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); - } else { - tmp =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); - } - break; - case ARM_VFP_MVFR2: - if (!arm_dc_feature(s, ARM_FEATURE_V8)) { - return 1; - } - /* fall through */ - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - if (IS_USER(s) - || !arm_dc_feature(s, ARM_FEATURE_MVFR)) { - return 1; - } - tmp =3D load_cpu_field(vfp.xregs[rn]); - break; - default: - return 1; - } - } else { - gen_mov_F0_vreg(0, rn); - tmp =3D gen_vfp_mrs(); - } - if (rd =3D=3D 15) { - /* Set the 4 flag bits in the CPSR. */ - gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - } - } else { - /* arm->vfp */ - if (is_sysreg) { - rn >>=3D 1; - /* system register */ - switch (rn) { - case ARM_VFP_FPSID: - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - /* Writes are ignored. */ - break; - case ARM_VFP_FPSCR: - tmp =3D load_reg(s, rd); - gen_helper_vfp_set_fpscr(cpu_env, tmp); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - case ARM_VFP_FPEXC: - if (IS_USER(s)) - return 1; - /* TODO: VFP subarchitecture support. - * For now, keep the EN bit only */ - tmp =3D load_reg(s, rd); - tcg_gen_andi_i32(tmp, tmp, 1 << 30); - store_cpu_field(tmp, vfp.xregs[rn]); - gen_lookup_tb(s); - break; - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: - if (IS_USER(s)) { - return 1; - } - tmp =3D load_reg(s, rd); - store_cpu_field(tmp, vfp.xregs[rn]); - break; - default: - return 1; - } - } else { - tmp =3D load_reg(s, rd); - gen_vfp_msr(tmp); - gen_mov_vreg_F0(0, rn); - } - } - } + /* already handled by decodetree */ + return 1; } else { /* data processing */ bool rd_is_dp =3D dp; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 8286bdc0729..bb7de403df3 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -62,3 +62,7 @@ VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1= 0000 \ =20 VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ vn=3D%vn_dp + +VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 +VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ + vn=3D%vn_sp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 14/42] target/arm: Convert VFP two-register transfer insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 70 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 46 +--------------------- target/arm/vfp.decode | 5 +++ 3 files changed, 77 insertions(+), 44 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 74c10f9024b..5f081221b83 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -783,3 +783,73 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) =20 return true; } + +static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) +{ + TCGv_i32 tmp; + + /* + * VMOV between two general-purpose registers and two single precision + * floating point registers + */ + if (!vfp_access_check(s)) { + return true; + } + + if (a->op) { + /* fpreg to gpreg */ + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + store_reg(s, a->rt, tmp); + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm + 1); + store_reg(s, a->rt2, tmp); + } else { + /* gpreg to fpreg */ + tmp =3D load_reg(s, a->rt); + neon_store_reg32(tmp, a->vm); + tmp =3D load_reg(s, a->rt2); + neon_store_reg32(tmp, a->vm + 1); + } + + return true; +} + +static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a) +{ + TCGv_i32 tmp; + + /* + * VMOV between two general-purpose registers and one double precision + * floating point register + */ + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (a->op) { + /* fpreg to gpreg */ + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm * 2); + store_reg(s, a->rt, tmp); + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm * 2 + 1); + store_reg(s, a->rt2, tmp); + } else { + /* gpreg to fpreg */ + tmp =3D load_reg(s, a->rt); + neon_store_reg32(tmp, a->vm * 2); + tcg_temp_free_i32(tmp); + tmp =3D load_reg(s, a->rt2); + neon_store_reg32(tmp, a->vm * 2 + 1); + tcg_temp_free_i32(tmp); + } + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 6bb0e994cc5..a57d972eaa7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3703,50 +3703,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) case 0xc: case 0xd: if ((insn & 0x03e00000) =3D=3D 0x00400000) { - /* two-register transfer */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - if (dp) { - VFP_DREG_M(rm, insn); - } else { - rm =3D VFP_SREG_M(insn); - } - - if (insn & ARM_CP_RW_BIT) { - /* vfp->arm */ - if (dp) { - gen_mov_F0_vreg(0, rm * 2); - tmp =3D gen_vfp_mrs(); - store_reg(s, rd, tmp); - gen_mov_F0_vreg(0, rm * 2 + 1); - tmp =3D gen_vfp_mrs(); - store_reg(s, rn, tmp); - } else { - gen_mov_F0_vreg(0, rm); - tmp =3D gen_vfp_mrs(); - store_reg(s, rd, tmp); - gen_mov_F0_vreg(0, rm + 1); - tmp =3D gen_vfp_mrs(); - store_reg(s, rn, tmp); - } - } else { - /* arm->vfp */ - if (dp) { - tmp =3D load_reg(s, rd); - gen_vfp_msr(tmp); - gen_mov_vreg_F0(0, rm * 2); - tmp =3D load_reg(s, rn); - gen_vfp_msr(tmp); - gen_mov_vreg_F0(0, rm * 2 + 1); - } else { - tmp =3D load_reg(s, rd); - gen_vfp_msr(tmp); - gen_mov_vreg_F0(0, rm); - tmp =3D load_reg(s, rn); - gen_vfp_msr(tmp); - gen_mov_vreg_F0(0, rm + 1); - } - } + /* Already handled by decodetree */ + return 1; } else { /* Load/store */ rn =3D (insn >> 16) & 0xf; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index bb7de403df3..134f1c9ef58 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -66,3 +66,8 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1= 1 0000 \ VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ vn=3D%vn_sp + +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ + vm=3D%vm_sp +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ + vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T5pJCvoVL1jFgiOABWaIy/SlC0FgTPbtTeCLF0KVYlg=; b=l0NbhlZaHlMCn8ICqpj8wMJ3RUN8ZUsGUVC53S6vBBYR7KGZ076gF0G5ffEXx+JvvI 9G+G5RY/DgqlUaQ2+WOQLEMYd3D1v0d06jHUqiI2XhLYbzYeUqRLGRThYpW5QgH5bvQC nTNOw7dFumZv7VyMLgHdXZ6wbRYPqOj4tC4u4IlLIBddW7vL5IJF+q8VQfDx67lHt03v Bk2+YfXd19JZ1/+4hxoLtbGZ9y7lVUdxNNgLVAJ2apfv6PsB+nvEVZ/59PyKag2Vow3a QFB59o5QwMtw2zQh69u2VKeJ1V/yd6Javt27ffQBa31OrooxFOQ0DxYKG/tY9lTwIsJB 5YzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T5pJCvoVL1jFgiOABWaIy/SlC0FgTPbtTeCLF0KVYlg=; b=KDUHmoQc4wX2zklS/iyoOc/qx3Rh+Ss6iFAOgp+xVp0yBvWylWmoitXlQSma1ZE6JS C4nTa8e6EJEs+bhhYSvAgtA5KCcsRJ74h6xBb42Q6QBJL5sqVyH1C2XZyUbh4yfZC1d+ dD1WQDNjpHi4W5ojCzB/Gf2N6k2KZGPwK361DAhaV22FjTNWcKqrQYvtkZN12Q2YcHiy Bw86YtSLFpZFiXYqxZm8c0cQHg2pWDY/bJM7LAu/e3rFrSXzHtEGJcvRA6WtE9UPeiKG 8XrB2BztO8DIUtkSfE3lGRbiTVyU0uD6Ot1a4b/p2Hhb8BKCFy7K9J3ViODAVuotxyTd /Axg== X-Gm-Message-State: APjAAAXnX/+pN/1KD5Les5kpaatcq6NcH4dfpfNd7hpLkYi08Mf+Z0Do 5+HCa4fC7EJ7F7Z4lW0HbNdj+g== X-Google-Smtp-Source: APXvYqz5ZWoG2qIpTbhb1G4o+WwtR7NsZH65Mrtx+0kbtWOET8UGf5LYvzJYf4A/NWOQqKU9TZhXkw== X-Received: by 2002:a1c:e718:: with SMTP id e24mr864446wmh.104.1559843188201; Thu, 06 Jun 2019 10:46:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:42 +0100 Message-Id: <20190606174609.20487-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 15/42] target/arm: Convert VFP VLDR and VSTR to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP single load/store insns VLDR and VSTR to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 73 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 22 +--------- target/arm/vfp.decode | 7 ++++ 3 files changed, 82 insertions(+), 20 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 5f081221b83..40f2cac3e2e 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -853,3 +853,76 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_sp *a) =20 return true; } + +static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) +{ + uint32_t offset; + TCGv_i32 addr; + + if (!vfp_access_check(s)) { + return true; + } + + offset =3D a->imm << 2; + if (!a->u) { + offset =3D -offset; + } + + if (s->thumb && a->rn =3D=3D 15) { + /* This is actually UNPREDICTABLE */ + addr =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(addr, s->pc & ~2); + } else { + addr =3D load_reg(s, a->rn); + } + tcg_gen_addi_i32(addr, addr, offset); + if (a->l) { + gen_vfp_ld(s, false, addr); + gen_mov_vreg_F0(false, a->vd); + } else { + gen_mov_F0_vreg(false, a->vd); + gen_vfp_st(s, false, addr); + } + tcg_temp_free_i32(addr); + + return true; +} + +static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a) +{ + uint32_t offset; + TCGv_i32 addr; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + offset =3D a->imm << 2; + if (!a->u) { + offset =3D -offset; + } + + if (s->thumb && a->rn =3D=3D 15) { + /* This is actually UNPREDICTABLE */ + addr =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(addr, s->pc & ~2); + } else { + addr =3D load_reg(s, a->rn); + } + tcg_gen_addi_i32(addr, addr, offset); + if (a->l) { + gen_vfp_ld(s, true, addr); + gen_mov_vreg_F0(true, a->vd); + } else { + gen_mov_F0_vreg(true, a->vd); + gen_vfp_st(s, true, addr); + } + tcg_temp_free_i32(addr); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index a57d972eaa7..de3bde4b55f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3713,26 +3713,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) else rd =3D VFP_SREG_D(insn); if ((insn & 0x01200000) =3D=3D 0x01000000) { - /* Single load/store */ - offset =3D (insn & 0xff) << 2; - if ((insn & (1 << 23)) =3D=3D 0) - offset =3D -offset; - if (s->thumb && rn =3D=3D 15) { - /* This is actually UNPREDICTABLE */ - addr =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr =3D load_reg(s, rn); - } - tcg_gen_addi_i32(addr, addr, offset); - if (insn & (1 << 20)) { - gen_vfp_ld(s, dp, addr); - gen_mov_vreg_F0(dp, rd); - } else { - gen_mov_F0_vreg(dp, rd); - gen_vfp_st(s, dp, addr); - } - tcg_temp_free_i32(addr); + /* Already handled by decodetree */ + return 1; } else { /* load/store multiple */ int w =3D insn & (1 << 21); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 134f1c9ef58..8fa7fa0bead 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -71,3 +71,10 @@ VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 ...= . \ vm=3D%vm_sp VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ vm=3D%vm_dp + +# Note that the half-precision variants of VLDR and VSTR are +# not part of this decodetree at all because they have bits [9:8] =3D=3D 0= b01 +VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ + vd=3D%vd_sp +VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ + vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2hMUMrakSCxqu0+AorNAFQDJwafHWVC502jtmxiJQCQ=; b=zvvfzakuj3sdQU3phw60fwS15pSc85DsXI1mKipCMlK/Jt2XI/IdNW/JwzaYepMiIw 0/0A7eos3whg2/nY2eKFx2iQhnQbvuBSNlanqxEbL8ro5uRBtpq92GLSj5ZrqyWSZ+gj KqlAKQU9fvwDJ+WAZHlCuryaVYAq03o8daQxEuDP3gGP1i2q4XhmZRryXtGc3LEKJAdm oA+CmxBsxkvn7+6MgpIH+CSSg6U3S7P/1hvJG5lUv6i0H62s9zFWVvGSFQjq4tZ4TFIW LTRMY72tvnjlHkCasopTKqTN9/TV8vhaRIw96h6EMxiYISAdR/wayw3NJHuhajZMKGWf cxcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2hMUMrakSCxqu0+AorNAFQDJwafHWVC502jtmxiJQCQ=; b=bCSnN4Xu8MV5Im2RrCdmSJZByoNtbXWWFw7oBGVaTDCrZNERYN5oyR4451IqNCle5v /iSymDoEv/F6on1Ddoz+A0q2JqRkmeLaH1GLTe81L8Ruyuh2HkOa4acI933dScA8/nS6 MRZrMWNyqoKMZYudsoV/55Q+fUVNTjgKd7ioJh1rUEwHZkOSNiraTYW7FGTqLo58oLhf rNr58zN9kKRHA2c/Bf9axPsC1AOfXfsGdhU+5RaXpPRrx0nVa4x2vRTRc+SltB2B6BYH 3cZe8mGuGxy2fc9LZOEgUp+HC1NVVY2amLSVChoY71+NG52IuRbKfhT5B8t/qhYbgIqa 1+jw== X-Gm-Message-State: APjAAAWx4/N2S2MnbSJT6911T9W1aDE5XluZyyC+xTziVvRmDElg6nKQ KrtUBnJLBweKYSGjl3IZ7n4mxA== X-Google-Smtp-Source: APXvYqx9tn+DRUm0mJ0yXY8gRVkbQNfKGbHdzjhQX1xAuPM/FDAGScX1se1BzQMpByyZVCnkT6nlkQ== X-Received: by 2002:adf:b64b:: with SMTP id i11mr30611696wre.205.1559843189443; Thu, 06 Jun 2019 10:46:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:43 +0100 Message-Id: <20190606174609.20487-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 162 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 97 +------------------- target/arm/vfp.decode | 18 ++++ 3 files changed, 183 insertions(+), 94 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 40f2cac3e2e..32a1805e582 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -926,3 +926,165 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_sp *a) =20 return true; } + +static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) +{ + uint32_t offset; + TCGv_i32 addr; + int i, n; + + n =3D a->imm; + + if (n =3D=3D 0 || (a->vd + n) > 32) { + /* + * UNPREDICTABLE cases for bad immediates: we choose to + * UNDEF to avoid generating huge numbers of TCG ops + */ + return false; + } + if (a->rn =3D=3D 15 && a->w) { + /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (s->thumb && a->rn =3D=3D 15) { + /* This is actually UNPREDICTABLE */ + addr =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(addr, s->pc & ~2); + } else { + addr =3D load_reg(s, a->rn); + } + if (a->p) { + /* pre-decrement */ + tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * Here 'addr' is the lowest address we will store to, + * and is either the old SP (if post-increment) or + * the new SP (if pre-decrement). For post-increment + * where the old value is below the limit and the new + * value is above, it is UNKNOWN whether the limit check + * triggers; we choose to trigger. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + offset =3D 4; + for (i =3D 0; i < n; i++) { + if (a->l) { + /* load */ + gen_vfp_ld(s, false, addr); + gen_mov_vreg_F0(false, a->vd + i); + } else { + /* store */ + gen_mov_F0_vreg(false, a->vd + i); + gen_vfp_st(s, false, addr); + } + tcg_gen_addi_i32(addr, addr, offset); + } + if (a->w) { + /* writeback */ + if (a->p) { + offset =3D -offset * n; + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + + return true; +} + +static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) +{ + uint32_t offset; + TCGv_i32 addr; + int i, n; + + n =3D a->imm >> 1; + + if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { + /* + * UNPREDICTABLE cases for bad immediates: we choose to + * UNDEF to avoid generating huge numbers of TCG ops + */ + return false; + } + if (a->rn =3D=3D 15 && a->w) { + /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (s->thumb && a->rn =3D=3D 15) { + /* This is actually UNPREDICTABLE */ + addr =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(addr, s->pc & ~2); + } else { + addr =3D load_reg(s, a->rn); + } + if (a->p) { + /* pre-decrement */ + tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * Here 'addr' is the lowest address we will store to, + * and is either the old SP (if post-increment) or + * the new SP (if pre-decrement). For post-increment + * where the old value is below the limit and the new + * value is above, it is UNKNOWN whether the limit check + * triggers; we choose to trigger. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + offset =3D 8; + for (i =3D 0; i < n; i++) { + if (a->l) { + /* load */ + gen_vfp_ld(s, true, addr); + gen_mov_vreg_F0(true, a->vd + i); + } else { + /* store */ + gen_mov_F0_vreg(true, a->vd + i); + gen_vfp_st(s, true, addr); + } + tcg_gen_addi_i32(addr, addr, offset); + } + if (a->w) { + /* writeback */ + if (a->p) { + offset =3D -offset * n; + } else if (a->imm & 1) { + offset =3D 4; + } else { + offset =3D 0; + } + + if (offset !=3D 0) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index de3bde4b55f..a109f058795 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3092,9 +3092,8 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; + uint32_t rd, rn, rm, op, i, n, delta_d, delta_m, bank_mask; int dp, veclen; - TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; =20 @@ -3702,98 +3701,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) break; case 0xc: case 0xd: - if ((insn & 0x03e00000) =3D=3D 0x00400000) { - /* Already handled by decodetree */ - return 1; - } else { - /* Load/store */ - rn =3D (insn >> 16) & 0xf; - if (dp) - VFP_DREG_D(rd, insn); - else - rd =3D VFP_SREG_D(insn); - if ((insn & 0x01200000) =3D=3D 0x01000000) { - /* Already handled by decodetree */ - return 1; - } else { - /* load/store multiple */ - int w =3D insn & (1 << 21); - if (dp) - n =3D (insn >> 1) & 0x7f; - else - n =3D insn & 0xff; - - if (w && !(((insn >> 23) ^ (insn >> 24)) & 1)) { - /* P =3D=3D U , W =3D=3D 1 =3D> UNDEF */ - return 1; - } - if (n =3D=3D 0 || (rd + n) > 32 || (dp && n > 16)) { - /* UNPREDICTABLE cases for bad immediates: we choose to - * UNDEF to avoid generating huge numbers of TCG ops - */ - return 1; - } - if (rn =3D=3D 15 && w) { - /* writeback to PC is UNPREDICTABLE, we choose to UNDE= F */ - return 1; - } - - if (s->thumb && rn =3D=3D 15) { - /* This is actually UNPREDICTABLE */ - addr =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr =3D load_reg(s, rn); - } - if (insn & (1 << 24)) /* pre-decrement */ - tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2)); - - if (s->v8m_stackcheck && rn =3D=3D 13 && w) { - /* - * Here 'addr' is the lowest address we will store to, - * and is either the old SP (if post-increment) or - * the new SP (if pre-decrement). For post-increment - * where the old value is below the limit and the new - * value is above, it is UNKNOWN whether the limit che= ck - * triggers; we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - if (dp) - offset =3D 8; - else - offset =3D 4; - for (i =3D 0; i < n; i++) { - if (insn & ARM_CP_RW_BIT) { - /* load */ - gen_vfp_ld(s, dp, addr); - gen_mov_vreg_F0(dp, rd + i); - } else { - /* store */ - gen_mov_F0_vreg(dp, rd + i); - gen_vfp_st(s, dp, addr); - } - tcg_gen_addi_i32(addr, addr, offset); - } - if (w) { - /* writeback */ - if (insn & (1 << 24)) - offset =3D -offset * n; - else if (dp && (insn & 1)) - offset =3D 4; - else - offset =3D 0; - - if (offset !=3D 0) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - } - break; + /* Already handled by decodetree */ + return 1; default: /* Should never happen. */ return 1; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 8fa7fa0bead..68c9ffcfd3c 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -78,3 +78,21 @@ VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ vd=3D%vd_sp VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ vd=3D%vd_dp + +# We split the load/store multiple up into two patterns to avoid +# overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" +# grouping: +# P=3D0 U=3D0 W=3D0 is 64-bit VMOV +# P=3D1 W=3D0 is VLDR/VSTR +# P=3DU W=3D1 is UNDEF +# leaving P=3D0 U=3D1 W=3Dx and P=3D1 U=3D0 W=3D1 for load/store multiple. +# These include FSTM/FLDM. +VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ + vd=3D%vd_sp p=3D0 u=3D1 +VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ + vd=3D%vd_dp p=3D0 u=3D1 + +VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ + vd=3D%vd_sp p=3D1 u=3D0 w=3D1 +VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ + vd=3D%vd_dp p=3D1 u=3D0 w=3D1 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844099; cv=none; d=zoho.com; s=zohoarc; b=adrQKZ0TqlhQ6fGCX9OgAeNdINUj15o6RQisSKC86gJ+5zNBwFZrfDhzF8q0EeYyc21GmNfVRs6f1vW1Ttxmgf2jXMO1jm8OnIQeFrjSH5FQmzYRDVtQPNYZSbsvHgonm4utnGCFB+vWcykkZ/lO6L/7vw+jR7sFWvHf4aDE6WI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844099; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=xuR5O75XRjEcreJpXtoncdyc1wUFktWsTBFaHEVLLS4=; b=eeaRbrFYyYVRuv7PXnG48WUgyhaD84PImRC4ngpEXtQXni9XRcDjQQr0QzPwyjZCVuOALy0ebL888WuVFoOyRZjDnwyBoGatb6NHXZci8VPjAfZfme0AmOrym5I9j1jpipO10bC8aEpOoWU3JNVckDVD1ZhOpCqKDs1RH3n/3CY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559844099498419.00925495070203; Thu, 6 Jun 2019 11:01:39 -0700 (PDT) Received: from localhost ([127.0.0.1]:36118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwhm-0000Fg-9m for importer@patchew.org; Thu, 06 Jun 2019 14:01:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwTt-0004D5-5m for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwTq-0003jA-VM for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:17 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwTo-00031f-8u for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:12 -0400 Received: by mail-wm1-x341.google.com with SMTP id z23so808360wma.4 for ; Thu, 06 Jun 2019 10:46:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xuR5O75XRjEcreJpXtoncdyc1wUFktWsTBFaHEVLLS4=; b=MpuHRXLiK1N8Ag2Jyzt6vPT55fWy72zJv9vVem14NGWlcztB2V6kou0WLKXfOGuWw7 FiuFVyb321lzS3nnQWV8sBDrTZgdyfRpipIg4Z0MZhy3r1Ik04m6raSLbO4x8uHlBmcu 74fvIxQrdcFQxJ7ybwI+qN8SDCZKz8wrklvSOvXt/H2cNaUVf7Oyc67QFq0a0K1XUlI8 4CdZF/aXWIytaKM6skEGjig1if3sKuDHt9kQql86/3en0nQXewhYByVn/C0fYJA/9wTt ucQtNhHAsEJ/gl+uSpd9EcPwABcQX5iGLFEEz9jkQqLZ6Fv+Xo9g1BBOhBrAtQogrev5 abDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xuR5O75XRjEcreJpXtoncdyc1wUFktWsTBFaHEVLLS4=; b=itVkNAC+6iJBc+vsOJeseJlpHu2snzM9xgKJXrJf3lRlFAmK76JyrKpdDSSOBTAmfU sdVJuqnzR2Ri81x1ZyLERAlPtgyQVU7/9OQpo/U4eOVHwSqllgW98M/pwsugTiAPlwE6 ug1GDWTWGmUpmiDBlAVpkCOH6+V6f+qSWH5nhKCbpiVrOzy3utZd0jm/miPY6Q1LZ+tC BONAf+zJRSXnMBb1Ji5jAiXyBBxPE2y8mvHgjE0Z6Rt4WeyEPYEZvSAQ3cYX895i4f4j Ggj3RhcPl1XGYn9Q4oGRXwRTMWbPnvsV9hjXEPMwV9sLiYGcO9GlbA+V7V8xv+84aUYm Azbw== X-Gm-Message-State: APjAAAUC0D5NHYfXOPv+wQ/sQAWwvCogYX5wiEbWKmm5oVOo5LGon5Cs CjAeboWC6oaAHN/pRIACSUKJquyP4Uus8A== X-Google-Smtp-Source: APXvYqyJtVcurFHJGzSm0ECKTwoXC0o0uwytX0IJb8F7K0yjihv92ZkPOWNLCwpWnbNWRp2/oqgoow== X-Received: by 2002:a1c:f712:: with SMTP id v18mr912640wmh.0.1559843190483; Thu, 06 Jun 2019 10:46:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:44 +0100 Message-Id: <20190606174609.20487-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 46 +++++++++++++++++++++------------- target/arm/translate.c | 18 ------------- 2 files changed, 28 insertions(+), 36 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 32a1805e582..9729946d734 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -857,7 +857,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_= 64_sp *a) static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) { uint32_t offset; - TCGv_i32 addr; + TCGv_i32 addr, tmp; =20 if (!vfp_access_check(s)) { return true; @@ -876,13 +876,15 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_V= LDR_VSTR_sp *a) addr =3D load_reg(s, a->rn); } tcg_gen_addi_i32(addr, addr, offset); + tmp =3D tcg_temp_new_i32(); if (a->l) { - gen_vfp_ld(s, false, addr); - gen_mov_vreg_F0(false, a->vd); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd); } else { - gen_mov_F0_vreg(false, a->vd); - gen_vfp_st(s, false, addr); + neon_load_reg32(tmp, a->vd); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } + tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); =20 return true; @@ -892,6 +894,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_sp *a) { uint32_t offset; TCGv_i32 addr; + TCGv_i64 tmp; =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { @@ -915,13 +918,15 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_sp *a) addr =3D load_reg(s, a->rn); } tcg_gen_addi_i32(addr, addr, offset); + tmp =3D tcg_temp_new_i64(); if (a->l) { - gen_vfp_ld(s, true, addr); - gen_mov_vreg_F0(true, a->vd); + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd); } else { - gen_mov_F0_vreg(true, a->vd); - gen_vfp_st(s, true, addr); + neon_load_reg64(tmp, a->vd); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } + tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); =20 return true; @@ -930,7 +935,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_sp *a) static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) { uint32_t offset; - TCGv_i32 addr; + TCGv_i32 addr, tmp; int i, n; =20 n =3D a->imm; @@ -976,18 +981,20 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) } =20 offset =3D 4; + tmp =3D tcg_temp_new_i32(); for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_vfp_ld(s, false, addr); - gen_mov_vreg_F0(false, a->vd + i); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd + i); } else { /* store */ - gen_mov_F0_vreg(false, a->vd + i); - gen_vfp_st(s, false, addr); + neon_load_reg32(tmp, a->vd + i); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); } + tcg_temp_free_i32(tmp); if (a->w) { /* writeback */ if (a->p) { @@ -1006,6 +1013,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) { uint32_t offset; TCGv_i32 addr; + TCGv_i64 tmp; int i, n; =20 n =3D a->imm >> 1; @@ -1056,18 +1064,20 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) } =20 offset =3D 8; + tmp =3D tcg_temp_new_i64(); for (i =3D 0; i < n; i++) { if (a->l) { /* load */ - gen_vfp_ld(s, true, addr); - gen_mov_vreg_F0(true, a->vd + i); + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd + i); } else { /* store */ - gen_mov_F0_vreg(true, a->vd + i); - gen_vfp_st(s, true, addr); + neon_load_reg64(tmp, a->vd + i); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); } + tcg_temp_free_i64(tmp); if (a->w) { /* writeback */ if (a->p) { diff --git a/target/arm/translate.c b/target/arm/translate.c index a109f058795..cc4cb81a46e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1522,24 +1522,6 @@ VFP_GEN_FIX(uhto, ) VFP_GEN_FIX(ulto, ) #undef VFP_GEN_FIX =20 -static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr) -{ - if (dp) { - gen_aa32_ld64(s, cpu_F0d, addr, get_mem_index(s)); - } else { - gen_aa32_ld32u(s, cpu_F0s, addr, get_mem_index(s)); - } -} - -static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr) -{ - if (dp) { - gen_aa32_st64(s, cpu_F0d, addr, get_mem_index(s)); - } else { - gen_aa32_st32(s, cpu_F0s, addr, get_mem_index(s)); - } -} - static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559845041; cv=none; d=zoho.com; s=zohoarc; b=NMKUTEiW8h/WhV9hilWey13nkkAwT/VQwqDObsrHufzRksFSeynSWRIcZ66xLL4G8W5bisTToiLbO2m69INd2YckVcaP4ePqMFRGy0AbkefGjJiq3Wz8tJY9JPDywamhONeN2FcfMvMJNwuEWeMzlzHgz1hlT6vXpMvw6EVgqFQ= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6H2cYVZuxI3eixc96ejcRWcHNnY+ydDjL5UvKY4ybaI=; b=NTpH9iUtS1/Z3z/fxQsLYiiaKeQzFhLzvcMrcUD4JbKuDx2vybXqrkCbwiuQ9GHvA9 B9UxJa7AH6KjfpKsP4Sl8yE8byaWJxnNLx1G072MHepu6FAGgGhUrM1mQ+CnBie3RPhS farjbjz+VaQdYTm06E8epkLpNzaTeQdb6utINModO8M/bV8y0cng33wJ8IDmeof9xhi3 pCotDauSMiifeoT/0phchDLriZPLQNfRwkjfObrM0ayyM7+AcA4prBSFYihCY3NdbbVN EKwHUizPPtLsCQcYEgVlRgVXSbqy/OHiMUIxKavlR3jC8F+kCs++oi2Yz4M3HdoF9o7c zgLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6H2cYVZuxI3eixc96ejcRWcHNnY+ydDjL5UvKY4ybaI=; b=qr0+PEgso3kvIP6Xv5cUsOcxDhCgG7yl9VlAWCecscicsbAviPDSsGD6Jb+GhIaxE1 RWMq7gRJiwe5w/8Sta+AzRBV3X23wi0Cz3KLMx24jk8NS6NZ2B6uQWoHH9ZePAa/rNYh F/MM4/86VlAuBb53T/0ka2k2a0nwenc8wYFlHRi0mXMvKrHqU9JEGs0j8UuqGEyTzlKU SAiMxAXfs1NMjcirj9TQQFpDgnRpVW7ZYciYaRKBzEVbGXcxq4C0nEvrQNGDM3KUipt+ N7Jirkdc7USLuFKNVVxaRjpus5WGWVIqcJqrb4HhkzwaGN4QZF0qoQa2iRB3+7DVv1+h 6hpw== X-Gm-Message-State: APjAAAUVzriFLtccYYeef634URXxuqSGyORDCUcCHo2mwbqV1hP/6w7F KhqzjXTAVUen8x+SVeF8Bc0fzQ== X-Google-Smtp-Source: APXvYqx+wrwuAxxFJ6S1BEtg60MW/KolQaLeTrUrjz+2qhZCvKerHjT+AcIyh1QqQ/t3SknzAluxkg== X-Received: by 2002:a05:600c:21c6:: with SMTP id x6mr837466wmj.102.1559843191698; Thu, 06 Jun 2019 10:46:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:45 +0100 Message-Id: <20190606174609.20487-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 18/42] target/arm: Convert VFP VMLA to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/translate-vfp.inc.c | 205 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 14 ++- target/arm/vfp.decode | 6 + 4 files changed, 224 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 30fb107c605..c37f78f2032 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3414,6 +3414,11 @@ static inline bool isar_feature_aa32_fp_d32(const AR= MISARegisters *id) return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; } =20 +static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 9729946d734..4f922dc8405 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1098,3 +1098,208 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) =20 return true; } + +/* + * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp(). + * The callback should emit code to write a value to vd. If + * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd + * will contain the old value of the relevant VFP register; + * otherwise it must be written to only. + */ +typedef void VFPGen3OpSPFn(TCGv_i32 vd, + TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst); +typedef void VFPGen3OpDPFn(TCGv_i64 vd, + TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst); + +/* + * Perform a 3-operand VFP data processing instruction. fn is the + * callback to do the actual operation; this function deals with the + * code to handle looping around for VFP vector processing. + */ +static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, + int vd, int vn, int vm, bool reads_vd) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i32 f0, f1, fd; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0x18; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D s->vec_stride + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i32(); + f1 =3D tcg_temp_new_i32(); + fd =3D tcg_temp_new_i32(); + fpst =3D get_fpstatus_ptr(0); + + neon_load_reg32(f0, vn); + neon_load_reg32(f1, vm); + + for (;;) { + if (reads_vd) { + neon_load_reg32(fd, vd); + } + fn(fd, f0, f1, fpst); + neon_store_reg32(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + neon_load_reg32(f0, vn); + if (delta_m) { + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg32(f1, vm); + } + } + + tcg_temp_free_i32(f0); + tcg_temp_free_i32(f1); + tcg_temp_free_i32(fd); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, + int vd, int vn, int vm, bool reads_vd) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i64 f0, f1, fd; + TCGv_ptr fpst; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0xc; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D (s->vec_stride >> 1) + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i64(); + f1 =3D tcg_temp_new_i64(); + fd =3D tcg_temp_new_i64(); + fpst =3D get_fpstatus_ptr(0); + + neon_load_reg64(f0, vn); + neon_load_reg64(f1, vm); + + for (;;) { + if (reads_vd) { + neon_load_reg64(fd, vd); + } + fn(fd, f0, f1, fpst); + neon_store_reg64(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + neon_load_reg64(f0, vn); + if (delta_m) { + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg64(f1, vm); + } + } + + tcg_temp_free_i64(f0); + tcg_temp_free_i64(f1); + tcg_temp_free_i64(fd); + tcg_temp_free_ptr(fpst); + + return true; +} + +static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fp= st) +{ + /* Note that order of inputs to the add matters for NaNs */ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a) +{ + return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fp= st) +{ + /* Note that order of inputs to the add matters for NaNs */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_sp *a) +{ + return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index cc4cb81a46e..2fa516364f3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3133,6 +3133,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) op =3D ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) = & 1); rn =3D VFP_SREG_N(insn); =20 + switch (op) { + case 0: + /* Already handled by decodetree */ + return 1; + default: + break; + } + if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { @@ -3312,12 +3320,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 0: /* VMLA: fd + (fn * fm) */ - /* Note that order of inputs to the add matters for Na= Ns */ - gen_vfp_F1_mul(dp); - gen_mov_F0_vreg(dp, rd); - gen_vfp_add(dp); - break; case 1: /* VMLS: fd + -(fn * fm) */ gen_vfp_mul(dp); gen_vfp_F1_neg(dp); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 68c9ffcfd3c..9530e17ae02 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -96,3 +96,9 @@ VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ vd=3D%vd_sp p=3D1 u=3D0 w=3D1 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ vd=3D%vd_dp p=3D1 u=3D0 w=3D1 + +# 3-register VFP data-processing; bits [23,21:20,6] identify the operation. +VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 19/42] target/arm: Convert VFP VMLS to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VMLS instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 38 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 8 +------ target/arm/vfp.decode | 5 +++++ 3 files changed, 44 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 4f922dc8405..00f64401dda 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1303,3 +1303,41 @@ static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_= sp *a) { return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true); } + +static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fp= st) +{ + /* + * VMLS: vd =3D vd + -(vn * vm) + * Note that order of inputs to the add matters for NaNs. + */ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(tmp, tmp); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a) +{ + return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fp= st) +{ + /* + * VMLS: vd =3D vd + -(vn * vm) + * Note that order of inputs to the add matters for NaNs. + */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(tmp, tmp); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_sp *a) +{ + return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 2fa516364f3..dc19d8fcab1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3134,7 +3134,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0: + case 0 ... 1: /* Already handled by decodetree */ return 1; default: @@ -3320,12 +3320,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 1: /* VMLS: fd + -(fn * fm) */ - gen_vfp_mul(dp); - gen_vfp_F1_neg(dp); - gen_mov_F0_vreg(dp, rd); - gen_vfp_add(dp); - break; case 2: /* VNMLS: -fd + (fn * fm) */ /* Note that it isn't valid to replace (-A + B) with (= B - A) * or similar plausible looking simplifications diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 9530e17ae02..7bcf2260eec 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -102,3 +102,8 @@ VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GZ0x0o1HQFZ10vVq+O8T2K/nYflpLwHxG+mZSGXfk1c=; b=F5IQ3U0+lGe5a2Qb1CD3+VtqncMm81++cPZHMdGZ2PIiPr7XFvkeUTnGdscifQP/eO PrnQlmQtx3DED+z3nP+w/TFZqE2XZuGhGyd1g+5xoZ+AJSOLFIH2uQPvv7fkUqTBINVz DVqki0qdRq0vCWPipqtx2KDFHVh7wwfg1G1oP2g192ytetxUdgFcwv1dCfv4M19HBj4b vAEQbiBsyXW5hb2cusFy/3YAPtSBgb/ficMlO6e8bM8klE6d1+kdirJc8bg06s9pnqmy eSjfXL30lOtiwtrfky+jVGU/vCnsu4nOqpHc9h0ccV5s8NXrMI4XJXR0qz0TKUgOSZwG qs9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GZ0x0o1HQFZ10vVq+O8T2K/nYflpLwHxG+mZSGXfk1c=; b=lPI0jyWpfbEgFPCE51y6bEqxURnYPAcTkMr6NY51HRrGpTrU4wrS3ptL28gL2CJuGe lgM0YzLKg+PdXqZ18Mi7aZWKagnNyorHuXYSSk7g6nmP3PTaXlrMX4Y2uqGALmb69543 6TwlrPk+ylhID1HBsjLgQR9arLzJe7HIO+fh2sO9Kztz0TFlu4suZck09TbQFV4wiq1q s2d4V+NbNEOzOkhIA+g/hlXQLzdPdUwd58DDqts8ELboAbTRdPOtzhVPJc7GHgB4V3FL N1Gck3W3+NDjAkF/0P7dflYDfXMomh5o5dOy5UMxMMoF9Gv98PTATxAjFRrK0p84cD0A cZ0A== X-Gm-Message-State: APjAAAVPNAelw98TQW7ZPDT6mjz/9mD32mSwpH9YgWAPXvOTowRAXRq5 E+MBxIU/f0hF5e1mAUagoYrDXQ== X-Google-Smtp-Source: APXvYqx/Glj6IK59PxfrLQlgZ97u1fp5AeogXe5rkTpXNclXwohQ6V+YdgMMfRC0PlCtbiWc7T4xog== X-Received: by 2002:adf:8385:: with SMTP id 5mr4068311wre.194.1559843193653; Thu, 06 Jun 2019 10:46:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:47 +0100 Message-Id: <20190606174609.20487-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 20/42] target/arm: Convert VFP VNMLS to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VNMLS instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 42 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 24 +------------------ target/arm/vfp.decode | 5 ++++ 3 files changed, 48 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 00f64401dda..1d7100debe4 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1341,3 +1341,45 @@ static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_= sp *a) { return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true); } + +static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr f= pst) +{ + /* + * VNMLS: -fd + (fn * fm) + * Note that it isn't valid to replace (-A + B) with (B - A) or similar + * plausible looking simplifications because this will give wrong resu= lts + * for NaNs. + */ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(vd, vd); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr f= pst) +{ + /* + * VNMLS: -fd + (fn * fm) + * Note that it isn't valid to replace (-A + B) with (B - A) or similar + * plausible looking simplifications because this will give wrong resu= lts + * for NaNs. + */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(vd, vd); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_sp *a) +{ + return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index dc19d8fcab1..bb86c603712 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1393,18 +1393,6 @@ VFP_OP2(div) =20 #undef VFP_OP2 =20 -static inline void gen_vfp_F1_mul(int dp) -{ - /* Like gen_vfp_mul() but put result in F1 */ - TCGv_ptr fpst =3D get_fpstatus_ptr(0); - if (dp) { - gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, fpst); - } else { - gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, fpst); - } - tcg_temp_free_ptr(fpst); -} - static inline void gen_vfp_F1_neg(int dp) { /* Like gen_vfp_neg() but put result in F1 */ @@ -3134,7 +3122,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 1: + case 0 ... 2: /* Already handled by decodetree */ return 1; default: @@ -3320,16 +3308,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 2: /* VNMLS: -fd + (fn * fm) */ - /* Note that it isn't valid to replace (-A + B) with (= B - A) - * or similar plausible looking simplifications - * because this will give wrong results for NaNs. - */ - gen_vfp_F1_mul(dp); - gen_mov_F0_vreg(dp, rd); - gen_vfp_neg(dp); - gen_vfp_add(dp); - break; case 3: /* VNMLA: -fd + -(fn * fm) */ gen_vfp_mul(dp); gen_vfp_F1_neg(dp); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 7bcf2260eec..08e4f427408 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -107,3 +107,8 @@ VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 21/42] target/arm: Convert VFP VNMLA to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VNMLA instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 19 +------------------ target/arm/vfp.decode | 5 +++++ 3 files changed, 40 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 1d7100debe4..8532bf4abcd 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1383,3 +1383,37 @@ static bool trans_VNMLS_dp(DisasContext *s, arg_VNML= S_sp *a) { return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true); } + +static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr f= pst) +{ + /* VNMLA: -fd + -(fn * fm) */ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(tmp, tmp); + gen_helper_vfp_negs(vd, vd); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr f= pst) +{ + /* VNMLA: -fd + (fn * fm) */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(tmp, tmp); + gen_helper_vfp_negd(vd, vd); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a) +{ + return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index bb86c603712..73b30ed33d1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1393,16 +1393,6 @@ VFP_OP2(div) =20 #undef VFP_OP2 =20 -static inline void gen_vfp_F1_neg(int dp) -{ - /* Like gen_vfp_neg() but put result in F1 */ - if (dp) { - gen_helper_vfp_negd(cpu_F1d, cpu_F0d); - } else { - gen_helper_vfp_negs(cpu_F1s, cpu_F0s); - } -} - static inline void gen_vfp_abs(int dp) { if (dp) @@ -3122,7 +3112,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 2: + case 0 ... 3: /* Already handled by decodetree */ return 1; default: @@ -3308,13 +3298,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 3: /* VNMLA: -fd + -(fn * fm) */ - gen_vfp_mul(dp); - gen_vfp_F1_neg(dp); - gen_mov_F0_vreg(dp, rd); - gen_vfp_neg(dp); - gen_vfp_add(dp); - break; case 4: /* mul: fn * fm */ gen_vfp_mul(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 08e4f427408..c50d2c3ebf3 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -112,3 +112,8 @@ VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O5grNllV+sv27kAA5O3rl1i8qW/FtM8e/iepHVf3KD8=; b=p8kaIRy4pZWp1AK0+YjVMmUWTVQxxPrT3d5rzcuG+7xKitRD1gc9N1kKuqrO/vjL+f fKmx+2O9OzWJIQzC42CK31rdK8J6QrWAcSswUzCgrT3VsB8jPcQgS5ei9Cblf3P7lrUQ CoUBaVKB59i+KxtZaKwWFrpLNIC0ma0yKMksOokoFPcICBHDz4QfomgOUtBQV3E4rwU6 9CBUJQCKlzOUpOWgcdjjCXhcR3HgjBucwdpryWsP6HLNGqT4A6KkMrUH3YE70ANwEiRx aRrHdffAUDWgB3+/gJ4d/EIQhNVzq2unFwMkFoNVWL+AZS8AY6uoP7SBHq9axK5SR/mx jzAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O5grNllV+sv27kAA5O3rl1i8qW/FtM8e/iepHVf3KD8=; b=PY/Lz5wZNT2lwd0kfyThD1tWoJHJ7+k6Wl0YRZhyj659m1UuVIgpjm0LG3VyZfNTIr 9/8JSK2E5EiWCmLtnrWnGEoXP2ZfZAhA9Lb3NlGeHEjPIAkr/pvxAwQFaZqtbKn8/Upf 8J7Mlr7KdJBMOkGubG+2r5ca5KSQWs33XTa1s8YSzA0ZKSjBcNQIwKEU9bdXL6Y8XcYK HU0bkdlqYG11QjXT12OA/yXoRU9escKdWhcaQvtKVsAF53VM+WkaLRKYCz/Ge481FdLR HHrC+bKAhhGRALS2gF/nW4ucCym8v6InmpfQLVj6o/rYyzDmdzqcG7qWRJy0TrKWgJBC rJMg== X-Gm-Message-State: APjAAAWZNU7N6AFadnR3PZBatrxVGY7SBi4aCeUgHr8hjHn6NE2MM0YC LFH6fwWtybtcqkaZVaVooXfRMA== X-Google-Smtp-Source: APXvYqz1q6bLJI+Vj7CpTmKUxNMjB2p68bB+/xd2pWJyorFWeGVK4i3ODMpdNovY/VfC+Mj4d2jhBg== X-Received: by 2002:adf:e309:: with SMTP id b9mr30659068wrj.135.1559843195961; Thu, 06 Jun 2019 10:46:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:49 +0100 Message-Id: <20190606174609.20487-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 22/42] target/arm: Convert VMUL to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VMUL instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 5 +---- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8532bf4abcd..a2afe82b349 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1417,3 +1417,13 @@ static bool trans_VNMLA_dp(DisasContext *s, arg_VNML= A_sp *a) { return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); } + +static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, fals= e); +} + +static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_sp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, fals= e); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 73b30ed33d1..226f1006ced 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3112,7 +3112,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 3: + case 0 ... 4: /* Already handled by decodetree */ return 1; default: @@ -3298,9 +3298,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) for (;;) { /* Perform the calculation. */ switch (op) { - case 4: /* mul: fn * fm */ - gen_vfp_mul(dp); - break; case 5: /* nmul: -(fn * fm) */ gen_vfp_mul(dp); gen_vfp_neg(dp); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index c50d2c3ebf3..d7fcb9709a9 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -117,3 +117,8 @@ VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844126; cv=none; d=zoho.com; s=zohoarc; b=ZDzacbKfaE9sW49Hsz4pIxx+er3bQEqwM58v4XwVbXsW6fZu+Iv0Z0ESbTyW2tMu5dQD1WSB3unHVdMItYrOmJdyzMzx/9/qCAi/Oh2O2uzGR/yMrx1Iofd8WGBdlYRf5Qj7f5v9aKQwUsNivq8sH2clQ5axgDgZKIC0N424qTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844126; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nUY4whzXyU6WP8ecPGM+NaX0pvWgHVw5NXfobszfOy8=; b=Zo+TVtOy6rVIv4HwodK6OaAr91eGekUM5zqafiRT6gFxPrXkxKjtc1SNK55SLnGhuyfpRf9Lp/ndwjLOm+toSFGOYpkhmRFZawpOklqtKjUAsTYxUzc1QeGPOZD8KHa0bgr5ENxlG63xGQ6x9TLPWJoBClgTUEAWlm3dsA/W5dM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559844126348410.21049058326616; Thu, 6 Jun 2019 11:02:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:36124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwi8-00028J-W7 for importer@patchew.org; Thu, 06 Jun 2019 14:02:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44933) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwU8-0004V9-NL for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU7-0004Aw-2J for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:32 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36296) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU6-00036z-MC for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:30 -0400 Received: by mail-wm1-x343.google.com with SMTP id u8so827480wmm.1 for ; Thu, 06 Jun 2019 10:46:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nUY4whzXyU6WP8ecPGM+NaX0pvWgHVw5NXfobszfOy8=; b=XIocGkdbUohjdpc4QxP5z6w9olsbcw6lZk/w7nNiQQ0tCw5AGHYVhb9Ft0HOsE7vsN WvKY73o4Z5L6o6xkIqug2FfZZViFPQVDuS4KwNov2mN9QzBQchsEmoaxyI+6W8nq7TFU N1ir+JJSokfXkGORffm5FmKV6uTTl+KA6uEKuZf06gxNdry6xSw65WpUrTt/xYcViDre 2cn/amSOFjgXBQzaQNsQ9M0mmC31vm6gZRzaRimvHJVe8IEJ5iL5qfocqC8kpByprYhe AXllxYSrVrVL/R1pl51kX/L3wMGuMkAjUZrqGVfp9kOmU++DnBEnLwagyyEnB3oSIGCi 0uSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nUY4whzXyU6WP8ecPGM+NaX0pvWgHVw5NXfobszfOy8=; b=A7pZUg296QxVHWuGSAO5Zmzc1SjG6OeX6DvNxRE2MkqOek2EJiTWr1557JJ9zMfQGY s6w8e6nOdTXPvL2o3mmqaymxXUew/4e7B0S12Gylp6oEp0tLuzxCL2eWT3OMYvg/VHPu B5qm+mpG0BRgaiKfE+NlSV/zj2FhHkXHeD0aRBRye+5lOARbvA2qpK2EQvcdPTzly3oQ zfFdFbV9QXUuiscxWeKflO8mi1IjFwpLiuzAljkRjFO3T1Uym21ccfIPe7PaA1GmWJmZ LKalWJVV7NTjECxcH68hwFQ0RzI1kMFAsPwzjP23hF+HbMX0t2VacgSqPuUXTLM0A7Dk 8E5A== X-Gm-Message-State: APjAAAWZmQc2fSXpjIQMcIxqp1VZpXYCRweqIg0ftmyBAcjlDw+srji2 iaI+CRgTuhCINb2LqVJSKZd0/Q== X-Google-Smtp-Source: APXvYqwwc9TDH0UDF7WFTC8zm2We7QQX3POscAnpkXYWgY6BeOaAT3HCFYyWe+xvH+5m7ilEEUrKxA== X-Received: by 2002:a7b:c057:: with SMTP id u23mr825826wmc.29.1559843196978; Thu, 06 Jun 2019 10:46:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:50 +0100 Message-Id: <20190606174609.20487-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 23/42] target/arm: Convert VNMUL to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VNMUL instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 24 ++++++++++++++++++++++++ target/arm/translate.c | 7 +------ target/arm/vfp.decode | 5 +++++ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a2afe82b349..4c684f033b6 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1427,3 +1427,27 @@ static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_= sp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, fals= e); } + +static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr f= pst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muls(vd, vn, vm, fpst); + gen_helper_vfp_negs(vd, vd); +} + +static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false); +} + +static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr f= pst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muld(vd, vn, vm, fpst); + gen_helper_vfp_negd(vd, vd); +} + +static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_sp *a) +{ + return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 226f1006ced..23addcf53d6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1388,7 +1388,6 @@ static inline void gen_vfp_##name(int dp) = \ =20 VFP_OP2(add) VFP_OP2(sub) -VFP_OP2(mul) VFP_OP2(div) =20 #undef VFP_OP2 @@ -3112,7 +3111,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 4: + case 0 ... 5: /* Already handled by decodetree */ return 1; default: @@ -3298,10 +3297,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 5: /* nmul: -(fn * fm) */ - gen_vfp_mul(dp); - gen_vfp_neg(dp); - break; case 6: /* add: fn + fm */ gen_vfp_add(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index d7fcb9709a9..3063fcac23f 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -122,3 +122,8 @@ VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7cJ3cFmAyElsbk0Hu0rymmkEdd46OTUs5chKPb+2SUk=; b=PuzlN0rOoe+tct2TDQT9IC5tcPr1vkND3v3RXksDDziqk71KN+I8TM4mGsw6gjSsOC zc0I5GCHYLuY2iIPqWRRmNzYATGQXE4iQUwk8bvjPykHMgepqJdVu9xi8QUiNW2/7k3m zdeTw5IQndN3DmT48esq9QVncIiIWXyX9UimzoVeGedZqdGybV4c2S0aBCYtTVQto4i1 Yk3ODpGi6XUxjgJ+d6+PKN8aD/61vnjxXGNZqTclD+1rNlJrfMyvgIShncRbNdGEN3W0 HqprcflwaiJiFUN4o8D7doQYbrlWUsXsdrhaI7e8HK6eQCfAtLrvI3nsCCuqWewHazXQ +Rog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7cJ3cFmAyElsbk0Hu0rymmkEdd46OTUs5chKPb+2SUk=; b=NOqLO0zDqtXnIbWxIk1tdOksbXPEL4fWWqqMqaiz/8zbYKsUPdoeNKWx5hTYJm/5Zq 7/IsKJeu4iUOSA8cO2RUyno8LomqW5UmU0iZCL5Km4JFz9ONpuQ//8moJ5cqVYgFbHjI nNSk98+HYtu4d1TAzsblEEehRqEGgAzgn/bGBflnJ+Awp+RxD7xVtMz0yjXAhOau8q5s MVNpXvnLG/z/6UIn1u91NjaYvtRiwB30hFgqLw/QfIBmrnB/aG97//5gNt/iPylpJPQq 8trVDMjj49O4+fB3OpAA3Vo542hqhi52aFPUuOVz1C3QWXlK4kX+/cPD0IZ1xwJiX99E BtVA== X-Gm-Message-State: APjAAAXw8eYOXwrq1mmwpHaptm23zXkEPe4/658qWY5jGYlxbAAGRthS 1EEkhkXHVEeIVSDNAgcVj99MrA== X-Google-Smtp-Source: APXvYqwNOjLbparFDztc5upKC6q8OlaD59H1/fy/WMloMbPoIaAitzEnTw3k6NME/WFfkBCcIjq7TA== X-Received: by 2002:a1c:ed07:: with SMTP id l7mr753998wmh.148.1559843197969; Thu, 06 Jun 2019 10:46:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:51 +0100 Message-Id: <20190606174609.20487-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 24/42] target/arm: Convert VADD to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VADD instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 6 +----- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 4c684f033b6..14aeb25f597 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1451,3 +1451,13 @@ static bool trans_VNMUL_dp(DisasContext *s, arg_VNMU= L_sp *a) { return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); } + +static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, fals= e); +} + +static bool trans_VADD_dp(DisasContext *s, arg_VADD_sp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, fals= e); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 23addcf53d6..7fa255f6598 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1386,7 +1386,6 @@ static inline void gen_vfp_##name(int dp) = \ tcg_temp_free_ptr(fpst); \ } =20 -VFP_OP2(add) VFP_OP2(sub) VFP_OP2(div) =20 @@ -3111,7 +3110,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 5: + case 0 ... 6: /* Already handled by decodetree */ return 1; default: @@ -3297,9 +3296,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) for (;;) { /* Perform the calculation. */ switch (op) { - case 6: /* add: fn + fm */ - gen_vfp_add(dp); - break; case 7: /* sub: fn - fm */ gen_vfp_sub(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 3063fcac23f..d911f12dfd0 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -127,3 +127,8 @@ VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844273; cv=none; d=zoho.com; s=zohoarc; b=oQ3EyEK0CBDoKhoa8u/rlEXfUd8wzxq7CbB/Xs0loZLpEuQWBsUVqcWSf4I+zy/ADL5MeSxfQaJiWt5dIh006VEuHirihuKnYmU4oexPdKA5nfdQJSQm7I8zDNHr3qSkcN7WRGsH2FryxNEsNDpaYfgQUNPM2M0oERaZTQvdpbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844273; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nNQjd9/+a2DdLghORqFl+Muzj1ZfiiJpWnJhjxjLPOE=; b=US2GP7z3IgF3QwubSdNkPUERluedf3Uj4623EX1davDG+iXxMwGm/pBm3h3CDMr2C6XyKTtXLxHKHGG2ildMVOxYLx8+aX2ArMtWGMhW1BIZYFP/UdbxeaVrRHKZ87/oFMRooWtHaDCT+j7FmR53/Hfxap2LgGtfR/ZIB97aHkA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559844273138528.6154362603055; Thu, 6 Jun 2019 11:04:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:36159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwkX-0004QT-Sh for importer@patchew.org; Thu, 06 Jun 2019 14:04:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwUB-0004a7-8G for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU7-0004Ca-GD for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:35 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:51559) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU7-00038g-7L for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:31 -0400 Received: by mail-wm1-x343.google.com with SMTP id f10so812923wmb.1 for ; Thu, 06 Jun 2019 10:46:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nNQjd9/+a2DdLghORqFl+Muzj1ZfiiJpWnJhjxjLPOE=; b=AeivwsWv6H3IMBY0RADPYPO1lUXNcmCV50EZlViQj9rpGM/zN5493L4aRJAyIaNeOQ Yk2k7qHXCL3EBHhm+2MP/CTSx7N04cQHVYJCjw2vdVFdrm0cV8X27GlCoR4O/enGbfW6 dceQC6n7721RoOitNI4VdXQsDYDs6kRXhinqLrGbGet3rek38chCJDlvg5GYjX8lUIhy zTRwZdi0U/vFTEdxajMNQ4xN9YfNnEGwTbWt0hJ0sP0cXhfiu4rhlbXam1ZjOW3yjLcB xO9N6UZdylICDPYeRQaUyT8sLJZCIlyF0BmRanSelP3XkXEk/8eI6NyQlxrsSagEdeH/ u0UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nNQjd9/+a2DdLghORqFl+Muzj1ZfiiJpWnJhjxjLPOE=; b=BVIgIu2q2bBC3tMY8BXbQMCZ4pxppaxeQ/wL+cS0R3qPHkrAAkLoy55yfxvweVfX3/ 5SZl56v1NQWDUp3kYo/icBW6p9U9Sw2v9G1+QnJcs6kI4pnnQ0teHzOWp4YoVFk1eg9S qNmQ3wRbInSLytH8zb6Nypg12PHgDBZ4MFEUASrguCJdArWbe0piCycv3y5qZhJTm2OO aZx8/b6xuPXe+OhhKzwfPnTW0GRqhmqvAHgC9fPcCz8ZWMCT7OckfYgx70LUDfdU+V8S kuLxzvSSimCepuZZrje45yIGWeQwtk5zFV87B2LojT4T8eritN0FIjgnklYNhFDHpn1y uoMA== X-Gm-Message-State: APjAAAVygJSq2JkPPwTiU8293GDnGv6EHsQ+BOpl4+XFlK7E5zSyKEdi GPCfox83CgkNRrZ/hM17UScTHg== X-Google-Smtp-Source: APXvYqwpeQ8mciG9lO53pZDwVTwx/zorKDR6VJFwTyaeMhrANtqz7/G13SAurpGczM2SGLhUJBpAwA== X-Received: by 2002:a1c:305:: with SMTP id 5mr824561wmd.101.1559843198881; Thu, 06 Jun 2019 10:46:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:52 +0100 Message-Id: <20190606174609.20487-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 25/42] target/arm: Convert VSUB to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VSUB instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 6 +----- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 14aeb25f597..12da3b8acb8 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1461,3 +1461,13 @@ static bool trans_VADD_dp(DisasContext *s, arg_VADD_= sp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, fals= e); } + +static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, fals= e); +} + +static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_sp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, fals= e); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 7fa255f6598..433f1cbf2c7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1386,7 +1386,6 @@ static inline void gen_vfp_##name(int dp) = \ tcg_temp_free_ptr(fpst); \ } =20 -VFP_OP2(sub) VFP_OP2(div) =20 #undef VFP_OP2 @@ -3110,7 +3109,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 6: + case 0 ... 7: /* Already handled by decodetree */ return 1; default: @@ -3296,9 +3295,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) for (;;) { /* Perform the calculation. */ switch (op) { - case 7: /* sub: fn - fm */ - gen_vfp_sub(dp); - break; case 8: /* div: fn / fm */ gen_vfp_div(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index d911f12dfd0..de56f44efc9 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -132,3 +132,8 @@ VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559843517; cv=none; d=zoho.com; s=zohoarc; b=COtvMWOIhWMwQGa7cSFPL6MtgD14+8wlM50dUR9rX6wnCiP7jp8p2Ap7Z3P1xk6+jOzZVsNfDVc0TNgQn6SabR7wcGse5lXYtkgAfKSHfP8mVoF6avsHbXHbfv8T5PclTsmE+k/TBGEyGLTAmwPJVWII9KvyFUCAVbpM7Ko+PsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559843517; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=/3K4w5xTobetV/OczLSlt15Lz4WijJvW66/wYpgJ/Os=; b=kTJOOLpJkvEu37B1+cCIzMJ4YKnowSFPZOcJaSBx5jxLdDBHKMkG4vcTFNQOigMt3TxYRtdPXm6Qn9BmVnd/WwKPmNO2kxbiaFQSfM5V8gwn4kzsLOYnLk55vzS6+n91J+cZjbaKWv4HcLrY2VgR3COSzWsFeywZFwhW2IQuRuk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559843517583902.0012394603148; Thu, 6 Jun 2019 10:51:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:35936 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwYO-00089K-FB for importer@patchew.org; Thu, 06 Jun 2019 13:51:56 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwTo-00047h-Fb for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwTl-0003bV-Iw for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:11 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39174) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwTj-0003A2-Qr for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:08 -0400 Received: by mail-wm1-x341.google.com with SMTP id z23so808736wma.4 for ; Thu, 06 Jun 2019 10:46:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/3K4w5xTobetV/OczLSlt15Lz4WijJvW66/wYpgJ/Os=; b=VvivHsjkIt0SLNToC5eJ3tTFbQZ/kvt+LIiLBd144+B3yhA5Q5fkCt5J49T0Yp42yj 6CIoYaq3msCfoUYY+vv1hJlKFb4CDXAe9zMXMmdJv6AO/wxlj6M68lpggO+fKGSrCYaC SAQnJewYXZG2JVW8ZE2Fx0DRJjruEFUAOFGLxQl8VpEMmd9Lb63ZytQ/jkvbXH8a59Ed AvGm3p/F3gDXC++Fa1350I0KUQaPqGBWBEnPcAMptGQiDVjzOJz2eK//Q55qs70u7irA OOPInS8CrEuTEKTpL3hKCPnMAT+GPuX3ydpBfiFITYP5xRJOQimA9//ClTXCj5v0Ctuq l5Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/3K4w5xTobetV/OczLSlt15Lz4WijJvW66/wYpgJ/Os=; b=OI6vzinGfD32jrNc8mNV2nS3FllZiKFTfCNQcKgcJ2xe+Wa66OXrBfqtuFjdh6gtVp KIQXwsI6wqEW1PVmWlMrYgIBxBMliTMguR9rxQiqskaRnKoeEy8M29VKzVOxsdfj6Fd3 JZRD9xuLzuAEoKO9ZOUPrayOwmdhwxOsFZc4Jn8aMDsZZGwIbGT9BVHLvMuaSS1NtVeK YWAkn2KeAOj+d8artcvyoUE4/sqReDAsjwcEWr0+R0icr0yERlZf8/CK4ngGQTCjIgMI 7sPca5m+j+ey8LsMbGs38J+EjtFovqHgKXUvQr/nuaRneMZt/ewr0daXQW28zXpAgqzC SxJA== X-Gm-Message-State: APjAAAUC4JqtIAbasZb5EWHUQd6PW3kOCPfpQONrJ0sglV9gg42XZ9VL Znedc8hIYd51NZE8yEihM0/KAQ== X-Google-Smtp-Source: APXvYqwAQ1KC2Nm1sUEmztvu+fWqHZoJu9/92aLtWzBL5C1R5ppap5PJWcT7YhXfaxOyciZf5Jt7Bg== X-Received: by 2002:a1c:dc45:: with SMTP id t66mr828212wmg.63.1559843199885; Thu, 06 Jun 2019 10:46:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:53 +0100 Message-Id: <20190606174609.20487-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 26/42] target/arm: Convert VDIV to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VDIV instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 21 +-------------------- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 12da3b8acb8..6af99605d5c 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1471,3 +1471,13 @@ static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_= sp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, fals= e); } + +static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, fals= e); +} + +static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_sp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 433f1cbf2c7..d35bf9d92c3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1374,22 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon) return statusptr; } =20 -#define VFP_OP2(name) \ -static inline void gen_vfp_##name(int dp) \ -{ \ - TCGv_ptr fpst =3D get_fpstatus_ptr(0); \ - if (dp) { \ - gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \ - } else { \ - gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \ - } \ - tcg_temp_free_ptr(fpst); \ -} - -VFP_OP2(div) - -#undef VFP_OP2 - static inline void gen_vfp_abs(int dp) { if (dp) @@ -3109,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 7: + case 0 ... 8: /* Already handled by decodetree */ return 1; default: @@ -3295,9 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) for (;;) { /* Perform the calculation. */ switch (op) { - case 8: /* div: fn / fm */ - gen_vfp_div(dp); - break; case 10: /* VFNMA : fd =3D muladd(-fd, fn, fm) */ case 11: /* VFNMS : fd =3D muladd(-fd, -fn, fm) */ case 12: /* VFMA : fd =3D muladd( fd, fn, fm) */ diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index de56f44efc9..de305f60e18 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -137,3 +137,8 @@ VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp +VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DYPK+P+JSUxtoNlpvBWaaa9Mw2BXlyzOlDcWjRdGGn0=; b=NbBUrf5mKw3jfcFN3ktPU9a4uSCffrdw9pHyV+1wktCRpVkyahWZJJAedIbCdYENZ0 4VFbASA3IO6v9HnOS7GuA3R7MF3wJN7fB8Q+bxAGDGRspBYmqS/ujM+T23v1Ogd3go3Y qQrJa7Od5VUp9nEBwKXSS+9vABrVFyvXh+rUOyrFvrfq30HjZcnhmmv/kLljBWw8fmYT 1HXx61AGhj8033HonupdDuaYcdp76unR9YSNl2C2SqHGYMLxLme4zJZS6lcJMhdhdM5F EDkuBMt3/7543yNpcO3IPcUHX2eUB3goW029PhOrXHn9791s+j8o+uCMkdF/ukOxIjhT SgqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DYPK+P+JSUxtoNlpvBWaaa9Mw2BXlyzOlDcWjRdGGn0=; b=iIQcOMl0eX2LCGsoJtjbnjwFtIohkjK45He/AYLG5DFJp5MkuqUNEWiXE/lx/i4eeh oXtjOJZXF7NYrbHQiwhBtZtnaNuSv1kI9FM2pnoJSaWfb7BTayP5Sx2qAKFsZKBkI6sP HPWoan+h0TGqguSAF1IB580ZA+JOfrtuxPEW92dXSUT7vvMdy52IdwMNgs2wUI12lsKi 2BLyb7ykj+YUPsR9eUzGW6mN6ywCpazXJanHsXtXrpvEJsV+KCa27tqXzKl8tBZWR+Cc 8cBN8upWadYi7irH8ja+v7sOwZNIxUT8f9igSCNMYVGGgtd4Nq7BO6o98eMbak3kY0cy qjsA== X-Gm-Message-State: APjAAAUn0PaAO2H+e3zKAThAn14sIXdjZHjsGkX14GsOrnBfXcp2cMqP bJRZq2+MSmlGbbdBEyqPhOS94w== X-Google-Smtp-Source: APXvYqy9iCSDwEMfPwGtNSqE1lbXJZ3pNvVCQJiADOqdnmsVroDrewSmXKtTaJ4B6S3Yz/wBfUS2fg== X-Received: by 2002:a5d:53d2:: with SMTP id a18mr3581270wrw.98.1559843201025; Thu, 06 Jun 2019 10:46:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:54 +0100 Message-Id: <20190606174609.20487-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PATCH 27/42] target/arm: Convert VFP fused multiply-add insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 121 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 53 +-------------- target/arm/vfp.decode | 9 +++ 3 files changed, 131 insertions(+), 52 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 6af99605d5c..ba6506a378c 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1481,3 +1481,124 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV= _sp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } + +static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) +{ + /* + * VFNMA : fd =3D muladd(-fd, fn, fm) + * VFNMS : fd =3D muladd(-fd, -fn, fm) + * VFMA : fd =3D muladd( fd, fn, fm) + * VFMS : fd =3D muladd( fd, -fn, fm) + * + * These are fused multiply-add, and must be done as one floating + * point operation with no rounding between the multiplication and + * addition steps. NB that doing the negations here as separate + * steps is correct : an input NaN should come out with its sign + * bit flipped if it is a negated-input. + */ + TCGv_ptr fpst; + TCGv_i32 vn, vm, vd; + + /* + * Present in VFPv4 only. + * In v7A, UNPREDICTABLE with non-zero vector length/stride; from + * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. + */ + if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || + (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vn =3D tcg_temp_new_i32(); + vm =3D tcg_temp_new_i32(); + vd =3D tcg_temp_new_i32(); + + neon_load_reg32(vn, a->vn); + neon_load_reg32(vm, a->vm); + if (a->o2) { + /* VFNMS, VFMS */ + gen_helper_vfp_negs(vn, vn); + } + neon_load_reg32(vd, a->vd); + if (a->o1 & 1) { + /* VFNMA, VFNMS */ + gen_helper_vfp_negs(vd, vd); + } + fpst =3D get_fpstatus_ptr(0); + gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); + neon_store_reg32(vd, a->vd); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(vn); + tcg_temp_free_i32(vm); + tcg_temp_free_i32(vd); + + return true; +} + +static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a) +{ + /* + * VFNMA : fd =3D muladd(-fd, fn, fm) + * VFNMS : fd =3D muladd(-fd, -fn, fm) + * VFMA : fd =3D muladd( fd, fn, fm) + * VFMS : fd =3D muladd( fd, -fn, fm) + * + * These are fused multiply-add, and must be done as one floating + * point operation with no rounding between the multiplication and + * addition steps. NB that doing the negations here as separate + * steps is correct : an input NaN should come out with its sign + * bit flipped if it is a negated-input. + */ + TCGv_ptr fpst; + TCGv_i64 vn, vm, vd; + + /* + * Present in VFPv4 only. + * In v7A, UNPREDICTABLE with non-zero vector length/stride; from + * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. + */ + if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || + (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x1= 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vn =3D tcg_temp_new_i64(); + vm =3D tcg_temp_new_i64(); + vd =3D tcg_temp_new_i64(); + + neon_load_reg64(vn, a->vn); + neon_load_reg64(vm, a->vm); + if (a->o2) { + /* VFNMS, VFMS */ + gen_helper_vfp_negd(vn, vn); + } + neon_load_reg64(vd, a->vd); + if (a->o1 & 1) { + /* VFNMA, VFNMS */ + gen_helper_vfp_negd(vd, vd); + } + fpst =3D get_fpstatus_ptr(0); + gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); + neon_store_reg64(vd, a->vd); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(vn); + tcg_temp_free_i64(vm); + tcg_temp_free_i64(vd); + + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index d35bf9d92c3..e8785fd26e6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3093,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 8: + case 0 ... 13: /* Already handled by decodetree */ return 1; default: @@ -3279,57 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 10: /* VFNMA : fd =3D muladd(-fd, fn, fm) */ - case 11: /* VFNMS : fd =3D muladd(-fd, -fn, fm) */ - case 12: /* VFMA : fd =3D muladd( fd, fn, fm) */ - case 13: /* VFMS : fd =3D muladd( fd, -fn, fm) */ - /* These are fused multiply-add, and must be done as o= ne - * floating point operation with no rounding between t= he - * multiplication and addition steps. - * NB that doing the negations here as separate steps = is - * correct : an input NaN should come out with its sig= n bit - * flipped if it is a negated-input. - */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { - return 1; - } - if (dp) { - TCGv_ptr fpst; - TCGv_i64 frd; - if (op & 1) { - /* VFNMS, VFMS */ - gen_helper_vfp_negd(cpu_F0d, cpu_F0d); - } - frd =3D tcg_temp_new_i64(); - tcg_gen_ld_f64(frd, cpu_env, vfp_reg_offset(dp, rd= )); - if (op & 2) { - /* VFNMA, VFNMS */ - gen_helper_vfp_negd(frd, frd); - } - fpst =3D get_fpstatus_ptr(0); - gen_helper_vfp_muladdd(cpu_F0d, cpu_F0d, - cpu_F1d, frd, fpst); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(frd); - } else { - TCGv_ptr fpst; - TCGv_i32 frd; - if (op & 1) { - /* VFNMS, VFMS */ - gen_helper_vfp_negs(cpu_F0s, cpu_F0s); - } - frd =3D tcg_temp_new_i32(); - tcg_gen_ld_f32(frd, cpu_env, vfp_reg_offset(dp, rd= )); - if (op & 2) { - gen_helper_vfp_negs(frd, frd); - } - fpst =3D get_fpstatus_ptr(0); - gen_helper_vfp_muladds(cpu_F0s, cpu_F0s, - cpu_F1s, frd, fpst); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(frd); - } - break; case 14: /* fconst */ if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return 1; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index de305f60e18..37eec0e1310 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -142,3 +142,12 @@ VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp + +VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 +VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D1 +VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ + vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D2 +VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D2 --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 28/42] target/arm: Convert VMOV (imm) to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VMOV (immediate) instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 129 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 27 +------ target/arm/vfp.decode | 5 ++ 3 files changed, 136 insertions(+), 25 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ba6506a378c..a2eeb6cb511 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1602,3 +1602,132 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_s= p *a) =20 return true; } + +static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) +{ + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i32 fd; + uint32_t n, i, vd; + + vd =3D a->vd; + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0x18; + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D s->vec_stride + 1; + } + } + + n =3D (a->imm4h << 28) & 0x80000000; + i =3D ((a->imm4h << 4) & 0x70) | a->imm4l; + if (i & 0x40) { + i |=3D 0x780; + } else { + i |=3D 0x800; + } + n |=3D i << 19; + + fd =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(fd, n); + + for (;;) { + neon_store_reg32(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + } + + tcg_temp_free_i32(fd); + return true; +} + +static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) +{ + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i64 fd; + uint32_t n, i, vd; + + vd =3D a->vd; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0xc; + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D (s->vec_stride >> 1) + 1; + } + } + + n =3D (a->imm4h << 28) & 0x80000000; + i =3D ((a->imm4h << 4) & 0x70) | a->imm4l; + if (i & 0x40) { + i |=3D 0x3f80; + } else { + i |=3D 0x4000; + } + n |=3D i << 16; + + fd =3D tcg_temp_new_i64(); + tcg_gen_movi_i64(fd, ((uint64_t)n) << 32); + + for (;;) { + neon_store_reg64(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + } + + tcg_temp_free_i64(fd); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index e8785fd26e6..38ec026d865 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3033,7 +3033,7 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, op, i, n, delta_d, delta_m, bank_mask; + uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask; int dp, veclen; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -3093,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) rn =3D VFP_SREG_N(insn); =20 switch (op) { - case 0 ... 13: + case 0 ... 14: /* Already handled by decodetree */ return 1; default: @@ -3279,29 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 14: /* fconst */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return 1; - } - - n =3D (insn << 12) & 0x80000000; - i =3D ((insn >> 12) & 0x70) | (insn & 0xf); - if (dp) { - if (i & 0x40) - i |=3D 0x3f80; - else - i |=3D 0x4000; - n |=3D i << 16; - tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32); - } else { - if (i & 0x40) - i |=3D 0x780; - else - i |=3D 0x800; - n |=3D i << 19; - tcg_gen_movi_i32(cpu_F0s, n); - } - break; case 15: /* extension space */ switch (rn) { case 0: /* cpy */ diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 37eec0e1310..1818d4f71e1 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -151,3 +151,8 @@ VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .= ... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D2 VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D2 + +VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \ + vd=3D%vd_sp +VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ + vd=3D%vd_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 29/42] target/arm: Convert VABS to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 167 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 12 ++- target/arm/vfp.decode | 5 + 3 files changed, 180 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a2eeb6cb511..d0282f1f921 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1111,6 +1111,14 @@ typedef void VFPGen3OpSPFn(TCGv_i32 vd, typedef void VFPGen3OpDPFn(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst); =20 +/* + * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp(). + * The callback should emit code to write a value to vd (which + * should be written to only). + */ +typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); +typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); + /* * Perform a 3-operand VFP data processing instruction. fn is the * callback to do the actual operation; this function deals with the @@ -1274,6 +1282,155 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, return true; } =20 +static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int = vm) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i32 f0, fd; + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0x18; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D s->vec_stride + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i32(); + fd =3D tcg_temp_new_i32(); + + neon_load_reg32(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg32(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + if (delta_m =3D=3D 0) { + /* single source one-many */ + while (veclen--) { + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + neon_store_reg32(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg32(f0, vm); + } + + tcg_temp_free_i32(f0); + tcg_temp_free_i32(fd); + + return true; +} + +static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int = vm) +{ + uint32_t delta_m =3D 0; + uint32_t delta_d =3D 0; + uint32_t bank_mask =3D 0; + int veclen =3D s->vec_len; + TCGv_i64 f0, fd; + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask =3D 0xc; + + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) =3D=3D 0) { + /* scalar */ + veclen =3D 0; + } else { + delta_d =3D (s->vec_stride >> 1) + 1; + + if ((vm & bank_mask) =3D=3D 0) { + /* mixed scalar/vector */ + delta_m =3D 0; + } else { + /* vector */ + delta_m =3D delta_d; + } + } + } + + f0 =3D tcg_temp_new_i64(); + fd =3D tcg_temp_new_i64(); + + neon_load_reg64(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg64(fd, vd); + + if (veclen =3D=3D 0) { + break; + } + + if (delta_m =3D=3D 0) { + /* single source one-many */ + while (veclen--) { + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + neon_store_reg64(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + neon_load_reg64(f0, vm); + } + + tcg_temp_free_i64(f0); + tcg_temp_free_i64(fd); + + return true; +} + static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fp= st) { /* Note that order of inputs to the add matters for NaNs */ @@ -1731,3 +1888,13 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) tcg_temp_free_i64(fd); return true; } + +static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a) +{ + return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm); +} + +static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) +{ + return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 38ec026d865..ace9f803ab7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3096,6 +3096,14 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) case 0 ... 14: /* Already handled by decodetree */ return 1; + case 15: + switch (rn) { + case 1: + /* Already handled by decodetree */ + return 1; + default: + break; + } default: break; } @@ -3104,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ - case 0x01: /* vabs */ case 0x02: /* vneg */ case 0x03: /* vsqrt */ break; @@ -3284,9 +3291,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 0: /* cpy */ /* no-op */ break; - case 1: /* abs */ - gen_vfp_abs(dp); - break; case 2: /* neg */ gen_vfp_neg(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 1818d4f71e1..7035861c270 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -156,3 +156,8 @@ VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4= l:4 \ vd=3D%vd_sp VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ vd=3D%vd_dp + +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YjVm+cX22zoyuHU03fYipUHvsizBftG/iHWYkwVfhEA=; b=eowGwb18WGDo4xD8H0ZWgGRnw2MQw0JMlxUcH0N2k4p0QBmJAtpzDuaLw+M+g+3y4o +G2o/HzlMzwzZ9EgsBsvdt++8C2KxFZm7LTjLmII28dTsKvf5Oux2KbIyY11PW7qTwCp ZWM6yoXvtLgbgZX+0GjGcy37Sz82Vs9HhWfi5XZ7dQJK7YARlwRW1dWC4aIaLTG6kIHm gfw9IPEjtIhObnuuLTyIEwenGBKIuMhnN9LWOZto1dhAdeygnAOnhfFwX7gcv+B6f54v TvuiiMiXHJ66JL+Pra0QfN+elX4OgBmYzVot6HcZCA/xnggn5vB7Rul6BqHhEnx7qdu2 Mplg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YjVm+cX22zoyuHU03fYipUHvsizBftG/iHWYkwVfhEA=; b=soHSkRgzmbms+Ca4zT/Uq5kn26p2mI/MbIOfacxdBnUTgLVC6hhbx0Is8UZdLf+JBM 5BymI8BkzUUVaKsp750n+4svgd6VMnzox9L7fJvN4RPXZ1tJWoneyKFaJUAvkNPBCevu qiw7dSHjf5VjxjYjJBEYsq6BuuhuUmd34IVsNGCckTFWTyuuOfM0iUR83+seg2AiOLul TAOgTV/UD13wF+ExwurgI4ay/2PUaWmlSFGg0DKQOI8oUGkA5c/sV/AnfDhxfywi0hEP c2wTIdihSAPa9sMxArSI/kU+WNChdGnXkOLx6QZ4nrupiNYA+h4zeH+XElZPxDCBLmn9 AWTQ== X-Gm-Message-State: APjAAAVHUtjer90tlqKriX+Yp5aD2YreShFoFQu6mf+pJmcwQsqdfOVg Vc0MmToFJ2SLllWNv5c8ov0Xt5XqAICfTg== X-Google-Smtp-Source: APXvYqwALLGDPtphcaCVv5Ve7CJ2hhdWViM1mwV+lorH3npXdDcxMxIBX2OFaDaSl22m6894AdNNAw== X-Received: by 2002:adf:dd82:: with SMTP id x2mr6457026wrl.27.1559843204615; Thu, 06 Jun 2019 10:46:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:57 +0100 Message-Id: <20190606174609.20487-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 30/42] target/arm: Convert VNEG to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VNEG instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 6 +----- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index d0282f1f921..6e06b2a130a 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1898,3 +1898,13 @@ static bool trans_VABS_dp(DisasContext *s, arg_VABS_= dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); } + +static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a) +{ + return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm); +} + +static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) +{ + return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index ace9f803ab7..cc67ab069bc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3098,7 +3098,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 1: + case 1 ... 2: /* Already handled by decodetree */ return 1; default: @@ -3112,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ - case 0x02: /* vneg */ case 0x03: /* vsqrt */ break; =20 @@ -3291,9 +3290,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 0: /* cpy */ /* no-op */ break; - case 2: /* neg */ - gen_vfp_neg(dp); - break; case 3: /* sqrt */ gen_vfp_sqrt(dp); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 7035861c270..79e41963be4 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -161,3 +161,8 @@ VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ vd=3D%vd_dp vm=3D%vm_dp + +VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844473; cv=none; d=zoho.com; s=zohoarc; b=IpuNp5lzVvNh8dZTotqU+Mw8XVERESWP9gaR664BFEH2M6RG6tmgIpONeaa5IQpOPVF4V84rqojjhovApTbJFLTalHK0HZIup73mpIh1Hz4Qt9LYlKYnfPYvnN0mt2Vkj/FVhyBqL2bTBuBA66mkDNHorNIBE5WueNVmRxGsFoI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559844473; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kCydqH+FEckzIy4SdO9TgeD3fKBJOY8MRSuCPKdNzwE=; b=YpO/Ju+ZiNzJ/rwpd1yoaTO3xZlR5pnfB9UhlLczoRh1hpLjesmPYs9STZNp8tUHpKCqHFULBYySsOD3jnI3u/SQkWqJ/06DszLt71t3SqursaHVw6B0HaZOtqvE8HJbje2TW9UrCaWRmqpQjv7hHJH6KO304654Tn2vaq/BaZY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559844473656791.7321858979105; Thu, 6 Jun 2019 11:07:53 -0700 (PDT) Received: from localhost ([127.0.0.1]:36224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwno-0007lf-Jv for importer@patchew.org; Thu, 06 Jun 2019 14:07:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwUA-0004ZE-Kg for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU7-0004CK-Dw for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:34 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:36155) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU7-0003ES-3e for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:31 -0400 Received: by mail-wr1-x444.google.com with SMTP id n4so3351152wrs.3 for ; Thu, 06 Jun 2019 10:46:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kCydqH+FEckzIy4SdO9TgeD3fKBJOY8MRSuCPKdNzwE=; b=ykq12WR9buJhLcv13TZUE5HdDi0v/cQdfbOouc+Mm+VaJNsmGmLzr+H6hbVUNm7Yxq B/ZiPTA0lEJ4KX2C/vTuwBJ2oWs3MJuhdqw9D+59/3OcMHKTKr9dJHQoPynCHpXI8euA vSC7t0lurG7BplozEm5FGamQ82UZ/qWIWiqpV6RLgWWMpSNQ9AC2sLxdPfvyDyrL6CgA Xd8hqG2itTgWIeYFIEDlJ66O1Jk8KnTUvASeAmUSBVd+2vHgCUgwIaZaXJR4TyD6oFb1 erupPwuyAxIlCXC1U1qwVOQ9L2KO3jxDmB3sZhek01EeqmdE8QHGOsZHqTm+TjafVWZy ot+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kCydqH+FEckzIy4SdO9TgeD3fKBJOY8MRSuCPKdNzwE=; b=odQiwdetq4/WjT1OtIx3LeZSbDWCqMDhYVsWpKodxG6grXb9kyIVC1daC5ERF5qRJk +RgsaZYH+YUevLUYDuIqCut9fbt6FH9ekWwGaZaq0mCghRrR7NQM6P64fBiGCgeZ0HW5 bHPU5iKXLuDTafKiNGZHIw6gyKbYi0tP47lMcMJZP+VyhaHVRd6RYJ2xAaZPb8meoOoa nlaotastpJuXU97UYJ6C8kyDxbssHFdcOL1e903xw22AnntiayJb+oRFTwxdUmEsNq1f COIkd8T6pCo6q4fEn5L9ThfeBbO4J9J7kkd9EuOdWfQP81Un6g/3TjeZiC1Mz2i1sH8q 7sHg== X-Gm-Message-State: APjAAAWe9w2Fv52rm2j3Mf+Z1snhMV2FLPzxTY6DJOeJFvQ5CJhpsStq M9F5xRMVkruZ5Q0aSOSq5J+qFhU/mXmipQ== X-Google-Smtp-Source: APXvYqzUFKgRUW0HVU1mESlLHoyIT6eGangEybkNYM8CA0t/vpCZrIOQBKPGD3igN7X+x9cSp3KgMA== X-Received: by 2002:adf:db12:: with SMTP id s18mr6006866wri.335.1559843205858; Thu, 06 Jun 2019 10:46:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:58 +0100 Message-Id: <20190606174609.20487-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 31/42] target/arm: Convert VSQRT to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VSQRT instruction to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 20 ++++++++++++++++++++ target/arm/translate.c | 14 +------------- target/arm/vfp.decode | 5 +++++ 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 6e06b2a130a..ae2f77a873b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1908,3 +1908,23 @@ static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_= dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); } + +static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) +{ + gen_helper_vfp_sqrts(vd, vm, cpu_env); +} + +static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a) +{ + return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm); +} + +static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) +{ + gen_helper_vfp_sqrtd(vd, vm, cpu_env); +} + +static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a) +{ + return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index cc67ab069bc..fda0962761f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1390,14 +1390,6 @@ static inline void gen_vfp_neg(int dp) gen_helper_vfp_negs(cpu_F0s, cpu_F0s); } =20 -static inline void gen_vfp_sqrt(int dp) -{ - if (dp) - gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); - else - gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); -} - static inline void gen_vfp_cmp(int dp) { if (dp) @@ -3098,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 1 ... 2: + case 1 ... 3: /* Already handled by decodetree */ return 1; default: @@ -3112,7 +3104,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ - case 0x03: /* vsqrt */ break; =20 case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */ @@ -3290,9 +3281,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 0: /* cpy */ /* no-op */ break; - case 3: /* sqrt */ - gen_vfp_sqrt(dp); - break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ { TCGv_ptr fpst =3D get_fpstatus_ptr(false); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 79e41963be4..2780e1ed9ea 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -166,3 +166,8 @@ VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ vd=3D%vd_dp vm=3D%vm_dp + +VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tJUsST+aGlhOT8pqIZXKH+UcDOpMGU+FNgpH8UqWdjI=; b=bN/xsLRzT8Q84/gf511fQfvi31EeHwKExgk767yOQlU8rI8utj7kWWk8Prx5bBTCFe bqxp8zuGngk5WDInm13pyrOagQT9xOaMapl1GMJSql/AhXgly34CjJNrEb/5oQsPeJgK 1OyYle+Ehn4nu+h3Kt+hQWvYe+95rRZ1eSonlrJpvJyE8uS6EmSzRuFOBsM5vBPRrmye nT7RKx/nw6y47GOZFPndFvm0C969LpiMMNyW+DxgOZVmkxwIDCQHLEjHqHsBVQUnCubl gX9Oq2qTQu2TdMp5ULOXsS/LPeMTiLNCKX941Qg05TrY1LlEp20Fx8dfwWb+OVNrOFOe ApTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tJUsST+aGlhOT8pqIZXKH+UcDOpMGU+FNgpH8UqWdjI=; b=eZ4O4N4X7h7Gp4+UQYZl+QxB3VjyyYQbKSlJg3eWZps25HQxUwyhHDiSwrAaJqb7K4 wBCtUknB9CpcMYqdv2ONmbRSKiU0nwfTSwR/6xncnUsJhSy6jQdDvzoeTW8QWUmy9LM0 8xJ01AHDiuS+zpF7d7c6uBK6v53zJXRH0/e0KOa9HL8QGYLkw/opWKhP8/cBkqj0f5Zo mp3ZlEHtYgnn4KAlpC5icVTOgslUnJ9v0SWHM95m3V9YFlTqUcPAmiktZDSwnc8htraW 5XQ2e7vSoKN1qmJYACHE9vbBsp6dQxQUXZwxmlwcoYdZR00EazceiGVqKl83GTmq2Z3h OZ9A== X-Gm-Message-State: APjAAAXCn2/pOsbhjXsiqmibotzke6jcF79TkQu/r6jW7iMTnn5UMBFo OsJm8Op6fV2/iCX9Mip+krXB8w== X-Google-Smtp-Source: APXvYqyGY5/i6QRBuA/py8ffunh6piU7AYVExNp7vxZigcM/By4154AEfJtkQcjdDI2cMA/qy613vQ== X-Received: by 2002:a5d:42c5:: with SMTP id t5mr15941360wrr.5.1559843206924; Thu, 06 Jun 2019 10:46:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:59 +0100 Message-Id: <20190606174609.20487-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 32/42] target/arm: Convert VMOV (register) to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 10 ++++++++++ target/arm/translate.c | 8 +------- target/arm/vfp.decode | 5 +++++ 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ae2f77a873b..a7e4ae31985 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1889,6 +1889,16 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return true; } =20 +static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a) +{ + return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm); +} + +static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a) +{ + return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm); +} + static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a) { return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm); diff --git a/target/arm/translate.c b/target/arm/translate.c index fda0962761f..639e0f5f91e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3090,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 1 ... 3: + case 0 ... 3: /* Already handled by decodetree */ return 1; default: @@ -3103,9 +3103,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x00: /* vmov */ - break; - case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */ case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */ /* @@ -3278,9 +3275,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) switch (op) { case 15: /* extension space */ switch (rn) { - case 0: /* cpy */ - /* no-op */ - break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ { TCGv_ptr fpst =3D get_fpstatus_ptr(false); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 2780e1ed9ea..b72ab8b8067 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -157,6 +157,11 @@ VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm= 4l:4 \ VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ vd=3D%vd_dp =20 +VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp + VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ELVX9mpiICAoImlyrSnIvE4rv+CnGilnkJ9v9OB0C0U=; b=MIInXsNNAaSFb6PofaMJwA4MeJu+v0IyO8pnsEA+M818y01TKkItqztMPaChV733Tx nJnksToTB+tP4YsNp5YBG+bBOidrgHWuqkbZz2wdxe8Q5KMXidlb9WqOj+efaaiGo6gq KG/LwmsdYVqkUKEUi4tBnWK50qSQ2U5EFh+B7TCWc2zj7AZEetOts2SCGV23ZW0sF65G wnno0WnOeMvKmMnLwr/OnaZdOMv329VKP4N/q/5QE9zyFX2pDoGRUUi02wgg4EtwYDao hFrKCZbHKxuDLVNsBPcI8jWyg+RtcUHao+KxFKRMNwhu1e7wUZnroslZZ1aSUXj8JrDX iomQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ELVX9mpiICAoImlyrSnIvE4rv+CnGilnkJ9v9OB0C0U=; b=lkl6sXS0mBB8h6+wIcXH3Ky8YciD9SfNrJmQ8RwVippmkw9lFI5MV0YBZGL3wO8O7j 3UWQzXMHOgCc61GpySxtNR90HFAYW2peT5k7U19OvlhDCpmawqqmZtwZTS6pvljF8GLK etjeuIbvg9cAbf5fGlmpdrF5ajiQAYPeR12aGFGF9+iHVvA/ijGsIGVzCFT/aY7d+NVI oIHktU74/4oSr6gVyk8y0VDgJ562ANwOr49T2nZzlpPNLCFkET1ZSnaLGU1pfyjgwcmp wFeMWA82/v4Poe99doY8a1EgTdHrfUkAIub0z2egyeJ9EawwlOvW7Uf/N9eOJj26oHaQ N/tA== X-Gm-Message-State: APjAAAVNIETmk3cEsLVbbH7AG2tAOU7+9yIUlZSHNcplPOJhksw3V21H 7D6XPeGVoIHlRVhA2+sSsqwlIyxgaHPcLg== X-Google-Smtp-Source: APXvYqxRyNmkp2do+nFr5UmhpWOLHk8D2Qzkp+UXqfG7obvGPoUoWxCQG1Ck62EPvGcoEh7RYgOZeA== X-Received: by 2002:a7b:cb48:: with SMTP id v8mr803177wmj.108.1559843208078; Thu, 06 Jun 2019 10:46:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:00 +0100 Message-Id: <20190606174609.20487-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 33/42] target/arm: Convert VFP comparison insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP comparison instructions to decodetree. Note that comparison instructions should not honour the VFP short-vector length and stride information: they are scalar-only operations. This applies to all the 2-operand instructions except for VMOV, VABS, VNEG and VSQRT. (In the old decoder this is implemented via the "if (op =3D=3D 15 && rn > 3) { veclen =3D 0; }" check.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 67 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 51 +------------------------- target/arm/vfp.decode | 5 +++ 3 files changed, 73 insertions(+), 50 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a7e4ae31985..872b01621cc 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1938,3 +1938,70 @@ static bool trans_VSQRT_dp(DisasContext *s, arg_VSQR= T_dp *a) { return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); } + +static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) +{ + TCGv_i32 vd, vm; + + /* Vm/M bits must be zero for the Z variant */ + if (a->z && a->vm !=3D 0) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd =3D tcg_temp_new_i32(); + vm =3D tcg_temp_new_i32(); + + neon_load_reg32(vd, a->vd); + if (a->z) { + tcg_gen_movi_i32(vm, 0); + } else { + neon_load_reg32(vm, a->vm); + } + + if (a->e) { + gen_helper_vfp_cmpes(vd, vm, cpu_env); + } else { + gen_helper_vfp_cmps(vd, vm, cpu_env); + } + return true; +} + +static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) +{ + TCGv_i64 vd, vm; + + /* Vm/M bits must be zero for the Z variant */ + if (a->z && a->vm !=3D 0) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd =3D tcg_temp_new_i64(); + vm =3D tcg_temp_new_i64(); + + neon_load_reg64(vd, a->vd); + if (a->z) { + tcg_gen_movi_i64(vm, 0); + } else { + neon_load_reg64(vm, a->vm); + } + + if (a->e) { + gen_helper_vfp_cmped(vd, vm, cpu_env); + } else { + gen_helper_vfp_cmpd(vd, vm, cpu_env); + } + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 639e0f5f91e..26994e0d427 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1390,30 +1390,6 @@ static inline void gen_vfp_neg(int dp) gen_helper_vfp_negs(cpu_F0s, cpu_F0s); } =20 -static inline void gen_vfp_cmp(int dp) -{ - if (dp) - gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); - else - gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); -} - -static inline void gen_vfp_cmpe(int dp) -{ - if (dp) - gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); - else - gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); -} - -static inline void gen_vfp_F1_ld0(int dp) -{ - if (dp) - tcg_gen_movi_i64(cpu_F1d, 0); - else - tcg_gen_movi_i32(cpu_F1s, 0); -} - #define VFP_GEN_ITOF(name) \ static inline void gen_vfp_##name(int dp, int neon) \ { \ @@ -3091,6 +3067,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 15: switch (rn) { case 0 ... 3: + case 8 ... 11: /* Already handled by decodetree */ return 1; default: @@ -3135,11 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) rd_is_dp =3D false; break; =20 - case 0x08: case 0x0a: /* vcmp, vcmpz */ - case 0x09: case 0x0b: /* vcmpe, vcmpez */ - no_output =3D true; - break; - case 0x0c: /* vrintr */ case 0x0d: /* vrintz */ case 0x0e: /* vrintx */ @@ -3240,14 +3212,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) /* Load the initial operands. */ if (op =3D=3D 15) { switch (rn) { - case 0x08: case 0x09: /* Compare */ - gen_mov_F0_vreg(dp, rd); - gen_mov_F1_vreg(dp, rm); - break; - case 0x0a: case 0x0b: /* Compare with zero */ - gen_mov_F0_vreg(dp, rd); - gen_vfp_F1_ld0(dp); - break; case 0x14: /* vcvt fp <-> fixed */ case 0x15: case 0x16: @@ -3357,19 +3321,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) gen_vfp_msr(tmp); break; } - case 8: /* cmp */ - gen_vfp_cmp(dp); - break; - case 9: /* cmpe */ - gen_vfp_cmpe(dp); - break; - case 10: /* cmpz */ - gen_vfp_cmp(dp); - break; - case 11: /* cmpez */ - gen_vfp_F1_ld0(dp); - gen_vfp_cmpe(dp); - break; case 12: /* vrintr */ { TCGv_ptr fpst =3D get_fpstatus_ptr(0); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index b72ab8b8067..9db7aa7021a 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -176,3 +176,8 @@ VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ vd=3D%vd_dp vm=3D%vm_dp + +VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 82 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 56 +---------------------- target/arm/vfp.decode | 6 +++ 3 files changed, 89 insertions(+), 55 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 872b01621cc..3ad93cc48f4 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -30,6 +30,26 @@ #include "decode-vfp.inc.c" #include "decode-vfp-uncond.inc.c" =20 +/* + * Return the offset of a 16-bit half of the specified VFP single-precision + * register. If top is true, returns the top 16 bits; otherwise the bottom + * 16 bits. + */ +static inline long vfp_f16_offset(unsigned reg, bool top) +{ + long offs =3D vfp_reg_offset(false, reg); +#ifdef HOST_WORDS_BIGENDIAN + if (!top) { + offs +=3D 2; + } +#else + if (top) { + offs +=3D 2; + } +#endif + return offs; +} + /* * Check that VFP access is enabled. If it is, do the necessary * M-profile lazy-FP handling and then return true. @@ -2005,3 +2025,65 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) } return true; } + +static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + ahp_mode =3D get_ahp_flag(); + tmp =3D tcg_temp_new_i32(); + /* The T bit tells us if we want the low or high 16 bits of Vm */ + tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + TCGv_i64 vd; + + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + ahp_mode =3D get_ahp_flag(); + tmp =3D tcg_temp_new_i32(); + /* The T bit tells us if we want the low or high 16 bits of Vm */ + tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + vd =3D tcg_temp_new_i64(); + gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + tcg_temp_free_i64(vd); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 26994e0d427..65e69873654 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3066,7 +3066,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 3: + case 0 ... 5: case 8 ... 11: /* Already handled by decodetree */ return 1; @@ -3080,24 +3080,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */ - case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */ - /* - * VCVTB, VCVTT: only present with the halfprec extens= ion - * UNPREDICTABLE if bit 8 is set prior to ARMv8 - * (we choose to UNDEF) - */ - if (dp) { - if (!dc_isar_feature(aa32_fp16_dpconv, s)) { - return 1; - } - } else { - if (!dc_isar_feature(aa32_fp16_spconv, s)) { - return 1; - } - } - rm_is_dp =3D false; - break; case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */ case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */ if (dp) { @@ -3239,42 +3221,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(false); - TCGv_i32 ahp_mode =3D get_ahp_flag(); - tmp =3D gen_vfp_mrs(); - tcg_gen_ext16u_i32(tmp, tmp); - if (dp) { - gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - fpst, ahp_mode); - } else { - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - fpst, ahp_mode); - } - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - break; - } - case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(false); - TCGv_i32 ahp =3D get_ahp_flag(); - tmp =3D gen_vfp_mrs(); - tcg_gen_shri_i32(tmp, tmp, 16); - if (dp) { - gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp, - fpst, ahp); - } else { - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, - fpst, ahp); - } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - break; - } case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ { TCGv_ptr fpst =3D get_fpstatus_ptr(false); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 9db7aa7021a..53d9544f7cd 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -181,3 +181,9 @@ VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .= ... \ vd=3D%vd_sp vm=3D%vm_sp VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_dp + +# VCVTT and VCVTB from f16: Vd format depends on size bit; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T8dalXGNHmxlBlWh+OiCcc7lIFztXGrOob93cvWGYJo=; b=rckAy9wuRpm9ndEk89Ia4Cat+MDcGXxFHNXHYVpHq8ca2fR7l4CVN4O4nXykW42a99 vVqfgJV5P71nxxA6PreoyF3b0CjibKNoFaX4cjF6XKBNUYXzVM54I7tndWmQguXRswZs yT5O3UKqzhMEce2DwBO1Q0M/RRHBq8z85mf5thOwwtzQWODJN4Wxy5BJItXdAuZYya4e HUephacWp549tPSRQrQ7dH3/tIyOQuZ55b4fpgdNcDuvIaa4thl7DJD5iqin1c52sRup VXkN+SCk1iwZ/dkh9cOLo60253iT2uelNEbX+DWRwC0JIi1gEpxvoqgITaZ9S+KV3ExF Zf4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T8dalXGNHmxlBlWh+OiCcc7lIFztXGrOob93cvWGYJo=; b=IYgZMjes0Jj85NI3me8ZPxvn0HTWb3mTK0mbg6tzGw5dQHBBZEg3QlgcvN9ytoB/CW myBlZ38LhO9Rs4iVcGkc3za5ChvQDZhppLUjO9ecZ+xcRJloYWBRpQ9EecWbBSOeu6sw KacP9T4rOfHeVJ/yXGWDQ1Dgtz46v3f9lduyr0OymTuW18uK/hkZ2F2+IwEK7obNiE0K VwQGYrToWFgfsWnBvTgyTXlt9ufk8wBjLoUtklGI3+hhblq1zBkJmnnc7s6pzA/dKGZb j8rQ3W3AhCHxY20r3oXLNW8BpqT3RG/1q6aEcqwDUsdB7Disx8PUo0fLRhtjJAwiKSYK yJJQ== X-Gm-Message-State: APjAAAVTkv9vPxWo+kCXOkpF7G1EVaCDWzshyn2p9SqzWAYFDyTfyIKw cQMOvLQu0gMFNFohTc8VDU14Qg== X-Google-Smtp-Source: APXvYqxJCmxEwurXvgyaUOBeti8Bgs+T5hN5dZnjJeTtn86FMBsnvq5jMpyuN5O+0Fh4bNMmIFz2pw== X-Received: by 2002:a5d:4904:: with SMTP id x4mr3808601wrq.337.1559843210172; Thu, 06 Jun 2019 10:46:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:02 +0100 Message-Id: <20190606174609.20487-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 35/42] target/arm: Convert the VCVT-to-f16 insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVTT and VCVTB instructions which convert from f32 and f64 to f16 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit store of the right half of the input single-precision register rather than doing a load/modify/store sequence on the full 32 bits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 62 ++++++++++++++++++++++++++ target/arm/translate.c | 79 +--------------------------------- target/arm/vfp.decode | 6 +++ 3 files changed, 69 insertions(+), 78 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3ad93cc48f4..d2ae148ca69 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2087,3 +2087,65 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) tcg_temp_free_i64(vd); return true; } + +static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + ahp_mode =3D get_ahp_flag(); + tmp =3D tcg_temp_new_i32(); + + neon_load_reg32(tmp, a->vm); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); + tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + TCGv_i64 vm; + + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + ahp_mode =3D get_ahp_flag(); + tmp =3D tcg_temp_new_i32(); + vm =3D tcg_temp_new_i64(); + + neon_load_reg64(vm, a->vm); + gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); + tcg_temp_free_i64(vm); + tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 65e69873654..3edcd7beff3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2963,20 +2963,6 @@ static int disas_dsp_insn(DisasContext *s, uint32_t = insn) #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) =20 -/* Move between integer and VFP cores. */ -static TCGv_i32 gen_vfp_mrs(void) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_F0s); - return tmp; -} - -static void gen_vfp_msr(TCGv_i32 tmp) -{ - tcg_gen_mov_i32(cpu_F0s, tmp); - tcg_temp_free_i32(tmp); -} - static void gen_neon_dup_low16(TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -3003,8 +2989,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) { uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask; int dp, veclen; - TCGv_i32 tmp; - TCGv_i32 tmp2; =20 if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { return 1; @@ -3066,8 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 5: - case 8 ... 11: + case 0 ... 11: /* Already handled by decodetree */ return 1; default: @@ -3080,20 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */ - case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */ - if (dp) { - if (!dc_isar_feature(aa32_fp16_dpconv, s)) { - return 1; - } - } else { - if (!dc_isar_feature(aa32_fp16_spconv, s)) { - return 1; - } - } - rd_is_dp =3D false; - break; - case 0x0c: /* vrintr */ case 0x0d: /* vrintz */ case 0x0e: /* vrintx */ @@ -3221,52 +3190,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(false); - TCGv_i32 ahp =3D get_ahp_flag(); - tmp =3D tcg_temp_new_i32(); - - if (dp) { - gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - fpst, ahp); - } else { - gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - fpst, ahp); - } - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - gen_mov_F0_vreg(0, rd); - tmp2 =3D gen_vfp_mrs(); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - gen_vfp_msr(tmp); - break; - } - case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(false); - TCGv_i32 ahp =3D get_ahp_flag(); - tmp =3D tcg_temp_new_i32(); - if (dp) { - gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d, - fpst, ahp); - } else { - gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, - fpst, ahp); - } - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - tcg_gen_shli_i32(tmp, tmp, 16); - gen_mov_F0_vreg(0, rd); - tmp2 =3D gen_vfp_mrs(); - tcg_gen_ext16u_i32(tmp2, tmp2); - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - gen_vfp_msr(tmp); - break; - } case 12: /* vrintr */ { TCGv_ptr fpst =3D get_fpstatus_ptr(0); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 53d9544f7cd..b88d1d06f02 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -187,3 +187,9 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 ....= \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_sp + +# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on = size bit +VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=46/bfSh4qTs1HLqCmXNVzF6OG+uw62+U38VNlBMJ2qI=; b=cOSoUsYM+G2KfYZGf4O4+ZCJ0BrLVsGeHhwA7/LaH9nT2CjN81UD++uN+YUsy1IrKG /zgWsHljek2DtOL+8qspdf7ZL8G7qSyQIGJsuzcdUVhdl4TY9FCMcu7MQQd75VngW0L2 oMxhW8O841JZf5ydfZghNxx6+YCAPLKg3WBIuYAueYShWppk0RpHXRlQYuudKBHN2wcd JEn9h5V4c8hTOlssDbCFwQHdvtOzGmpzNPDyXnYxoBc3Bh6ppjxDfOM7R/fHns8Ip7Ex uEYxeH8ZFLG1OcniK+gqLYCc2YIBDTSOP7kQ5QGBNPiQs/Ajd+B3IEDT8pE2dFMeUnDp 2RTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=46/bfSh4qTs1HLqCmXNVzF6OG+uw62+U38VNlBMJ2qI=; b=YgFoGtDqzo65DUKU80+AQvy1qPW+sEA5ANq9T9MbUe2DGnWZN4oSP++yu0EdejRiFb zrhUtGrCgwXQgIQAUpEPU16kGhnU/XMf1Et2SH6TbJRuttzFHzoT9cdumsiIWR4V4BIn W6yb1/4As4PLw+k7rG78XNzu1zgmzgq9XLSmmiFFa7tTNkK/SL88rO+Y0iaECN61zYmK WlH/7iXL670jxCSycPEP2uyF/h5us7G6FR3i69t5ikqasQ73IYkOEd1tqlYtxgCWBvN6 fccsk2K66hlRnVQLBc0kcEAQxRd2y8GUQhXuPRtFQGr6dlhSe1PF2Qk/edP1L0HavV80 50Vg== X-Gm-Message-State: APjAAAUxuzxw9/aPo73a5jnwBy/Q5JLpFyEAX4kjmXR4RWpAa/eprFSq amNwI01TlMPseV+rfbZV/elyDg== X-Google-Smtp-Source: APXvYqwRJgtSe5qWJ4fapndd9iXgRDGdj4jGQGZAnQhvzZKjCCza7ubmMiApDf4gtqoCiIgSOXvNpA== X-Received: by 2002:a5d:4a0b:: with SMTP id m11mr21176615wrq.251.1559843211397; Thu, 06 Jun 2019 10:46:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:03 +0100 Message-Id: <20190606174609.20487-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 36/42] target/arm: Convert VFP round insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 163 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 45 +-------- target/arm/vfp.decode | 15 +++ 3 files changed, 179 insertions(+), 44 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index d2ae148ca69..5768be40c3e 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2149,3 +2149,166 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg= _VCVT_f16_f64 *a) tcg_temp_free_i32(tmp); return true; } + +static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + gen_helper_rints(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_sp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + gen_helper_rintd(tmp, tmp, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + TCGv_i32 tcg_rmode; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + tcg_rmode =3D tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_rints(tmp, tmp, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_sp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + TCGv_i32 tcg_rmode; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + tcg_rmode =3D tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_rintd(tmp, tmp, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + tcg_temp_free_i32(tcg_rmode); + return true; +} + +static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + gen_helper_rints_exact(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst =3D get_fpstatus_ptr(false); + gen_helper_rintd_exact(tmp, tmp, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3edcd7beff3..e7831bf8abb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 11: + case 0 ... 14: /* Already handled by decodetree */ return 1; default: @@ -3063,11 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x0c: /* vrintr */ - case 0x0d: /* vrintz */ - case 0x0e: /* vrintx */ - break; - case 0x0f: /* vcvt double<->single */ rd_is_dp =3D !dp; break; @@ -3190,44 +3185,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 12: /* vrintr */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(0); - if (dp) { - gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); - } else { - gen_helper_rints(cpu_F0s, cpu_F0s, fpst); - } - tcg_temp_free_ptr(fpst); - break; - } - case 13: /* vrintz */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(0); - TCGv_i32 tcg_rmode; - tcg_rmode =3D tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - if (dp) { - gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); - } else { - gen_helper_rints(cpu_F0s, cpu_F0s, fpst); - } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_ptr(fpst); - break; - } - case 14: /* vrintx */ - { - TCGv_ptr fpst =3D get_fpstatus_ptr(0); - if (dp) { - gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst); - } else { - gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst); - } - tcg_temp_free_ptr(fpst); - break; - } case 15: /* single<->double conversion */ if (dp) { gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_en= v); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index b88d1d06f02..9942d2ae7ad 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -193,3 +193,18 @@ VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 ...= . \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp + +VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp + +VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ + vd=3D%vd_dp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fqQD45cISRBPqS8e6LTFUDKMsysfUAaIcXUmuocZRaE=; b=nkQYzNXNHDbWLrVXlPKFKH8LPdS9LPj+vnqLLyPUAAlocrmVHkUs+kd129b+gxnOE8 BLfekcL4snvSKQVCkmzUKg0tYbnl6Cpyud01MJhGGJU8FuofNs1uTBgMuq/ROFmiJTdG WlYrkeDDOqaGQT374lN1X3AbCFsGOIetX29DbVAq2NypysWNp79jM0/Wn48kk8fJUj9Y Hmee2K90jE85soQnje5kP6RcLJWAQuzRQVI82PPzB7AqJytHt6UivCLmA5qh82TWQjEw Vxx0bYzW36jxRbYElZO4PnfhQvx/gdVoAcPBtVakfpYvibz2Df7zFE3CwgaCHOmoSIbV orng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fqQD45cISRBPqS8e6LTFUDKMsysfUAaIcXUmuocZRaE=; b=gwsVA2aEePyouwqEIv5QyyjZTuRwUL0vzaGYo1C1oBWxaVGib9ROJOgm09cn0zFTUS EipNmdru1vk8g8LJs3y9+/AKIGdkayv4Jo00/d4YSlDETvGRq/rtWqxB5hW3f72p0O6I KyJobZfgf9HvWtp/ENQCU/rCIbGC9/oTizuQ+5B+qUeRFSTH+fsGd5NsLsgGu/01RJXL 6oS+PdQNyqt2TMCNjPs4S/rRvqCw6LzT1VFyddsG6gb9fP2zLWtflPxiGc2CCp8M129g iRuRubTmgekjcQSzIeF4kJvUkFLBf/2KHFeAWN1wC18X7KrbrMe+af97S25cSUlcu/kR HQDg== X-Gm-Message-State: APjAAAUf8H6/gNTvkFj8pimLX3z7ab0mKHASSZyy9ninLt3tbaRdcspz EpFBJwui+hkqEOuN41FRNWFWeQ== X-Google-Smtp-Source: APXvYqylZxEi4Eu9XFYAYN1iyFEU1FOn+E00RTXKnqrw0zWDIW+K9r7gSCBPfx7nKZ+0aPC46dYsFA== X-Received: by 2002:a5d:4603:: with SMTP id t3mr7683795wrq.315.1559843212359; Thu, 06 Jun 2019 10:46:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:04 +0100 Message-Id: <20190606174609.20487-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 37/42] target/arm: Convert double-single precision conversion insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVT double/single precision conversion insns to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 48 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 13 +-------- target/arm/vfp.decode | 6 +++++ 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 5768be40c3e..c4bf1249ee7 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2312,3 +2312,51 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) tcg_temp_free_i64(tmp); return true; } + +static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) +{ + TCGv_i64 vd; + TCGv_i32 vm; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm =3D tcg_temp_new_i32(); + vd =3D tcg_temp_new_i64(); + neon_load_reg32(vm, a->vm); + gen_helper_vfp_fcvtds(vd, vm, cpu_env); + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_i64(vd); + return true; +} + +static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) +{ + TCGv_i64 vm; + TCGv_i32 vd; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd =3D tcg_temp_new_i32(); + vm =3D tcg_temp_new_i64(); + neon_load_reg64(vm, a->vm); + gen_helper_vfp_fcvtsd(vd, vm, cpu_env); + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i64(vm); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index e7831bf8abb..2902bb7488e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 14: + case 0 ... 15: /* Already handled by decodetree */ return 1; default: @@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x0f: /* vcvt double<->single */ - rd_is_dp =3D !dp; - break; - case 0x10: /* vcvt.fxx.u32 */ case 0x11: /* vcvt.fxx.s32 */ rm_is_dp =3D false; @@ -3185,13 +3181,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 15: /* single<->double conversion */ - if (dp) { - gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_en= v); - } else { - gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_en= v); - } - break; case 16: /* fuito */ gen_vfp_uito(dp, 0); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 9942d2ae7ad..56b8b4e6046 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -208,3 +208,9 @@ VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ vd=3D%vd_dp vm=3D%vm_dp + +# VCVT between single and double: Vm precision depends on size; Vd is its = reverse +VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ + vd=3D%vd_dp vm=3D%vm_sp +VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B1+wWB3rNTZOHORyna/i52K8oN8xz+ryKjDaxSUmMDA=; b=ecqYYTIQnIUj7UQd/KwDb1Q7NNl45yDpRczzlOxXe96+kym6+CWpNHlhxAATXAGPPY HTH0fzH/D70LcofczuEjlPSP1ZtQTF7sp7z6zbLf08RqYUk2nIiefCHLIEcST0/HyoYk FJapHVzRAtJIrm/ZkpjwGTNjg+vK1uczHF9iyPZhfOMjbMuYQh1F/xoZ7gwzEwsY04sw Zoj6gI7NGUCcdmvQlQHPpCbofqNSFoQeq+rkxjUoxZIEZlD88yJlaihDRu2p5hOxhi+g m6FEDiMGvGivOMEJ4uIAEjcDy2d9HxVUND44WntuG7Q01kOqf0jqHb+/xx/n5FbfeRqD zWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B1+wWB3rNTZOHORyna/i52K8oN8xz+ryKjDaxSUmMDA=; b=nv9VTp7O2D2O9CVoQ7jDDmDfF9IL9a6XPfMKmbBhAnyWU/raQWlE++WmPgUJ7ahnuO NynZpB2BJYtm37kHCJZZ1n5lzvdIQfuNe8id9P37iLPxrtlKpsqPVAOXf0JeeqCmvnxY //uy2ogNm/Udu8kdtoyVMeUxi6Hq2tvOgwpmh5Zd8ey25P2hjzTC0OveWBPGHPl5+qaL dLt2t0KvNvU1xGe0En39t+B3D91GFrTgxklCV2uQjkpaGWXMxBVp5V8DG4/ChGNHSeTp n74UYVziiKEOotkXkYT4oX+M/+Dk3HVEZGzcRha8jYnSkK2hSepyzrcyyP1QPURTWJxH /DAA== X-Gm-Message-State: APjAAAVtp+q+afvxJyZxH8O8rQYQn/Xb9nuvtCfpfxqBGLclehQirql6 Cf/1BbdA2a7cwTjKBotMg9SoyU6EWm8qAg== X-Google-Smtp-Source: APXvYqy2gYAMbTYLUsZEGJLLRaf+4m38k0LChRzw6LG18+Dmk+uaH4ugGAe0lzN8ojtpxUlixigaEw== X-Received: by 2002:a5d:6949:: with SMTP id r9mr15936279wrw.73.1559843213416; Thu, 06 Jun 2019 10:46:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:05 +0100 Message-Id: <20190606174609.20487-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 38/42] target/arm: Convert integer-to-float insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVT integer-to-float instructions to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 58 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 12 +------ target/arm/vfp.decode | 6 ++++ 3 files changed, 65 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index c4bf1249ee7..e5b5c3cd6a5 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2360,3 +2360,61 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_= dp *a) tcg_temp_free_i64(vm); return true; } + +static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!vfp_access_check(s)) { + return true; + } + + vm =3D tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + fpst =3D get_fpstatus_ptr(false); + if (a->s) { + /* i32 -> f32 */ + gen_helper_vfp_sitos(vm, vm, fpst); + } else { + /* u32 -> f32 */ + gen_helper_vfp_uitos(vm, vm, fpst); + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) +{ + TCGv_i32 vm; + TCGv_i64 vd; + TCGv_ptr fpst; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm =3D tcg_temp_new_i32(); + vd =3D tcg_temp_new_i64(); + neon_load_reg32(vm, a->vm); + fpst =3D get_fpstatus_ptr(false); + if (a->s) { + /* i32 -> f64 */ + gen_helper_vfp_sitod(vd, vm, fpst); + } else { + /* u32 -> f64 */ + gen_helper_vfp_uitod(vd, vm, fpst); + } + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_i64(vd); + tcg_temp_free_ptr(fpst); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 2902bb7488e..b98f8f103ae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 15: + case 0 ... 17: /* Already handled by decodetree */ return 1; default: @@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) if (op =3D=3D 15) { /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { - case 0x10: /* vcvt.fxx.u32 */ - case 0x11: /* vcvt.fxx.s32 */ - rm_is_dp =3D false; - break; case 0x18: /* vcvtr.u32.fxx */ case 0x19: /* vcvtz.u32.fxx */ case 0x1a: /* vcvtr.s32.fxx */ @@ -3181,12 +3177,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 16: /* fuito */ - gen_vfp_uito(dp, 0); - break; - case 17: /* fsito */ - gen_vfp_sito(dp, 0); - break; case 19: /* vjcvt */ gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 56b8b4e6046..6da9a7913da 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -214,3 +214,9 @@ VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ vd=3D%vd_dp vm=3D%vm_sp VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +# VCVT from integer to floating point: Vm always single; Vd depends on size +VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ + vd=3D%vd_dp vm=3D%vm_sp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559844909; cv=none; d=zoho.com; s=zohoarc; b=h2KhtEraYIAVte1pXLOAXuCakG7yFEptROrcabWXe4hZokUeO1e0NkI1JIDs7esGSfw6/JVZ5rZVDqaceRJRKS95Dsl46qiBAZlPjJPlFuw0OX45rsUIjWJGEHwgCpbiw+P2549jYx8clwUl10kKrXlIvMpaoUkLdtqr9mvFKTY= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wS5685L1Ipovmuag8NGIyla+uLm909fdDbELT7NCVTo=; b=kO6gxBgDunxYaZYyfKx8QunKxrUrtFymb5DZKMA+mF68gHnV4hwKkXnfMBI59daABS TZBOaekNzRVCX0ycFJJDphkMuE97oQmykGnSOaK/GnTc3OrRfS9j5Nt+yXjYWmDQu3TS l/76AYhz8P6dSaX6x+7UMGvWRVnTRtQxn7Z9XYt/Zxg6vhKARprQ31CK0oJ2amhX6gxm +v+29d7HIOeoJdLtHR94VfqqhrlKWVFgAn3I/PULwq6CIRFNFjHIcvTehds++sNyYF2A vz0By02ix9QAfEru/QnA/fXf7juJheAcpK6knH7VaMc2QkCDLeGBzK5l4SMB6lYKbv+c RqRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wS5685L1Ipovmuag8NGIyla+uLm909fdDbELT7NCVTo=; b=Z4U0wC+avdIjgplEq+AogN1LDCF2lDdi4PkErekV7n2kU1AnDS4j4g1V7bwmihIUxQ ZHQCmSn5oGYgeEq4TMotdHhrOTP3a5Gk2AUb4qGh+CbN94JwajVXnbtmOJt+N/MauTR3 HlegVPC+K8SUrUlrhHLmWkSVbLxinkvNkUDSPs4g06K6BTtAOF5qCa3tD0D2ju5QPTlC 9lHXIgb/lZrAdXF0LI6/IPznwkVPZKrDdpp+Gq+GzJEeeSzbXOad1Ydre6Rp+vqKmQvI zs+LZ9M7szKITlXBjPZBWgzlEWHU0gele0GNLiU1IaxTti3UBQHdo8AkHfbt5fwNjLRL ye7g== X-Gm-Message-State: APjAAAW96NWYGW7lWxeXctA1FgAbwqbyXzLyCCbO/4L/ByX7S9U/0xYF hCH+Gmih9YY60JZbKD+yt5sNOg== X-Google-Smtp-Source: APXvYqxbfAWoYXCI3CL0fLime6srXUnBOiQ36w4KNtyJYj3arxTKIHbhw+VF5yAxsnPKGdtJ6OG7Mg== X-Received: by 2002:adf:dd82:: with SMTP id x2mr6457485wrl.27.1559843214449; Thu, 06 Jun 2019 10:46:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:06 +0100 Message-Id: <20190606174609.20487-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 39/42] target/arm: Convert VJCVT to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VJCVT instruction to decodetree. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 24 ++++++++++++++++++++++++ target/arm/translate.c | 12 +----------- target/arm/vfp.decode | 4 ++++ 3 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e5b5c3cd6a5..9bc852076a0 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2418,3 +2418,27 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_V= CVT_int_dp *a) tcg_temp_free_ptr(fpst); return true; } + +static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) +{ + TCGv_i32 vd; + TCGv_i64 vm; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm =3D tcg_temp_new_i64(); + vd =3D tcg_temp_new_i32(); + neon_load_reg64(vm, a->vm); + gen_helper_vjcvt(vd, vm, cpu_env); + neon_store_reg32(vd, a->vd); + tcg_temp_free_i64(vm); + tcg_temp_free_i32(vd); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index b98f8f103ae..687ef093f97 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 17: + case 0 ... 19: /* Already handled by decodetree */ return 1; default: @@ -3085,13 +3085,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) rm_is_dp =3D false; break; =20 - case 0x13: /* vjcvt */ - if (!dp || !dc_isar_feature(aa32_jscvt, s)) { - return 1; - } - rd_is_dp =3D false; - break; - default: return 1; } @@ -3177,9 +3170,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) switch (op) { case 15: /* extension space */ switch (rn) { - case 19: /* vjcvt */ - gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env); - break; case 20: /* fshto */ gen_vfp_shto(dp, 16 - rm, 0); break; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 6da9a7913da..1a7c9b533de 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -220,3 +220,7 @@ VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 ....= \ vd=3D%vd_sp vm=3D%vm_sp VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_sp + +# VJCVT is always dp to sp +VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ + vd=3D%vd_sp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 40/42] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 124 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 57 +-------------- target/arm/vfp.decode | 10 +++ 3 files changed, 136 insertions(+), 55 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 9bc852076a0..80804ebff90 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2442,3 +2442,127 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT = *a) tcg_temp_free_i32(vd); return true; } + +static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) +{ + TCGv_i32 vd, shift; + TCGv_ptr fpst; + int frac_bits; + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + frac_bits =3D (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); + + vd =3D tcg_temp_new_i32(); + neon_load_reg32(vd, a->vd); + + fpst =3D get_fpstatus_ptr(false); + shift =3D tcg_const_i32(frac_bits); + + /* Switch on op:U:sx bits */ + switch (a->opc) { + case 0: + gen_helper_vfp_shtos(vd, vd, shift, fpst); + break; + case 1: + gen_helper_vfp_sltos(vd, vd, shift, fpst); + break; + case 2: + gen_helper_vfp_uhtos(vd, vd, shift, fpst); + break; + case 3: + gen_helper_vfp_ultos(vd, vd, shift, fpst); + break; + case 4: + gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst); + break; + case 5: + gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst); + break; + case 6: + gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst); + break; + case 7: + gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst); + break; + default: + g_assert_not_reached(); + } + + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i32(shift); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) +{ + TCGv_i64 vd; + TCGv_i32 shift; + TCGv_ptr fpst; + int frac_bits; + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + frac_bits =3D (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); + + vd =3D tcg_temp_new_i64(); + neon_load_reg64(vd, a->vd); + + fpst =3D get_fpstatus_ptr(false); + shift =3D tcg_const_i32(frac_bits); + + /* Switch on op:U:sx bits */ + switch (a->opc) { + case 0: + gen_helper_vfp_shtod(vd, vd, shift, fpst); + break; + case 1: + gen_helper_vfp_sltod(vd, vd, shift, fpst); + break; + case 2: + gen_helper_vfp_uhtod(vd, vd, shift, fpst); + break; + case 3: + gen_helper_vfp_ultod(vd, vd, shift, fpst); + break; + case 4: + gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst); + break; + case 5: + gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst); + break; + case 6: + gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst); + break; + case 7: + gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst); + break; + default: + g_assert_not_reached(); + } + + neon_store_reg64(vd, a->vd); + tcg_temp_free_i64(vd); + tcg_temp_free_i32(shift); + tcg_temp_free_ptr(fpst); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 687ef093f97..16c24aafc98 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1439,13 +1439,9 @@ static inline void gen_vfp_##name(int dp, int shift,= int neon) \ tcg_temp_free_i32(tmp_shift); \ tcg_temp_free_ptr(statusptr); \ } -VFP_GEN_FIX(tosh, _round_to_zero) VFP_GEN_FIX(tosl, _round_to_zero) -VFP_GEN_FIX(touh, _round_to_zero) VFP_GEN_FIX(toul, _round_to_zero) -VFP_GEN_FIX(shto, ) VFP_GEN_FIX(slto, ) -VFP_GEN_FIX(uhto, ) VFP_GEN_FIX(ulto, ) #undef VFP_GEN_FIX =20 @@ -3050,7 +3046,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) return 1; case 15: switch (rn) { - case 0 ... 19: + case 0 ... 23: + case 28 ... 31: /* Already handled by decodetree */ return 1; default: @@ -3070,21 +3067,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) rd_is_dp =3D false; break; =20 - case 0x14: /* vcvt fp <-> fixed */ - case 0x15: - case 0x16: - case 0x17: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return 1; - } - /* Immediate frac_bits has same format as SREG_M. */ - rm_is_dp =3D false; - break; - default: return 1; } @@ -3143,17 +3125,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) /* Load the initial operands. */ if (op =3D=3D 15) { switch (rn) { - case 0x14: /* vcvt fp <-> fixed */ - case 0x15: - case 0x16: - case 0x17: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - /* Source and destination the same. */ - gen_mov_F0_vreg(dp, rd); - break; default: /* One source operand. */ gen_mov_F0_vreg(rm_is_dp, rm); @@ -3170,18 +3141,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) switch (op) { case 15: /* extension space */ switch (rn) { - case 20: /* fshto */ - gen_vfp_shto(dp, 16 - rm, 0); - break; - case 21: /* fslto */ - gen_vfp_slto(dp, 32 - rm, 0); - break; - case 22: /* fuhto */ - gen_vfp_uhto(dp, 16 - rm, 0); - break; - case 23: /* fulto */ - gen_vfp_ulto(dp, 32 - rm, 0); - break; case 24: /* ftoui */ gen_vfp_toui(dp, 0); break; @@ -3194,18 +3153,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) case 27: /* ftosiz */ gen_vfp_tosiz(dp, 0); break; - case 28: /* ftosh */ - gen_vfp_tosh(dp, 16 - rm, 0); - break; - case 29: /* ftosl */ - gen_vfp_tosl(dp, 32 - rm, 0); - break; - case 30: /* ftouh */ - gen_vfp_touh(dp, 16 - rm, 0); - break; - case 31: /* ftoul */ - gen_vfp_toul(dp, 32 - rm, 0); - break; default: /* undefined */ g_assert_not_reached(); } diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 1a7c9b533de..c3223a124ac 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -224,3 +224,13 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 ...= . \ # VJCVT is always dp to sp VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +# VCVT between floating-point and fixed-point. The immediate value +# is in the same format as a Vm single-precision register number. +# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field +# for the convenience of the trans_VCVT_fix functions. +%vcvt_fix_op 18:1 16:1 7:1 +VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ + vd=3D%vd_sp imm=3D%vm_sp opc=3D%vcvt_fix_op +VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ + vd=3D%vd_dp imm=3D%vm_sp opc=3D%vcvt_fix_op --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559845408; cv=none; d=zoho.com; s=zohoarc; b=TdS5cU3AvT4vixJ09e5ORA5jJAc3hEV1qZORNNZYJ2T1DOIj3irlgdxKW4dKHD1o3NMqpOQzmb9Zu3f4hRChmw6pTlWUxN3IzOVeHpnPLJH3RimPLt2FbILstJVvwiojqz5rlrEyXFfFSQSexrGrtFqPmR7qORNE9UC3gSaSXn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559845408; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BgQRGZdD+nntS+gM5xgt+/km/72hSxW1ESAV32KdFGw=; b=LmWBiM7HUMKCfvGOhlyreePhHjtfRa70Yn8AdlBCttvVoFnJv9xEMHIwDry7xSMZA1pl0gsg7YfQIV5+LpIZHwtkvxKd3xifJSiv27Tr5DyDtP/tfRrtm0z2YAt2dREX4xHo2mA9nHNEZVM6JMYPRgfSZrAnIp+M7z3jZDbSmpY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559845408177624.1417444029693; Thu, 6 Jun 2019 11:23:28 -0700 (PDT) Received: from localhost ([127.0.0.1]:36509 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYx2k-0006Ah-LH for importer@patchew.org; Thu, 06 Jun 2019 14:23:18 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYwUG-0004ft-Bs for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYwU8-0004GE-Ju for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:40 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:41009) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYwU8-0003Ob-4p for qemu-devel@nongnu.org; Thu, 06 Jun 2019 13:47:32 -0400 Received: by mail-wr1-x441.google.com with SMTP id c2so3327547wrm.8 for ; Thu, 06 Jun 2019 10:46:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BgQRGZdD+nntS+gM5xgt+/km/72hSxW1ESAV32KdFGw=; b=FziAatUmJZkBf7dDGOco4UfbiAoMnXwb0qck2+tDo/Ugxv78pNNiA3GcVDuM+hq3gp wLMGjDhpA4GdRFNJnKvYoHvupEP/AohEySXRCoPjNdVBJEJNluyC4u3+wzKy2I5IwsU8 xHtw6zJhGH0XNB/EjDvoCu3CIU+lPfUJMRmrPBFo/xwcZSNmCfOtbx+e0k+LnLTzg+Ed oGuqn+IDneezN+8QrdDlRlxADz0UVegIo6QDEZyPd3kIcEnUyl0Bc4FC/xQ/9z39wrGT RMvC+4NDW3xkvDv4OeRE8KhU3XxiCz1PaAqqNmxz5prvZ636vnEtjJ8wK5EnaCB/Pniw xysQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BgQRGZdD+nntS+gM5xgt+/km/72hSxW1ESAV32KdFGw=; b=LxXlVq2Hf4XHf3hXJruBeCJcNhniS6SQMKAX6xjqyMBfWKHKShDqSYUqY0T3bng3Bf rHM/LiGzHAKUxOckha3qZU0L/gMC9ZMHBJJ/IJTuUlV3VVs9/ay2fMHz5v0RMANqFdUs WthZNOfhFf4qJGwLWGLu4mrnHFbojzITyAEWEclR5gmvrouALUuOFbZzpQi+VWdcDrYV m+YqUKeqv5iCyKGBjoWonJfrRG/u/uhHPxKfdHrSj4TLV83EzkfJnUEdgJKzpAXLafpP 6aqQ2n761K2zrhA6piGbsV9fLQqRkEPTfSFQ+pEqopf9/LfXZ6zzazP+PBQFCaPXdCmi OqDA== X-Gm-Message-State: APjAAAXozKj0FGleImZ1e/gDNcOJeaxngu1NC0GOBWMGuJJD3aX2c/fd uNeMNceMoXeNcdKa77ttWKkStg== X-Google-Smtp-Source: APXvYqw0DYPs/PVtD/TBb2hbBAM7aF8GsJnkOPObCNrfYsyAfjopYBIRvh5AJHoeD/qC4r1utvG4PQ== X-Received: by 2002:adf:db81:: with SMTP id u1mr29648035wri.296.1559843216913; Thu, 06 Jun 2019 10:46:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:08 +0100 Message-Id: <20190606174609.20487-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 41/42] target/arm: Convert float-to-integer VCVT insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 72 ++++++++++ target/arm/translate.c | 241 +-------------------------------- target/arm/vfp.decode | 6 + 3 files changed, 80 insertions(+), 239 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 80804ebff90..90bc23ef773 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2566,3 +2566,75 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) tcg_temp_free_ptr(fpst); return true; } + +static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + vm =3D tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizs(vm, vm, fpst); + } else { + gen_helper_vfp_tosis(vm, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizs(vm, vm, fpst); + } else { + gen_helper_vfp_touis(vm, vm, fpst); + } + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) +{ + TCGv_i32 vd; + TCGv_i64 vm; + TCGv_ptr fpst; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst =3D get_fpstatus_ptr(false); + vm =3D tcg_temp_new_i64(); + vd =3D tcg_temp_new_i32(); + neon_load_reg64(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizd(vd, vm, fpst); + } else { + gen_helper_vfp_tosid(vd, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizd(vd, vm, fpst); + } else { + gen_helper_vfp_touid(vd, vm, fpst); + } + } + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i64(vm); + tcg_temp_free_ptr(fpst); + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 16c24aafc98..b999ce7a4ac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1418,9 +1418,7 @@ static inline void gen_vfp_##name(int dp, int neon) \ tcg_temp_free_ptr(statusptr); \ } =20 -VFP_GEN_FTOI(toui) VFP_GEN_FTOI(touiz) -VFP_GEN_FTOI(tosi) VFP_GEN_FTOI(tosiz) #undef VFP_GEN_FTOI =20 @@ -1612,33 +1610,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) } =20 #define tcg_gen_ld_f32 tcg_gen_ld_i32 -#define tcg_gen_ld_f64 tcg_gen_ld_i64 #define tcg_gen_st_f32 tcg_gen_st_i32 -#define tcg_gen_st_f64 tcg_gen_st_i64 - -static inline void gen_mov_F0_vreg(int dp, int reg) -{ - if (dp) - tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); -} - -static inline void gen_mov_F1_vreg(int dp, int reg) -{ - if (dp) - tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); -} - -static inline void gen_mov_vreg_F0(int dp, int reg) -{ - if (dp) - tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); - else - tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); -} =20 #define ARM_CP_RW_BIT (1 << 20) =20 @@ -2983,9 +2955,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask; - int dp, veclen; - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { return 1; } @@ -3005,214 +2974,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) return 0; } } - - if (extract32(insn, 28, 4) =3D=3D 0xf) { - /* - * Encodings with T=3D1 (Thumb) or unconditional (ARM): these - * were all handled by the decodetree decoder, so any insn - * patterns which get here must be UNDEF. - */ - return 1; - } - - /* - * FIXME: this access check should not take precedence over UNDEF - * for invalid encodings; we will generate incorrect syndrome informat= ion - * for attempts to execute invalid vfp/neon encodings with FP disabled. - */ - if (!vfp_access_check(s)) { - return 0; - } - - dp =3D ((insn & 0xf00) =3D=3D 0xb00); - switch ((insn >> 24) & 0xf) { - case 0xe: - if (insn & (1 << 4)) { - /* already handled by decodetree */ - return 1; - } else { - /* data processing */ - bool rd_is_dp =3D dp; - bool rm_is_dp =3D dp; - bool no_output =3D false; - - /* The opcode is in bits 23, 21, 20 and 6. */ - op =3D ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) = & 1); - rn =3D VFP_SREG_N(insn); - - switch (op) { - case 0 ... 14: - /* Already handled by decodetree */ - return 1; - case 15: - switch (rn) { - case 0 ... 23: - case 28 ... 31: - /* Already handled by decodetree */ - return 1; - default: - break; - } - default: - break; - } - - if (op =3D=3D 15) { - /* rn is opcode, encoded as per VFP_SREG_N. */ - switch (rn) { - case 0x18: /* vcvtr.u32.fxx */ - case 0x19: /* vcvtz.u32.fxx */ - case 0x1a: /* vcvtr.s32.fxx */ - case 0x1b: /* vcvtz.s32.fxx */ - rd_is_dp =3D false; - break; - - default: - return 1; - } - } else if (dp) { - /* rn is register number */ - VFP_DREG_N(rn, insn); - } - - if (rd_is_dp) { - VFP_DREG_D(rd, insn); - } else { - rd =3D VFP_SREG_D(insn); - } - if (rm_is_dp) { - VFP_DREG_M(rm, insn); - } else { - rm =3D VFP_SREG_M(insn); - } - - veclen =3D s->vec_len; - if (op =3D=3D 15 && rn > 3) { - veclen =3D 0; - } - - /* Shut up compiler warnings. */ - delta_m =3D 0; - delta_d =3D 0; - bank_mask =3D 0; - - if (veclen > 0) { - if (dp) - bank_mask =3D 0xc; - else - bank_mask =3D 0x18; - - /* Figure out what type of vector operation this is. */ - if ((rd & bank_mask) =3D=3D 0) { - /* scalar */ - veclen =3D 0; - } else { - if (dp) - delta_d =3D (s->vec_stride >> 1) + 1; - else - delta_d =3D s->vec_stride + 1; - - if ((rm & bank_mask) =3D=3D 0) { - /* mixed scalar/vector */ - delta_m =3D 0; - } else { - /* vector */ - delta_m =3D delta_d; - } - } - } - - /* Load the initial operands. */ - if (op =3D=3D 15) { - switch (rn) { - default: - /* One source operand. */ - gen_mov_F0_vreg(rm_is_dp, rm); - break; - } - } else { - /* Two source operands. */ - gen_mov_F0_vreg(dp, rn); - gen_mov_F1_vreg(dp, rm); - } - - for (;;) { - /* Perform the calculation. */ - switch (op) { - case 15: /* extension space */ - switch (rn) { - case 24: /* ftoui */ - gen_vfp_toui(dp, 0); - break; - case 25: /* ftouiz */ - gen_vfp_touiz(dp, 0); - break; - case 26: /* ftosi */ - gen_vfp_tosi(dp, 0); - break; - case 27: /* ftosiz */ - gen_vfp_tosiz(dp, 0); - break; - default: /* undefined */ - g_assert_not_reached(); - } - break; - default: /* undefined */ - return 1; - } - - /* Write back the result, if any. */ - if (!no_output) { - gen_mov_vreg_F0(rd_is_dp, rd); - } - - /* break out of the loop if we have finished */ - if (veclen =3D=3D 0) { - break; - } - - if (op =3D=3D 15 && delta_m =3D=3D 0) { - /* single source one-many */ - while (veclen--) { - rd =3D ((rd + delta_d) & (bank_mask - 1)) - | (rd & bank_mask); - gen_mov_vreg_F0(dp, rd); - } - break; - } - /* Setup the next operands. */ - veclen--; - rd =3D ((rd + delta_d) & (bank_mask - 1)) - | (rd & bank_mask); - - if (op =3D=3D 15) { - /* One source operand. */ - rm =3D ((rm + delta_m) & (bank_mask - 1)) - | (rm & bank_mask); - gen_mov_F0_vreg(dp, rm); - } else { - /* Two source operands. */ - rn =3D ((rn + delta_d) & (bank_mask - 1)) - | (rn & bank_mask); - gen_mov_F0_vreg(dp, rn); - if (delta_m) { - rm =3D ((rm + delta_m) & (bank_mask - 1)) - | (rm & bank_mask); - gen_mov_F1_vreg(dp, rm); - } - } - } - } - break; - case 0xc: - case 0xd: - /* Already handled by decodetree */ - return 1; - default: - /* Should never happen. */ - return 1; - } - return 0; + /* If the decodetree decoder didn't handle this insn, it must be UNDEF= */ + return 1; } =20 static inline bool use_goto_tb(DisasContext *s, target_ulong dest) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index c3223a124ac..ea24365bb4c 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -234,3 +234,9 @@ VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ vd=3D%vd_sp imm=3D%vm_sp opc=3D%vcvt_fix_op VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ vd=3D%vd_dp imm=3D%vm_sp opc=3D%vcvt_fix_op + +# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on = size +VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_sp +VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ + vd=3D%vd_sp vm=3D%vm_dp --=20 2.20.1 From nobody Wed Dec 17 04:17:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OPmJIDS5EQ/XYTrJS7IKfgCnnuP6L+oh/wc5ZioeaMA=; b=YAP0P6+0NIZjQep8hUx2ZRVvPOX2BPiGfh5a2k2s2Rq1di8HrpM1voHArcgjT/rBC+ qCbD1EsmKp1/o0lwtRemDDiREMl5QiQOYdk3BXunLB70qF7j7yH+L+MYQ6JQOH0QbC+w l9Su/02YGlOrQ5HiGMLupJgdc2OmG4cPOC7SOVv1ce6F3ORESdL+3DVhAy8AxDCJNKBc A9ezFuJwmtXzPX/OnA/0o9rmruy58t7D9Iz3TNxu0LffXhnUitufChLesfZK/O9n5UDL RGSqeNVHZaqPL/QU/aU4YKDwn3iace2pNlGXThMROUC7Wr4lRriQZeEVa5HYrLrUl7bu bNVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OPmJIDS5EQ/XYTrJS7IKfgCnnuP6L+oh/wc5ZioeaMA=; b=nc3L/JNYoK2p1H0WdEm23zaNQucUVGCbUe9v2EchTxT5aoj/t13nxtQyeIIFDEQ/SI Xj0ZjgjamDz6WoKHrGtDI9o/c51CRJsKw058fYUhOBEk7WM1jBPgVbCOUEBOrrmJMm5C vJNLBkU9bRFoAmkNLGPgmM1WjduKf5nGtLVk1k44SvVcPkMYZRYyY0NWR+Ci09ApoUWo cdbP6BVmmNSkkQ9y9JF2ofqJMdcVz6NSPduwMI4RCtbtQZpboBjhz3Y1Te1vHLwyXdMf ceBwFonDwQJR0hJa9T+QSWFA6OGxLQgvCyGzxx49gT6HV3NBN/PcqmShB1ByC7AFQAg1 JLuw== X-Gm-Message-State: APjAAAXkg6Gx7u2MO8pKtJ8BYLa4H7U8eCJzJwTKQNhSvJ9QsnRjOt7z Qo6dPrJy5GKIjdYM/q/4w2rS3g== X-Google-Smtp-Source: APXvYqza78vRv1VdlV46zO8iPVj8g7XFAy1jZDRndXnGI90mLGZpQp40V+OIYKyhkv1gjtRt+nwcgg== X-Received: by 2002:a5d:6b03:: with SMTP id v3mr10985542wrw.309.1559843218047; Thu, 06 Jun 2019 10:46:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:46:09 +0100 Message-Id: <20190606174609.20487-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 42/42] target/arm: Fix short-vector increment behaviour X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask =3D 0xc), if we start with vd =3D 6 and delta_d =3D 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 100 ++++++++++++++++++++------------- 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 90bc23ef773..baeea14d56f 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1139,6 +1139,42 @@ typedef void VFPGen3OpDPFn(TCGv_i64 vd, typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); =20 +/* + * Return true if the specified S reg is in a scalar bank + * (ie if it is s0..s7) + */ +static inline bool vfp_sreg_is_scalar(int reg) +{ + return (reg & 0x18) =3D=3D 0; +} + +/* + * Return true if the specified D reg is in a scalar bank + * (ie if it is d0..d3 or d16..d19) + */ +static inline bool vfp_dreg_is_scalar(int reg) +{ + return (reg & 0xc) =3D=3D 0; +} + +/* + * Advance the S reg number forwards by delta within its bank + * (ie increment the low 3 bits but leave the rest the same) + */ +static inline int vfp_advance_sreg(int reg, int delta) +{ + return ((reg + delta) & 0x7) | (reg & ~0x7); +} + +/* + * Advance the D reg number forwards by delta within its bank + * (ie increment the low 2 bits but leave the rest the same) + */ +static inline int vfp_advance_dreg(int reg, int delta) +{ + return ((reg + delta) & 0x3) | (reg & ~0x3); +} + /* * Perform a 3-operand VFP data processing instruction. fn is the * callback to do the actual operation; this function deals with the @@ -1149,7 +1185,6 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpS= PFn *fn, { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 f0, f1, fd; TCGv_ptr fpst; @@ -1164,16 +1199,14 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, } =20 if (veclen > 0) { - bank_mask =3D 0x18; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D s->vec_stride + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1204,11 +1237,11 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); + vn =3D vfp_advance_sreg(vn, delta_d); neon_load_reg32(f0, vn); if (delta_m) { - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vm =3D vfp_advance_sreg(vm, delta_m); neon_load_reg32(f1, vm); } } @@ -1226,7 +1259,6 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 f0, f1, fd; TCGv_ptr fpst; @@ -1246,16 +1278,14 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, } =20 if (veclen > 0) { - bank_mask =3D 0xc; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D (s->vec_stride >> 1) + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1285,11 +1315,11 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, } /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vn =3D ((vn + delta_d) & (bank_mask - 1)) | (vn & bank_mask); + vd =3D vfp_advance_dreg(vd, delta_d); + vn =3D vfp_advance_dreg(vn, delta_d); neon_load_reg64(f0, vn); if (delta_m) { - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vm =3D vfp_advance_dreg(vm, delta_m); neon_load_reg64(f1, vm); } } @@ -1306,7 +1336,6 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 @@ -1320,16 +1349,14 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2O= pSPFn *fn, int vd, int vm) } =20 if (veclen > 0) { - bank_mask =3D 0x18; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D s->vec_stride + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1355,7 +1382,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) if (delta_m =3D=3D 0) { /* single source one-many */ while (veclen--) { - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + vd =3D vfp_advance_sreg(vd, delta_d); neon_store_reg32(fd, vd); } break; @@ -1363,8 +1390,8 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); + vm =3D vfp_advance_sreg(vm, delta_m); neon_load_reg32(f0, vm); } =20 @@ -1378,7 +1405,6 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) { uint32_t delta_m =3D 0; uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 @@ -1397,16 +1423,14 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) } =20 if (veclen > 0) { - bank_mask =3D 0xc; - /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { delta_d =3D (s->vec_stride >> 1) + 1; =20 - if ((vm & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vm)) { /* mixed scalar/vector */ delta_m =3D 0; } else { @@ -1432,7 +1456,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) if (delta_m =3D=3D 0) { /* single source one-many */ while (veclen--) { - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mas= k); + vd =3D vfp_advance_dreg(vd, delta_d); neon_store_reg64(fd, vd); } break; @@ -1440,8 +1464,8 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); - vm =3D ((vm + delta_m) & (bank_mask - 1)) | (vm & bank_mask); + vd =3D vfp_advance_dreg(vd, delta_d); + vd =3D vfp_advance_dreg(vm, delta_m); neon_load_reg64(f0, vm); } =20 @@ -1783,7 +1807,6 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp = *a) static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) { uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i32 fd; uint32_t n, i, vd; @@ -1804,9 +1827,8 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) } =20 if (veclen > 0) { - bank_mask =3D 0x18; /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_sreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { @@ -1835,7 +1857,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vd =3D vfp_advance_sreg(vd, delta_d); } =20 tcg_temp_free_i32(fd); @@ -1845,7 +1867,6 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) { uint32_t delta_d =3D 0; - uint32_t bank_mask =3D 0; int veclen =3D s->vec_len; TCGv_i64 fd; uint32_t n, i, vd; @@ -1871,9 +1892,8 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) } =20 if (veclen > 0) { - bank_mask =3D 0xc; /* Figure out what type of vector operation this is. */ - if ((vd & bank_mask) =3D=3D 0) { + if (vfp_dreg_is_scalar(vd)) { /* scalar */ veclen =3D 0; } else { @@ -1902,7 +1922,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 /* Set up the operands for the next iteration */ veclen--; - vd =3D ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + vfp_advance_dreg(vd, delta_d); } =20 tcg_temp_free_i64(fd); --=20 2.20.1