From nobody Mon Feb 9 08:56:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559768345; cv=none; d=zoho.com; s=zohoarc; b=VGKAU4ig8b3HBwPROGDrLBupJga7u9RWMRg2CytIR35rwd1bv9pnJlfiJZCKn7q0jh0b+Lq2EzPXFMCgIEPIh16x94VW+I3g8ej7fkqgippyp6y+DRLQFD7u8fsVnrfhQ9t7HAxPDQE2+KEJwr1PQRk/EipDSjNJLV5U54Q2lQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559768345; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sxdSheH5ONNDctOIrrKCa9iTD3q6YA9fWWU9OaB3NP8=; b=LfU4T0ipM+yyDsJgkR+COd+RvZ7PLOfZ+gkJJJOfDnJuVAidFQXFsTOF/EiKS4BEU0i/8IzTMOW0884MVg+0u+oLvap19jX2fS7yluV02g1T9GLntDrGNHZCXX0FknyKY17SikmET0cDOcD3Kd3Lbzp5CO6syaGO7fRXsIsUMV8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559768345554401.2281658141786; Wed, 5 Jun 2019 13:59:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:49897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYczm-0007F7-25 for importer@patchew.org; Wed, 05 Jun 2019 16:58:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYcdP-0003uG-OU for qemu-devel@nongnu.org; Wed, 05 Jun 2019 16:35:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYcdM-0008Lz-Ln for qemu-devel@nongnu.org; Wed, 05 Jun 2019 16:35:47 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49064) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYcdM-0006wd-8z; Wed, 05 Jun 2019 16:35:44 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F240730860A3; Wed, 5 Jun 2019 20:35:00 +0000 (UTC) Received: from t460s.redhat.com (ovpn-116-124.ams2.redhat.com [10.36.116.124]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6F749619A9; Wed, 5 Jun 2019 20:34:59 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 22:33:55 +0200 Message-Id: <20190605203403.29461-26-david@redhat.com> In-Reply-To: <20190605203403.29461-1-david@redhat.com> References: <20190605203403.29461-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Wed, 05 Jun 2019 20:35:01 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL SUBSYSTEM s390x 25/33] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index e86ade9e44..fa2e801747 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1240,6 +1240,8 @@ F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC) /* VECTOR FP MULTIPLY AND SUBTRACT */ F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC) +/* VECTOR FP PERFORM SIGN OPERATION */ + F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC) =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index b624c7a8aa..9b8606ba25 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -2727,3 +2727,55 @@ static DisasJumpType op_vfma(DisasContext *s, DisasO= ps *o) 0, fn); return DISAS_NEXT; } + +static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 =3D get_field(s->fields, v1); + const uint8_t v2 =3D get_field(s->fields, v2); + const uint8_t fpf =3D get_field(s->fields, m3); + const uint8_t m4 =3D get_field(s->fields, m4); + const uint8_t m5 =3D get_field(s->fields, m5); + TCGv_i64 tmp; + + if (fpf !=3D FPF_LONG || extract32(m4, 0, 3) || m5 > 2) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m4, 3, 1)) { + tmp =3D tcg_temp_new_i64(); + read_vec_element_i64(tmp, v2, 0, ES_64); + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + tcg_gen_xori_i64(tmp, tmp, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + tcg_gen_ori_i64(tmp, tmp, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1); + break; + } + write_vec_element_i64(tmp, v1, 0, ES_64); + tcg_temp_free_i64(tmp); + } else { + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1); + break; + } + } + return DISAS_NEXT; +} --=20 2.21.0