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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 37/39] tcg/aarch64: Use LDP to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This changes the code generation for the tlb from e.g. ldur x0, [x19, #0xffffffffffffffe0] ldur x1, [x19, #0xffffffffffffffe8] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] to ldp x0, x1, [x19, #-0x20] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes. --- tcg/aarch64/tcg-target.inc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 57c297f9d7..b0f8106642 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1641,6 +1641,10 @@ static void add_qemu_ldst_label(TCGContext *s, bool = is_ld, TCGMemOpIdx oi, QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); =20 +/* These offsets are built into the LDP below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finali= zing the slow path. Generated code returns the host addend in X1, @@ -1649,23 +1653,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0, x3; + TCGReg x3; TCGType mask_type; uint64_t compare_mask; =20 mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); =20 /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, --=20 2.17.1