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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.33.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SsD841efZqo7uciuvvdZgxC3XyiWIUZWbge19pY103g=; b=KvFhHb3SAShtgHAUjH5dqVDJqyjIl8If/pMPiuRNI9c8DBuTUIonor4lXyQHWwUvzI jJ16f3R+Si68LJPYUARZ5kis6dOukRny8PmscbO4vlQ5kcww4ze6dEKZ4MOawxoieHmd 7AJ6iJlIjh9fdzY/XIQnU8Y12e4wFqtWeI91Ah1x78HNM6iwzr43Waz398KZr7WsT63G rgTkc/8y2NeAKNme8m5bl0VtJrFEfoSjGRTDYzWTcvK6iKMwFED+lkfWUWHAbjBXXWrx Udt0m0py2GYJWhJ1awF/VrsrlLMs8bv1rjsdwAjgbtCAfK72S4i2cPsiCREzqAq8VjMq oRSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SsD841efZqo7uciuvvdZgxC3XyiWIUZWbge19pY103g=; b=GttKA2EL+DItZ09Sq3fAg9kHT25jeUWoExtzbhoq5dLLFBj4Tb6C6FXJ2ZkCwxzlgK ttkOUpVKveDXgfaTlmppEDS5pjxNo1JkEIoqpPN1SQpNt2Rhy+2SPmF8yx9pSszUodF9 rkL0Rux4Yjfa0Dto+yl37ARlqv/Ydj4JvWxoTblm2MuqQiGWvIYLt4Iaz9K8g/X/kD/W 8qc5GykRK2dmSrYy0kwWflpOYd5dUVD4cnlGibtWQEnXoD0pDDAd/8UlD5SM3vXd2UJS dgjqcsbHklIcNsZVSun3/0jZpOkBrHjm3XiReWZPgQRkFwBOX3MMipf9wL1k+jl0bd4r OxAA== X-Gm-Message-State: APjAAAXq4uNtFiza7eAFj1X98CedApAzj1T9n7Xu31S2kFuppteoKqFs 0DBemvLkCJaHtXr6E8hDqarlTazXispYwg== X-Google-Smtp-Source: APXvYqx6X1YmYVinTn4WPjQRdsjrBsWOrrsHldQ+RN0PhZfeX3Rc/3AfKYarTGqgsKKRH8XRiNTykA== X-Received: by 2002:aca:5b57:: with SMTP id p84mr5549475oib.4.1559680436510; Tue, 04 Jun 2019 13:33:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:13 -0500 Message-Id: <20190604203351.27778-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH v4 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Both structures are allocated once per mmu_idx. There is no reason for them to be separate. Reviewed-by: Alistair Francis Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 17 ++++------------- accel/tcg/cputlb.c | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8f2a848bf5..52d150aaf1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -127,18 +127,6 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 -/** - * struct CPUTLBWindow - * @begin_ns: host time (in ns) at the beginning of the time window - * @max_entries: maximum number of entries observed in the window - * - * See also: tlb_mmu_resize_locked() - */ -typedef struct CPUTLBWindow { - int64_t begin_ns; - size_t max_entries; -} CPUTLBWindow; - typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -148,9 +136,12 @@ typedef struct CPUTLBDesc { */ target_ulong large_page_addr; target_ulong large_page_mask; + /* host time (in ns) at the beginning of the time window */ + int64_t window_begin_ns; + /* maximum number of entries observed in the window */ + size_t window_max_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - CPUTLBWindow window; size_t n_used_entries; } CPUTLBDesc; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cdcc377102..41f2296f93 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -79,11 +79,11 @@ static inline size_t sizeof_tlb(CPUArchState *env, uint= ptr_t mmu_idx) return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS); } =20 -static void tlb_window_reset(CPUTLBWindow *window, int64_t ns, +static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { - window->begin_ns =3D ns; - window->max_entries =3D max_entries; + desc->window_begin_ns =3D ns; + desc->window_max_entries =3D max_entries; } =20 static void tlb_dyn_init(CPUArchState *env) @@ -94,7 +94,7 @@ static void tlb_dyn_init(CPUArchState *env) CPUTLBDesc *desc =3D &env->tlb_d[i]; size_t n_entries =3D 1 << CPU_TLB_DYN_DEFAULT_BITS; =20 - tlb_window_reset(&desc->window, get_clock_realtime(), 0); + tlb_window_reset(desc, get_clock_realtime(), 0); desc->n_used_entries =3D 0; env->tlb_mask[i] =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; env->tlb_table[i] =3D g_new(CPUTLBEntry, n_entries); @@ -151,18 +151,18 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) int64_t now =3D get_clock_realtime(); int64_t window_len_ms =3D 100; int64_t window_len_ns =3D window_len_ms * 1000 * 1000; - bool window_expired =3D now > desc->window.begin_ns + window_len_ns; + bool window_expired =3D now > desc->window_begin_ns + window_len_ns; =20 - if (desc->n_used_entries > desc->window.max_entries) { - desc->window.max_entries =3D desc->n_used_entries; + if (desc->n_used_entries > desc->window_max_entries) { + desc->window_max_entries =3D desc->n_used_entries; } - rate =3D desc->window.max_entries * 100 / old_size; + rate =3D desc->window_max_entries * 100 / old_size; =20 if (rate > 70) { new_size =3D MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS); } else if (rate < 30 && window_expired) { - size_t ceil =3D pow2ceil(desc->window.max_entries); - size_t expected_rate =3D desc->window.max_entries * 100 / ceil; + size_t ceil =3D pow2ceil(desc->window_max_entries); + size_t expected_rate =3D desc->window_max_entries * 100 / ceil; =20 /* * Avoid undersizing when the max number of entries seen is just b= elow @@ -182,7 +182,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, in= t mmu_idx) =20 if (new_size =3D=3D old_size) { if (window_expired) { - tlb_window_reset(&desc->window, now, desc->n_used_entries); + tlb_window_reset(desc, now, desc->n_used_entries); } return; } @@ -190,7 +190,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, in= t mmu_idx) g_free(env->tlb_table[mmu_idx]); g_free(env->iotlb[mmu_idx]); =20 - tlb_window_reset(&desc->window, now, 0); + tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.33.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:33:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=RRJzWuO3icBCUJa9TEzYdbsu9X8p9QYtOzX1T6steVg=; b=pa6F2hUyti2LKoChQ7uZZTnkAb5ySTIH8RTaOk5yZiL2ieoQdTDlu7g0JjQvtmqkfs DBMgSJkMssQDS2mqO4itZSr5hjlDgMfN4hVETev/dU/a8U47xr2RrM+bWiE2dJJ60gL2 0eZmVxOtgT8pFxRHDYGhWC+JMh3QUd07PgUTbCiIMfMaLfzXkVpDkfK/Ahxfva4R0KGq qqcYZ17gTcY5kByrVV5pObP95y4TRdc6PJUmd7IPYIRZUHlcJWU7/lmFhSZn4xSIv9wZ 4a9sktCdTuusVtctCySJUFhLP83E8yQWGTH8tjsA6oWydp0eWa0T+90NIT+PcTD8GwE+ oaZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=RRJzWuO3icBCUJa9TEzYdbsu9X8p9QYtOzX1T6steVg=; b=ZphVUhHCXoY69nsOBquj/R8X4hRQDzoHzTkX21VdUr5fUkM20gVrlseilAikOCWFBy YKx0Ncp2iZCD/ifMsVdLcwpqyUalP4dym4crKwr7KCfjT8kxvpIWOGFsUTte/I95ZZV/ j00E9M17NERpxAWj0T60/2TbEoQgWgyzVpdAQbEJCOf0v35CameTV9qcWVQJeWTYWaFL 9DIUivkoNI3Oi7HWlx9cMCSkvCQH3jvIWvfmYwgCl/iOKCZzER4TJ86/XydDDAetV9IP nC9h+3CuamQXUUkht2mPt97wvcQ9KfWAMETOtBtP/HIvaOk3Wxmdbi3fKQEl0ui8CaO3 aCkw== X-Gm-Message-State: APjAAAVVX5tfMv5nRAi5QjVHdA/oBfrYS/rSn+T+FesClbzIB7Im4dvO gDqnteWTLmTGxnaTagoeSVqijbABE1vZoA== X-Google-Smtp-Source: APXvYqxEWoQDvtlJbWeaj5co5kZVLn8ammjgBiRtRpsEsQhcyjiOeaF9lx9udpZkw0/wxa0iNyJpqA== X-Received: by 2002:a05:6830:150:: with SMTP id j16mr6880364otp.262.1559680438429; Tue, 04 Jun 2019 13:33:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:14 -0500 Message-Id: <20190604203351.27778-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 02/39] tcg: Split out target/arch/cpu-param.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- v3: Add header comment + include guards. Copyright and license copied from cpu.h, when present. --- include/exec/cpu-defs.h | 22 +++++++++++++++++- target/alpha/cpu-param.h | 31 ++++++++++++++++++++++++++ target/alpha/cpu.h | 23 +------------------ target/arm/cpu-param.h | 34 ++++++++++++++++++++++++++++ target/arm/cpu.h | 33 +++------------------------ target/cris/cpu-param.h | 17 ++++++++++++++ target/cris/cpu.h | 11 +-------- target/hppa/cpu-param.h | 34 ++++++++++++++++++++++++++++ target/hppa/cpu.h | 24 +------------------- target/i386/cpu-param.h | 28 +++++++++++++++++++++++ target/i386/cpu.h | 21 ------------------ target/lm32/cpu-param.h | 17 ++++++++++++++ target/lm32/cpu.h | 12 +++------- target/m68k/cpu-param.h | 22 ++++++++++++++++++ target/m68k/cpu.h | 16 ++----------- target/microblaze/cpu-param.h | 18 +++++++++++++++ target/microblaze/cpu.h | 14 ++---------- target/mips/cpu-param.h | 29 ++++++++++++++++++++++++ target/mips/cpu.h | 3 +-- target/mips/mips-defs.h | 15 ------------- target/moxie/cpu-param.h | 17 ++++++++++++++ target/moxie/cpu.h | 12 +--------- target/nios2/cpu-param.h | 21 ++++++++++++++++++ target/nios2/cpu.h | 17 ++------------ target/openrisc/cpu-param.h | 17 ++++++++++++++ target/openrisc/cpu.h | 14 +++--------- target/ppc/cpu-param.h | 37 ++++++++++++++++++++++++++++++ target/ppc/cpu.h | 42 ++++------------------------------- target/riscv/cpu-param.h | 23 +++++++++++++++++++ target/riscv/cpu.h | 21 ++++-------------- target/s390x/cpu-param.h | 17 ++++++++++++++ target/s390x/cpu.h | 11 +-------- target/sh4/cpu-param.h | 21 ++++++++++++++++++ target/sh4/cpu.h | 14 +----------- target/sparc/cpu-param.h | 28 +++++++++++++++++++++++ target/sparc/cpu.h | 20 ++--------------- target/tilegx/cpu-param.h | 17 ++++++++++++++ target/tilegx/cpu.h | 9 +------- target/tricore/cpu-param.h | 17 ++++++++++++++ target/tricore/cpu.h | 4 +--- target/tricore/tricore-defs.h | 5 ----- target/unicore32/cpu-param.h | 17 ++++++++++++++ target/unicore32/cpu.h | 10 +-------- target/xtensa/cpu-param.h | 21 ++++++++++++++++++ target/xtensa/cpu.h | 21 +++++------------- 45 files changed, 544 insertions(+), 333 deletions(-) create mode 100644 target/alpha/cpu-param.h create mode 100644 target/arm/cpu-param.h create mode 100644 target/cris/cpu-param.h create mode 100644 target/hppa/cpu-param.h create mode 100644 target/i386/cpu-param.h create mode 100644 target/lm32/cpu-param.h create mode 100644 target/m68k/cpu-param.h create mode 100644 target/microblaze/cpu-param.h create mode 100644 target/mips/cpu-param.h create mode 100644 target/moxie/cpu-param.h create mode 100644 target/nios2/cpu-param.h create mode 100644 target/openrisc/cpu-param.h create mode 100644 target/ppc/cpu-param.h create mode 100644 target/riscv/cpu-param.h create mode 100644 target/s390x/cpu-param.h create mode 100644 target/sh4/cpu-param.h create mode 100644 target/sparc/cpu-param.h create mode 100644 target/tilegx/cpu-param.h create mode 100644 target/tricore/cpu-param.h create mode 100644 target/unicore32/cpu-param.h create mode 100644 target/xtensa/cpu-param.h diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 52d150aaf1..2694481769 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -34,8 +34,28 @@ #endif #include "exec/memattrs.h" =20 +#include "cpu-param.h" + #ifndef TARGET_LONG_BITS -#error TARGET_LONG_BITS must be defined before including this header +# error TARGET_LONG_BITS must be defined in cpu-param.h +#endif +#ifndef NB_MMU_MODES +# error NB_MMU_MODES must be defined in cpu-param.h +#endif +#ifndef TARGET_PHYS_ADDR_SPACE_BITS +# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_VIRT_ADDR_SPACE_BITS +# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h +#endif +#ifndef TARGET_PAGE_BITS +# ifdef TARGET_PAGE_BITS_VARY +# ifndef TARGET_PAGE_BITS_MIN +# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h +# endif +# else +# error TARGET_PAGE_BITS must be defined in cpu-param.h +# endif #endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h new file mode 100644 index 0000000000..692aee27ca --- /dev/null +++ b/target/alpha/cpu-param.h @@ -0,0 +1,31 @@ +/* + * Alpha cpu parameters for qemu. + * + * Copyright (c) 2007 Jocelyn Mayer + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef ALPHA_CPU_PARAM_H +#define ALPHA_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 13 +#ifdef CONFIG_USER_ONLY +/* + * ??? The kernel likes to give addresses in high memory. If the host has + * more virtual address space than the guest, this can lead to impossible + * allocations. Honor the long-standing assumption that only kernel addrs + * are negative, but otherwise allow allocations anywhere. This could lead + * to tricky emulation problems for programs doing tagged addressing, but + * that's far fewer than encounter the impossible allocation problem. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 63 +#define TARGET_VIRT_ADDR_SPACE_BITS 63 +#else +/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 44 +#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +#endif +#define NB_MMU_MODES 3 + +#endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ba6bc31b15..dc1883f0f1 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,8 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#define TARGET_LONG_BITS 64 #define ALIGNED_ONLY =20 #define CPUArchState struct CPUAlphaState @@ -31,28 +31,9 @@ /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#include "exec/cpu-defs.h" - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 =20 -#define TARGET_PAGE_BITS 13 - -#ifdef CONFIG_USER_ONLY -/* ??? The kernel likes to give addresses in high memory. If the host has - more virtual address space than the guest, this can lead to impossible - allocations. Honor the long-standing assumption that only kernel addrs - are negative, but otherwise allow allocations anywhere. This could lead - to tricky emulation problems for programs doing tagged addressing, but - that's far fewer than encounter the impossible allocation problem. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 63 -#define TARGET_VIRT_ADDR_SPACE_BITS 63 -#else -/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 44 -#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) -#endif - /* Alpha major type */ enum { ALPHA_EV3 =3D 1, @@ -217,8 +198,6 @@ enum { PALcode cheats and usees the KSEG mapping for its code+data rather than physical addresses. */ =20 -#define NB_MMU_MODES 3 - #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_KERNEL_IDX 0 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h new file mode 100644 index 0000000000..6e6948e960 --- /dev/null +++ b/target/arm/cpu-param.h @@ -0,0 +1,34 @@ +/* + * ARM cpu parameters for qemu. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef ARM_CPU_PARAM_H +#define ARM_CPU_PARAM_H 1 + +#ifdef TARGET_AARCH64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 48 +# define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 40 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif + +#ifdef CONFIG_USER_ONLY +#define TARGET_PAGE_BITS 12 +#else +/* + * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 + * have to support 1K tiny pages. + */ +# define TARGET_PAGE_BITS_VARY +# define TARGET_PAGE_BITS_MIN 10 +#endif + +#define NB_MMU_MODES 8 + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c34207611b..f8020b4823 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -22,23 +22,15 @@ =20 #include "kvm-consts.h" #include "hw/registerfields.h" - -#if defined(TARGET_AARCH64) - /* AArch64 definitions */ -# define TARGET_LONG_BITS 64 -#else -# define TARGET_LONG_BITS 32 -#endif +#include "qemu-common.h" +#include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 #define CPUArchState struct CPUARMState =20 -#include "qemu-common.h" -#include "cpu-qom.h" -#include "exec/cpu-defs.h" - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -114,7 +106,6 @@ enum { #define ARM_CPU_VIRQ 2 #define ARM_CPU_VFIQ 3 =20 -#define NB_MMU_MODES 8 /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -2639,24 +2630,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sy= nc); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 =20 -#if defined(CONFIG_USER_ONLY) -#define TARGET_PAGE_BITS 12 -#else -/* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 - * have to support 1K tiny pages. - */ -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 10 -#endif - -#if defined(TARGET_AARCH64) -# define TARGET_PHYS_ADDR_SPACE_BITS 48 -# define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -# define TARGET_PHYS_ADDR_SPACE_BITS 40 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h new file mode 100644 index 0000000000..36a3058761 --- /dev/null +++ b/target/cris/cpu-param.h @@ -0,0 +1,17 @@ +/* + * CRIS cpu parameters for qemu. + * + * Copyright (c) 2007 AXIS Communications AB + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef CRIS_CPU_PARAM_H +#define CRIS_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 857de79e24..25408c2bf7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,13 +23,10 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" =20 #define CPUArchState struct CPUCRISState =20 -#include "exec/cpu-defs.h" - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -105,8 +102,6 @@ #define CC_A 14 #define CC_P 15 =20 -#define NB_MMU_MODES 2 - typedef struct { uint32_t hi; uint32_t lo; @@ -260,12 +255,8 @@ enum { }; =20 /* CRIS uses 8k pages. */ -#define TARGET_PAGE_BITS 13 #define MMAP_SHIFT TARGET_PAGE_BITS =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h new file mode 100644 index 0000000000..a97d1428df --- /dev/null +++ b/target/hppa/cpu-param.h @@ -0,0 +1,34 @@ +/* + * PA-RISC cpu parameters for qemu. + * + * Copyright (c) 2016 Richard Henderson + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef HPPA_CPU_PARAM_H +#define HPPA_CPU_PARAM_H 1 + +#ifdef TARGET_HPPA64 +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 64 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 64 +#elif defined(CONFIG_USER_ONLY) +# define TARGET_LONG_BITS 32 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#else +/* + * In order to form the GVA from space:offset, + * we need a 64-bit virtual address space. + */ +# define TARGET_LONG_BITS 64 +# define TARGET_REGISTER_BITS 32 +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 5 + +#endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c1e0215e66..fb527eba88 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,25 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#ifdef TARGET_HPPA64 -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#elif defined(CONFIG_USER_ONLY) -#define TARGET_LONG_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#else -/* In order to form the GVA from space:offset, - we need a 64-bit virtual address space. */ -#define TARGET_LONG_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define TARGET_REGISTER_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have @@ -50,12 +33,7 @@ =20 #define CPUArchState struct CPUHPPAState =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 - #define ALIGNED_ONLY -#define NB_MMU_MODES 5 #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h new file mode 100644 index 0000000000..57abc64c0d --- /dev/null +++ b/target/i386/cpu-param.h @@ -0,0 +1,28 @@ +/* + * i386 cpu parameters for qemu. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef I386_CPU_PARAM_H +#define I386_CPU_PARAM_H 1 + +#ifdef TARGET_X86_64 +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 52 +/* + * ??? This is really 48 bits, sign-extended, but the only thing + * accessible to userland with bit 48 set is the VSYSCALL, and that + * is handled via other mechanisms. + */ +# define TARGET_VIRT_ADDR_SPACE_BITS 47 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bd06523a53..36f5095768 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,13 +24,6 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "hyperv-proto.h" - -#ifdef TARGET_X86_64 -#define TARGET_LONG_BITS 64 -#else -#define TARGET_LONG_BITS 32 -#endif - #include "exec/cpu-defs.h" =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ @@ -956,7 +949,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) =20 -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define NB_OPMASK_REGS 8 @@ -1695,19 +1687,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -#define TARGET_PAGE_BITS 12 - -#ifdef TARGET_X86_64 -#define TARGET_PHYS_ADDR_SPACE_BITS 52 -/* ??? This is really 48 bits, sign-extended, but the only thing - accessible to userland with bit 48 set is the VSYSCALL, and that - is handled via other mechanisms. */ -#define TARGET_VIRT_ADDR_SPACE_BITS 47 -#else -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - /* XXX: This value should match the one returned by CPUID * and in exec.c */ # if defined(TARGET_X86_64) diff --git a/target/lm32/cpu-param.h b/target/lm32/cpu-param.h new file mode 100644 index 0000000000..d89574ad19 --- /dev/null +++ b/target/lm32/cpu-param.h @@ -0,0 +1,17 @@ +/* + * LatticeMico32 cpu parameters for qemu. + * + * Copyright (c) 2010 Michael Walle + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef LM32_CPU_PARAM_H +#define LM32_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index d224d4426e..e75110c4e0 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -20,26 +20,20 @@ #ifndef LM32_CPU_H #define LM32_CPU_H =20 -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPULM32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" + +#define CPUArchState struct CPULM32State + struct CPULM32State; typedef struct CPULM32State CPULM32State; =20 -#define NB_MMU_MODES 1 -#define TARGET_PAGE_BITS 12 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) { return 0; } =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - /* Exceptions indices */ enum { EXCP_RESET =3D 0, diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h new file mode 100644 index 0000000000..06556dfbf3 --- /dev/null +++ b/target/m68k/cpu-param.h @@ -0,0 +1,22 @@ +/* + * m68k cpu parameters for qemu. + * + * Copyright (c) 2005-2007 CodeSourcery + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef M68K_CPU_PARAM_H +#define M68K_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +/* + * Coldfire Linux uses 8k pages + * and m68k linux uses 4k pages + * use the smallest one + */ +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9deff9e234..e99c102302 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -21,14 +21,12 @@ #ifndef M68K_CPU_H #define M68K_CPU_H =20 -#define TARGET_LONG_BITS 32 - -#define CPUArchState struct CPUM68KState - #include "qemu-common.h" #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 +#define CPUArchState struct CPUM68KState + #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -82,7 +80,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] =20 -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 typedef CPU_LDoubleU FPReg; @@ -502,12 +499,6 @@ void m68k_cpu_list(void); =20 void register_m68k_insns (CPUM68KState *env); =20 -/* Coldfire Linux uses 8k pages - * and m68k linux uses 4k pages - * use the smallest one - */ -#define TARGET_PAGE_BITS 12 - enum { /* 1 bit to define user level / supervisor access */ ACCESS_SUPER =3D 0x01, @@ -522,9 +513,6 @@ enum { ACCESS_DATA =3D 0x20, /* Data load/store access */ }; =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h new file mode 100644 index 0000000000..4abbc62d50 --- /dev/null +++ b/target/microblaze/cpu-param.h @@ -0,0 +1,18 @@ +/* + * MicroBlaze cpu parameters for qemu. + * + * Copyright (c) 2009 Edgar E. Iglesias + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef MICROBLAZE_CPU_PARAM_H +#define MICROBLAZE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 7a9fb8f4aa..b8db8ca9a3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -22,13 +22,11 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" +#include "fpu/softfloat-types.h" =20 #define CPUArchState struct CPUMBState =20 -#include "exec/cpu-defs.h" -#include "fpu/softfloat-types.h" struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) @@ -228,8 +226,6 @@ typedef struct CPUMBState CPUMBState; #define CC_NE 1 #define CC_EQ 0 =20 -#define NB_MMU_MODES 3 - #define STREAM_EXCEPTION (1 << 0) #define STREAM_ATOMIC (1 << 1) #define STREAM_TEST (1 << 2) @@ -340,12 +336,6 @@ void mb_tcg_init(void); int cpu_mb_signal_handler(int host_signum, void *pinfo, void *puc); =20 -/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU =20 #define cpu_signal_handler cpu_mb_signal_handler diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h new file mode 100644 index 0000000000..308660d29d --- /dev/null +++ b/target/mips/cpu-param.h @@ -0,0 +1,29 @@ +/* + * MIPS cpu parameters for qemu. + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef MIPS_CPU_PARAM_H +#define MIPS_CPU_PARAM_H 1 + +#ifdef TARGET_MIPS64 +# define TARGET_LONG_BITS 64 +#else +# define TARGET_LONG_BITS 32 +#endif +#ifdef TARGET_MIPS64 +#define TARGET_PHYS_ADDR_SPACE_BITS 48 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 +#else +#define TARGET_PHYS_ADDR_SPACE_BITS 40 +# ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 4 + +#endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 06a8ed4748..34e7aec4d0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -7,9 +7,9 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" -#include "mips-defs.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#include "mips-defs.h" =20 #define TCG_GUEST_DEFAULT_MO (0) =20 @@ -103,7 +103,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; =20 -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index dbdb4b2b2d..bbf056a548 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -5,23 +5,8 @@ //#define USE_HOST_FLOAT_REGS =20 /* Real pages are variable size... */ -#define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 =20 -#if defined(TARGET_MIPS64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 48 -#define TARGET_VIRT_ADDR_SPACE_BITS 48 -#else -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 40 -# ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#endif - /* * bit definitions for insn_flags (ISAs/ASEs flags) * ------------------------------------------------ diff --git a/target/moxie/cpu-param.h b/target/moxie/cpu-param.h new file mode 100644 index 0000000000..9a40ef525c --- /dev/null +++ b/target/moxie/cpu-param.h @@ -0,0 +1,17 @@ +/* + * Moxie cpu parameters for qemu. + * + * Copyright (c) 2008, 2010, 2013 Anthony Green + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef MOXIE_CPU_PARAM_H +#define MOXIE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index a63a96bc05..7164dd7f5f 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -21,8 +21,7 @@ #define MOXIE_CPU_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" =20 #define CPUArchState struct CPUMoxieState =20 @@ -33,15 +32,6 @@ #define MOXIE_EX_MMU_MISS 4 #define MOXIE_EX_BREAK 16 =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define NB_MMU_MODES 1 - typedef struct CPUMoxieState { =20 uint32_t flags; /* general execution flags */ diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h new file mode 100644 index 0000000000..38bedbfd61 --- /dev/null +++ b/target/nios2/cpu-param.h @@ -0,0 +1,21 @@ +/* + * Altera Nios II cpu parameters for qemu. + * + * Copyright (c) 2012 Chris Wulff + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef NIOS2_CPU_PARAM_H +#define NIOS2_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 + +#endif diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 35d3886dc2..c4ccea9cf0 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -22,13 +22,11 @@ #define NIOS2_CPU_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 32 +#include "exec/cpu-defs.h" +#include "qom/cpu.h" =20 #define CPUArchState struct CPUNios2State =20 -#include "exec/cpu-defs.h" -#include "qom/cpu.h" struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) @@ -164,8 +162,6 @@ typedef struct Nios2CPUClass { =20 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 =20 -#define NB_MMU_MODES 2 - struct CPUNios2State { uint32_t regs[NUM_CORE_REGS]; =20 @@ -225,13 +221,6 @@ void nios2_check_interrupts(CPUNios2State *env); =20 void do_nios2_semihosting(CPUNios2State *env); =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU =20 #define cpu_gen_code cpu_nios2_gen_code @@ -239,8 +228,6 @@ void do_nios2_semihosting(CPUNios2State *env); =20 #define CPU_SAVE_VERSION 1 =20 -#define TARGET_PAGE_BITS 12 - /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h new file mode 100644 index 0000000000..06ee64d171 --- /dev/null +++ b/target/openrisc/cpu-param.h @@ -0,0 +1,17 @@ +/* + * OpenRISC cpu parameters for qemu. + * + * Copyright (c) 2011-2012 Jia Liu + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef OPENRISC_CPU_PARAM_H +#define OPENRISC_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9473d94d0c..3727efabf3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,15 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H =20 -#define TARGET_LONG_BITS 32 +#include "qemu-common.h" +#include "exec/cpu-defs.h" +#include "qom/cpu.h" =20 #define CPUArchState struct CPUOpenRISCState =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; =20 -#include "qemu-common.h" -#include "exec/cpu-defs.h" -#include "qom/cpu.h" - #define TYPE_OPENRISC_CPU "or1k-cpu" =20 #define OPENRISC_CPU_CLASS(klass) \ @@ -56,7 +54,6 @@ typedef struct OpenRISCCPUClass { void (*parent_reset)(CPUState *cpu); } OpenRISCCPUClass; =20 -#define NB_MMU_MODES 3 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 enum { @@ -65,11 +62,6 @@ enum { MMU_USER_IDX =3D 2, }; =20 -#define TARGET_PAGE_BITS 13 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define SET_FP_CAUSE(reg, v) do {\ (reg) =3D ((reg) & ~(0x3f << 12)) | \ ((v & 0x3f) << 12);\ diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h new file mode 100644 index 0000000000..37b458d33d --- /dev/null +++ b/target/ppc/cpu-param.h @@ -0,0 +1,37 @@ +/* + * PowerPC cpu parameters for qemu. + * + * Copyright (c) 2007 Jocelyn Mayer + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef PPC_CPU_PARAM_H +#define PPC_CPU_PARAM_H 1 + +#ifdef TARGET_PPC64 +# define TARGET_LONG_BITS 64 +/* + * Note that the official physical address space bits is 62-M where M + * is implementation dependent. I've not looked up M for the set of + * cpus we emulate at the system level. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 62 +/* + * Note that the PPC environment architecture talks about 80 bit virtual + * addresses, with segmentation. Obviously that's not all visible to a + * single process, which is all we're concerned with here. + */ +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +# endif +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define TARGET_PAGE_BITS 12 +#define NB_MMU_MODES 10 + +#endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d7f23ad5e0..02ca453df3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -22,53 +22,20 @@ =20 #include "qemu-common.h" #include "qemu/int128.h" +#include "exec/cpu-defs.h" +#include "cpu-qom.h" +#include "exec/cpu-defs.h" +#include "cpu-qom.h" =20 /* #define PPC_EMULATE_32BITS_HYPV */ =20 -#if defined(TARGET_PPC64) -/* PowerPC 64 definitions */ -#define TARGET_LONG_BITS 64 -#define TARGET_PAGE_BITS 12 - #define TCG_GUEST_DEFAULT_MO 0 =20 -/* - * Note that the official physical address space bits is 62-M where M - * is implementation dependent. I've not looked up M for the set of - * cpus we emulate at the system level. - */ -#define TARGET_PHYS_ADDR_SPACE_BITS 62 - -/* - * Note that the PPC environment architecture talks about 80 bit - * virtual addresses, with segmentation. Obviously that's not all - * visible to a single process, which is all we're concerned with - * here. - */ -#ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 64 -#endif - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 -#else /* defined(TARGET_PPC64) */ -/* PowerPC 32 definitions */ -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#endif /* defined(TARGET_PPC64) */ - #define CPUArchState struct CPUPPCState =20 -#include "exec/cpu-defs.h" -#include "cpu-qom.h" - #if defined(TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -974,7 +941,6 @@ struct ppc_radix_page_info { * + real/paged mode combinations. The other two modes are for * external PID load/store. */ -#define NB_MMU_MODES 10 #define MMU_MODE8_SUFFIX _epl #define MMU_MODE9_SUFFIX _eps #define PPC_TLB_EPID_LOAD 8 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h new file mode 100644 index 0000000000..664fc1d371 --- /dev/null +++ b/target/riscv/cpu-param.h @@ -0,0 +1,23 @@ +/* + * RISC-V cpu parameters for qemu. + * + * Copyright (c) 2017-2018 SiFive, Inc. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef RISCV_CPU_PARAM_H +#define RISCV_CPU_PARAM_H 1 + +#if defined(TARGET_RISCV64) +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +#elif defined(TARGET_RISCV32) +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#endif +#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#define NB_MMU_MODES 4 + +#endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74e726c1c9..bc517dbad8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -20,27 +20,15 @@ #ifndef RISCV_CPU_H #define RISCV_CPU_H =20 -/* QEMU addressing/paging config */ -#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#if defined(TARGET_RISCV64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ -#elif defined(TARGET_RISCV32) -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ -#endif - -#define TCG_GUEST_DEFAULT_MO 0 - -#define CPUArchState struct CPURISCVState - #include "qemu-common.h" #include "qom/cpu.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" =20 +#define TCG_GUEST_DEFAULT_MO 0 + +#define CPUArchState struct CPURISCVState + #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -98,7 +86,6 @@ enum { =20 #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 -#define NB_MMU_MODES 4 #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h new file mode 100644 index 0000000000..472db648d7 --- /dev/null +++ b/target/s390x/cpu-param.h @@ -0,0 +1,17 @@ +/* + * S/390 cpu parameters for qemu. + * + * Copyright (c) 2009 Ulrich Hecht + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef S390_CPU_PARAM_H +#define S390_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 64 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 4 + +#endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7305cacc7b..3a82ea53e1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -24,26 +24,17 @@ #include "qemu-common.h" #include "cpu-qom.h" #include "cpu_models.h" - -#define TARGET_LONG_BITS 64 +#include "exec/cpu-defs.h" =20 #define ELF_MACHINE_UNAME "S390X" =20 #define CPUArchState struct CPUS390XState =20 -#include "exec/cpu-defs.h" - /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 64 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 - #include "exec/cpu-all.h" =20 -#define NB_MMU_MODES 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define MMU_MODE0_SUFFIX _primary diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h new file mode 100644 index 0000000000..81ace3503b --- /dev/null +++ b/target/sh4/cpu-param.h @@ -0,0 +1,21 @@ +/* + * SH4 cpu parameters for qemu. + * + * Copyright (c) 2005 Samuel Tardieu + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef SH4_CPU_PARAM_H +#define SH4_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 /* 4k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 2 + +#endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 547194aac7..7af6ff5d57 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,8 +22,8 @@ =20 #include "qemu-common.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 -#define TARGET_LONG_BITS 32 #define ALIGNED_ONLY =20 /* CPU Subtypes */ @@ -38,17 +38,6 @@ =20 #define CPUArchState struct CPUSH4State =20 -#include "exec/cpu-defs.h" - -#define TARGET_PAGE_BITS 12 /* 4k XXXXX */ - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -# define TARGET_VIRT_ADDR_SPACE_BITS 31 -#else -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -132,7 +121,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 =20 -#define NB_MMU_MODES 2 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 enum sh_features { diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h new file mode 100644 index 0000000000..4746d89411 --- /dev/null +++ b/target/sparc/cpu-param.h @@ -0,0 +1,28 @@ +/* + * Sparc cpu parameters for qemu. + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef SPARC_CPU_PARAM_H +#define SPARC_CPU_PARAM_H 1 + +#ifdef TARGET_SPARC64 +# define TARGET_LONG_BITS 64 +# define TARGET_PAGE_BITS 13 /* 8k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 41 +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 44 +# endif +# define NB_MMU_MODES 6 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PAGE_BITS 12 /* 4k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define NB_MMU_MODES 3 +#endif + +#endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f31e8535df..bcfdf513cf 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,31 +4,18 @@ #include "qemu-common.h" #include "qemu/bswap.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" =20 #define ALIGNED_ONLY =20 #if !defined(TARGET_SPARC64) -#define TARGET_LONG_BITS 32 #define TARGET_DPREGS 16 -#define TARGET_PAGE_BITS 12 /* 4k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_DPREGS 32 -#define TARGET_PAGE_BITS 13 /* 8k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 41 -# ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 44 -# endif #endif =20 #define CPUArchState struct CPUSPARCState =20 -#include "exec/cpu-defs.h" - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ @@ -225,10 +212,7 @@ enum { #define MIN_NWINDOWS 3 #define MAX_NWINDOWS 32 =20 -#if !defined(TARGET_SPARC64) -#define NB_MMU_MODES 3 -#else -#define NB_MMU_MODES 6 +#ifdef TARGET_SPARC64 typedef struct trap_state { uint64_t tpc; uint64_t tnpc; diff --git a/target/tilegx/cpu-param.h b/target/tilegx/cpu-param.h new file mode 100644 index 0000000000..80a341cbb7 --- /dev/null +++ b/target/tilegx/cpu-param.h @@ -0,0 +1,17 @@ +/* + * TILE-Gx cpu parameters for qemu. + * + * Copyright (c) 2015 Chen Gang + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef TILEGX_CPU_PARAM_H +#define TILEGX_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 64 +#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ +#define TARGET_PHYS_ADDR_SPACE_BITS 42 +#define TARGET_VIRT_ADDR_SPACE_BITS 64 +#define NB_MMU_MODES 1 + +#endif diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 238f8d36d7..429a6c6b43 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -21,13 +21,9 @@ #define TILEGX_CPU_H =20 #include "qemu-common.h" - -#define TARGET_LONG_BITS 64 - -#define CPUArchState struct CPUTLGState - #include "exec/cpu-defs.h" =20 +#define CPUArchState struct CPUTLGState =20 /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ @@ -154,9 +150,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ -#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#define TARGET_VIRT_ADDR_SPACE_BITS 64 #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 #include "exec/cpu-all.h" diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h new file mode 100644 index 0000000000..cf5d9af89d --- /dev/null +++ b/target/tricore/cpu-param.h @@ -0,0 +1,17 @@ +/* + * TriCore cpu parameters for qemu. + * + * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef TRICORE_CPU_PARAM_H +#define TRICORE_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 14 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 3 + +#endif diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 287f4328a3..bccde45a07 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -20,10 +20,10 @@ #ifndef TRICORE_CPU_H #define TRICORE_CPU_H =20 -#include "tricore-defs.h" #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "tricore-defs.h" =20 #define CPUArchState struct CPUTriCoreState =20 @@ -31,8 +31,6 @@ struct CPUTriCoreState; =20 struct tricore_boot_info; =20 -#define NB_MMU_MODES 3 - typedef struct tricore_def_t tricore_def_t; =20 typedef struct CPUTriCoreState CPUTriCoreState; diff --git a/target/tricore/tricore-defs.h b/target/tricore/tricore-defs.h index e871aa1c6b..f5e0a0bed8 100644 --- a/target/tricore/tricore-defs.h +++ b/target/tricore/tricore-defs.h @@ -18,11 +18,6 @@ #ifndef QEMU_TRICORE_DEFS_H #define QEMU_TRICORE_DEFS_H =20 -#define TARGET_PAGE_BITS 14 -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - #define TRICORE_TLB_MAX 128 =20 #endif /* QEMU_TRICORE_DEFS_H */ diff --git a/target/unicore32/cpu-param.h b/target/unicore32/cpu-param.h new file mode 100644 index 0000000000..94d8a5daa1 --- /dev/null +++ b/target/unicore32/cpu-param.h @@ -0,0 +1,17 @@ +/* + * UniCore32 cpu parameters for qemu. + * + * Copyright (C) 2010-2012 Guan Xuetao + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef UNICORE32_CPU_PARAM_H +#define UNICORE32_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index f052ee08bf..a4c4ea328e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -12,19 +12,11 @@ #ifndef UNICORE32_CPU_H #define UNICORE32_CPU_H =20 -#define TARGET_LONG_BITS 32 -#define TARGET_PAGE_BITS 12 - -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 - -#define CPUArchState struct CPUUniCore32State - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define NB_MMU_MODES 2 +#define CPUArchState struct CPUUniCore32State =20 typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h new file mode 100644 index 0000000000..4fde21b941 --- /dev/null +++ b/target/xtensa/cpu-param.h @@ -0,0 +1,21 @@ +/* + * Xtensa cpu parameters for qemu. + * + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef XTENSA_CPU_PARAM_H +#define XTENSA_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +#define TARGET_VIRT_ADDR_SPACE_BITS 30 +#else +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif +#define NB_MMU_MODES 4 + +#endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a0df46f73b..0c6afd43a4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -28,28 +28,17 @@ #ifndef XTENSA_CPU_H #define XTENSA_CPU_H =20 -#define ALIGNED_ONLY -#define TARGET_LONG_BITS 32 - -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - -#define CPUArchState struct CPUXtensaState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" =20 -#define NB_MMU_MODES 4 +#define ALIGNED_ONLY =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#ifdef CONFIG_USER_ONLY -#define TARGET_VIRT_ADDR_SPACE_BITS 30 -#else -#define TARGET_VIRT_ADDR_SPACE_BITS 32 -#endif -#define TARGET_PAGE_BITS 12 +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + +#define CPUArchState struct CPUXtensaState =20 enum { /* Additional instructions */ --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680766; cv=none; d=zoho.com; s=zohoarc; b=gxkMgircveeMgsD4qLnx5nJJBYRqg+jug7sj7i3E9QLaV9rcIVF0XWef/54p0lgro+m+ng5ibVxQJDwkmwtzpNTx0k78y0bKOv6e8KLAUkQGzDq55Sc0N1IwaG4oOq+qkbao4+y7W2ivNj1X0fVv6rUvRthaEZWzm9uhf8iQQ0c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559680766; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KTh7WI74HZX7qvAK8Mq5agv3MsbOOD4l7/fjyl8NNaw=; b=MGu4S/WgmntUMvoFayrBvpejKee4367wIhN3SfBVF7+HjqH29DINB6KvDRBQGYa1oY5afA38ijPkvvBVGGduZq8ETCSuMY9SoDlfHZHcaRX9S+lkpLGycSsc1ws5XdJ9nremUzfby66VZGi4QpFmA9fqqP2a9Xz/qRTOtOMmDv4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559680766916821.9765713159792; Tue, 4 Jun 2019 13:39:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:57642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGDE-0004yg-FS for importer@patchew.org; Tue, 04 Jun 2019 16:39:16 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8D-0000xT-3B for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG89-00041h-Kd for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:05 -0400 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:38817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG89-000414-CU for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:01 -0400 Received: by mail-ot1-x344.google.com with SMTP id d17so6677637oth.5 for ; Tue, 04 Jun 2019 13:34:01 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.33.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=KTh7WI74HZX7qvAK8Mq5agv3MsbOOD4l7/fjyl8NNaw=; b=tQ5vacwBmrqDM3lcCI8AhCvijyZhK9K8ExzsyPUf4/Uk5LjzegU3c6eIOjFCNieCZJ uUfR8icbP6mJDFzn7rmDFAgB9FgPRIA/8ckdsY1OAAohV2WvdZ2vLLOUs6Nruh28o30b RnFWX8/YKYGFJQoapZekGfa1swnIZGK42qAOwXLHwIOQcMqVEEAEgthBj1hy+5m+eHws eTFzuwtMK/+cXHMH9q3fPD/93KjhzPxX6u7uJ2NxYTD5n2Xi/sOtAkfbVWWqP1GvWQXe oJ57Oy8VyfERFJeTTEJaJa68oSfd5PwHrFc5sH0Ry0iNC2brn/G9gWIbmwKoJUy2GWIO nlRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=KTh7WI74HZX7qvAK8Mq5agv3MsbOOD4l7/fjyl8NNaw=; b=uYcCsGM975YqNJULndG3Q4Cam2gN+4aEMh+aTD1fipw9MPMhb+qZiSqXAz33vWUSts Njf0WaF91/yB4vzGGnoyv2mh9IF2H4FyOPcwiQ1bdKCWD0/77uJ+X7PjI9EWFwy1EyjH 27gRqQU25wGqdmSJCFAtxyoIqh7HIOK++mez6VmHSQ9KCTMnqAg8ZYuBLGqLsiYnSJVA EQ8lWhtoTrcH5swpK2bqN9BdpCt74xkuw0jYlv21H7BKBbrkTvwkokinad5oz7OiCo11 DhBPfHfahLC+vjgopjhA5IkvGbIbBep+HewFY5gEHOwBFFYE+Symyx/n0KNQYkEi+EhA RUXw== X-Gm-Message-State: APjAAAWGTA9Avyeg+J1Tma0ti1DQf8A9NIMWygMYT5t7z47vcHEqzCah MJWwvawg/QmbxZddDjvAiWo7qSyoJBbFcw== X-Google-Smtp-Source: APXvYqyt2P1F9NBqpKxo9/GMy9REtnp2hy0ypNVgaLMItmpU5WuVuJCroXKzO7BRz/DRs6TjZtoQaA== X-Received: by 2002:a9d:4c17:: with SMTP id l23mr6514721otf.367.1559680439827; Tue, 04 Jun 2019 13:33:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:15 -0500 Message-Id: <20190604203351.27778-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 03/39] tcg: Create struct CPUTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 61 +++++++------ include/exec/cpu_ldst.h | 6 +- accel/tcg/cputlb.c | 164 +++++++++++++++++++---------------- target/arm/translate-a64.c | 2 +- tcg/aarch64/tcg-target.inc.c | 10 +-- tcg/arm/tcg-target.inc.c | 10 +-- tcg/i386/tcg-target.inc.c | 4 +- tcg/mips/tcg-target.inc.c | 12 +-- tcg/ppc/tcg-target.inc.c | 8 +- tcg/riscv/tcg-target.inc.c | 12 +-- tcg/s390/tcg-target.inc.c | 8 +- tcg/sparc/tcg-target.inc.c | 12 +-- 12 files changed, 146 insertions(+), 163 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 2694481769..b9ec261b01 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -78,6 +78,7 @@ typedef uint64_t target_ulong; #endif =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) + /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 =20 @@ -147,6 +148,10 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +/* + * Data elements that are per MMU mode, minus the bits accessed by + * the TCG fast path. + */ typedef struct CPUTLBDesc { /* * Describe a region covering all of the large pages allocated @@ -160,16 +165,31 @@ typedef struct CPUTLBDesc { int64_t window_begin_ns; /* maximum number of entries observed in the window */ size_t window_max_entries; + size_t n_used_entries; /* The next index to use in the tlb victim table. */ size_t vindex; - size_t n_used_entries; + /* The tlb victim table, in two parts. */ + CPUTLBEntry vtable[CPU_VTLB_SIZE]; + CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; + /* The iotlb. */ + CPUIOTLBEntry *iotlb; } CPUTLBDesc; =20 +/* + * Data elements that are per MMU mode, accessed by the fast path. + */ +typedef struct CPUTLBDescFast { + /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ + uintptr_t mask; + /* The array of tlb entries itself. */ + CPUTLBEntry *table; +} CPUTLBDescFast; + /* * Data elements that are shared between all MMU modes. */ typedef struct CPUTLBCommon { - /* Serialize updates to tlb_table and tlb_v_table, and others as noted= . */ + /* Serialize updates to f.table and d.vtable, and others as noted. */ QemuSpin lock; /* * Within dirty, for each bit N, modifications have been made to @@ -187,35 +207,24 @@ typedef struct CPUTLBCommon { size_t elide_flush_count; } CPUTLBCommon; =20 -# define CPU_TLB \ - /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \ - uintptr_t tlb_mask[NB_MMU_MODES]; \ - CPUTLBEntry *tlb_table[NB_MMU_MODES]; -# define CPU_IOTLB \ - CPUIOTLBEntry *iotlb[NB_MMU_MODES]; - /* + * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. - * Note that NB_MMU_MODES is not yet defined; we can only reference it - * within preprocessor defines that will be expanded later. */ -#define CPU_COMMON_TLB \ - CPUTLBCommon tlb_c; \ - CPUTLBDesc tlb_d[NB_MMU_MODES]; \ - CPU_TLB \ - CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - CPU_IOTLB \ - CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; +typedef struct CPUTLB { + CPUTLBDescFast f[NB_MMU_MODES]; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBCommon c; +} CPUTLB; + +/* There are target-specific members named "tlb". This is temporary. */ +#define CPU_COMMON CPUTLB tlb_; +#define env_tlb(ENV) (&(ENV)->tlb_) =20 #else =20 -#define CPU_COMMON_TLB - -#endif - - -#define CPU_COMMON \ - /* soft mmu support */ \ - CPU_COMMON_TLB \ +#define CPU_COMMON /* Nothing */ + +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 #endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 7b28a839d2..a08b11bd2c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -139,21 +139,21 @@ static inline target_ulong tlb_addr_write(const CPUTL= BEntry *entry) static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - uintptr_t size_mask =3D env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS; + uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; =20 return (addr >> TARGET_PAGE_BITS) & size_mask; } =20 static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) { - return (env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS) + 1; + return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; } =20 /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) { - return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)]; + return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } =20 #ifdef MMU_MODE0_SUFFIX diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 41f2296f93..a3a39e9a77 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -76,7 +76,7 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); =20 static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx) { - return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS); + return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS); } =20 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, @@ -91,14 +91,14 @@ static void tlb_dyn_init(CPUArchState *env) int i; =20 for (i =3D 0; i < NB_MMU_MODES; i++) { - CPUTLBDesc *desc =3D &env->tlb_d[i]; + CPUTLBDesc *desc =3D &env_tlb(env)->d[i]; size_t n_entries =3D 1 << CPU_TLB_DYN_DEFAULT_BITS; =20 tlb_window_reset(desc, get_clock_realtime(), 0); desc->n_used_entries =3D 0; - env->tlb_mask[i] =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[i] =3D g_new(CPUTLBEntry, n_entries); - env->iotlb[i] =3D g_new(CPUIOTLBEntry, n_entries); + env_tlb(env)->f[i].mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[i].table =3D g_new(CPUTLBEntry, n_entries); + env_tlb(env)->d[i].iotlb =3D g_new(CPUIOTLBEntry, n_entries); } } =20 @@ -144,7 +144,7 @@ static void tlb_dyn_init(CPUArchState *env) */ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) { - CPUTLBDesc *desc =3D &env->tlb_d[mmu_idx]; + CPUTLBDesc *desc =3D &env_tlb(env)->d[mmu_idx]; size_t old_size =3D tlb_n_entries(env, mmu_idx); size_t rate; size_t new_size =3D old_size; @@ -187,14 +187,14 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) return; } =20 - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ - env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; - env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] =3D g_try_new(CPUIOTLBEntry, new_size); + env_tlb(env)->f[mmu_idx].mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].table =3D g_try_new(CPUTLBEntry, new_size); + env_tlb(env)->d[mmu_idx].iotlb =3D g_try_new(CPUIOTLBEntry, new_size); /* * If the allocations fail, try smaller sizes. We just freed some * memory, so going back to half of new_size has a good chance of work= ing. @@ -202,46 +202,47 @@ static void tlb_mmu_resize_locked(CPUArchState *env, = int mmu_idx) * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (env->tlb_table[mmu_idx] =3D=3D NULL || env->iotlb[mmu_idx] =3D= =3D NULL) { + while (env_tlb(env)->f[mmu_idx].table =3D=3D NULL || + env_tlb(env)->d[mmu_idx].iotlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); } new_size =3D MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS); - env->tlb_mask[mmu_idx] =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; + env_tlb(env)->f[mmu_idx].mask =3D (new_size - 1) << CPU_TLB_ENTRY_= BITS; =20 - g_free(env->tlb_table[mmu_idx]); - g_free(env->iotlb[mmu_idx]); - env->tlb_table[mmu_idx] =3D g_try_new(CPUTLBEntry, new_size); - env->iotlb[mmu_idx] =3D g_try_new(CPUIOTLBEntry, new_size); + g_free(env_tlb(env)->f[mmu_idx].table); + g_free(env_tlb(env)->d[mmu_idx].iotlb); + env_tlb(env)->f[mmu_idx].table =3D g_try_new(CPUTLBEntry, new_size= ); + env_tlb(env)->d[mmu_idx].iotlb =3D g_try_new(CPUIOTLBEntry, new_si= ze); } } =20 static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_id= x) { tlb_mmu_resize_locked(env, mmu_idx); - memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx)); - env->tlb_d[mmu_idx].n_used_entries =3D 0; + memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx)); + env_tlb(env)->d[mmu_idx].n_used_entries =3D 0; } =20 static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu= _idx) { - env->tlb_d[mmu_idx].n_used_entries++; + env_tlb(env)->d[mmu_idx].n_used_entries++; } =20 static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu= _idx) { - env->tlb_d[mmu_idx].n_used_entries--; + env_tlb(env)->d[mmu_idx].n_used_entries--; } =20 void tlb_init(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - qemu_spin_init(&env->tlb_c.lock); + qemu_spin_init(&env_tlb(env)->c.lock); =20 /* Ensure that cpu_reset performs a full flush. */ - env->tlb_c.dirty =3D ALL_MMUIDX_BITS; + env_tlb(env)->c.dirty =3D ALL_MMUIDX_BITS; =20 tlb_dyn_init(env); } @@ -273,9 +274,9 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, siz= e_t *pelide) CPU_FOREACH(cpu) { CPUArchState *env =3D cpu->env_ptr; =20 - full +=3D atomic_read(&env->tlb_c.full_flush_count); - part +=3D atomic_read(&env->tlb_c.part_flush_count); - elide +=3D atomic_read(&env->tlb_c.elide_flush_count); + full +=3D atomic_read(&env_tlb(env)->c.full_flush_count); + part +=3D atomic_read(&env_tlb(env)->c.part_flush_count); + elide +=3D atomic_read(&env_tlb(env)->c.elide_flush_count); } *pfull =3D full; *ppart =3D part; @@ -285,10 +286,11 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, s= ize_t *pelide) static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) { tlb_table_flush_by_mmuidx(env, mmu_idx); - memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); - env->tlb_d[mmu_idx].large_page_addr =3D -1; - env->tlb_d[mmu_idx].large_page_mask =3D -1; - env->tlb_d[mmu_idx].vindex =3D 0; + env_tlb(env)->d[mmu_idx].large_page_addr =3D -1; + env_tlb(env)->d[mmu_idx].large_page_mask =3D -1; + env_tlb(env)->d[mmu_idx].vindex =3D 0; + memset(env_tlb(env)->d[mmu_idx].vtable, -1, + sizeof(env_tlb(env)->d[0].vtable)); } =20 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) @@ -301,31 +303,31 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *= cpu, run_on_cpu_data data) =20 tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); =20 - all_dirty =3D env->tlb_c.dirty; + all_dirty =3D env_tlb(env)->c.dirty; to_clean =3D asked & all_dirty; all_dirty &=3D ~to_clean; - env->tlb_c.dirty =3D all_dirty; + env_tlb(env)->c.dirty =3D all_dirty; =20 for (work =3D to_clean; work !=3D 0; work &=3D work - 1) { int mmu_idx =3D ctz32(work); tlb_flush_one_mmuidx_locked(env, mmu_idx); } =20 - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 if (to_clean =3D=3D ALL_MMUIDX_BITS) { - atomic_set(&env->tlb_c.full_flush_count, - env->tlb_c.full_flush_count + 1); + atomic_set(&env_tlb(env)->c.full_flush_count, + env_tlb(env)->c.full_flush_count + 1); } else { - atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(to_clean)); + atomic_set(&env_tlb(env)->c.part_flush_count, + env_tlb(env)->c.part_flush_count + ctpop16(to_clean)); if (to_clean !=3D asked) { - atomic_set(&env->tlb_c.elide_flush_count, - env->tlb_c.elide_flush_count + + atomic_set(&env_tlb(env)->c.elide_flush_count, + env_tlb(env)->c.elide_flush_count + ctpop16(asked & ~to_clean)); } } @@ -410,11 +412,12 @@ static inline bool tlb_flush_entry_locked(CPUTLBEntry= *tlb_entry, static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, target_ulong page) { + CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; int k; =20 assert_cpu_is_self(ENV_GET_CPU(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - if (tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page)) { + if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); } } @@ -423,8 +426,8 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchSt= ate *env, int mmu_idx, static void tlb_flush_page_locked(CPUArchState *env, int midx, target_ulong page) { - target_ulong lp_addr =3D env->tlb_d[midx].large_page_addr; - target_ulong lp_mask =3D env->tlb_d[midx].large_page_mask; + target_ulong lp_addr =3D env_tlb(env)->d[midx].large_page_addr; + target_ulong lp_mask =3D env_tlb(env)->d[midx].large_page_mask; =20 /* Check if we need to flush due to large pages. */ if ((page & lp_mask) =3D=3D lp_addr) { @@ -459,13 +462,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", addr, mmu_idx_bitmap); =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -609,22 +612,22 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; unsigned int n =3D tlb_n_entries(env, mmu_idx); =20 for (i =3D 0; i < n; i++) { - tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], star= t1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i= ], + start1, length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], st= art1, - length); + tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[= i], + start1, length); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } =20 /* Called with tlb_c.lock held */ @@ -646,7 +649,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -654,10 +657,10 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); + tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], vad= dr); } } - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -665,7 +668,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) static void tlb_add_large_page(CPUArchState *env, int mmu_idx, target_ulong vaddr, target_ulong size) { - target_ulong lp_addr =3D env->tlb_d[mmu_idx].large_page_addr; + target_ulong lp_addr =3D env_tlb(env)->d[mmu_idx].large_page_addr; target_ulong lp_mask =3D ~(size - 1); =20 if (lp_addr =3D=3D (target_ulong)-1) { @@ -675,13 +678,13 @@ static void tlb_add_large_page(CPUArchState *env, int= mmu_idx, /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ - lp_mask &=3D env->tlb_d[mmu_idx].large_page_mask; + lp_mask &=3D env_tlb(env)->d[mmu_idx].large_page_mask; while (((lp_addr ^ vaddr) & lp_mask) !=3D 0) { lp_mask <<=3D 1; } } - env->tlb_d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; - env->tlb_d[mmu_idx].large_page_mask =3D lp_mask; + env_tlb(env)->d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; + env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 /* Add a new TLB entry. At most one entry for a given virtual address @@ -696,6 +699,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, int mmu_idx, target_ulong size) { CPUArchState *env =3D cpu->env_ptr; + CPUTLB *tlb =3D env_tlb(env); + CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; MemoryRegionSection *section; unsigned int index; target_ulong address; @@ -757,10 +762,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * a longer critical section, but this is not a concern since the TLB = lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&tlb->c.lock); =20 /* Note that the tlb is no longer clean. */ - env->tlb_c.dirty |=3D 1 << mmu_idx; + tlb->c.dirty |=3D 1 << mmu_idx; =20 /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -770,12 +775,12 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * different page; otherwise just overwrite the stale data. */ if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) { - unsigned vidx =3D env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; - CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; + unsigned vidx =3D desc->vindex++ % CPU_VTLB_SIZE; + CPUTLBEntry *tv =3D &desc->vtable[vidx]; =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; + desc->viotlb[vidx] =3D desc->iotlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -792,8 +797,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - env->iotlb[mmu_idx][index].addr =3D iotlb - vaddr_page; - env->iotlb[mmu_idx][index].attrs =3D attrs; + desc->iotlb[index].addr =3D iotlb - vaddr_page; + desc->iotlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -829,7 +834,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, =20 copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&tlb->c.lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -976,21 +981,28 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, =20 assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { - CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp =3D tlb_read_ofs(vtlb, elt_ofs); + CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; + target_ulong cmp; + + /* elt_ofs might correspond to .addr_write, so use atomic_read */ +#if TCG_OVERSIZED_GUEST + cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); +#else + cmp =3D atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); +#endif =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; + CPUTLBEntry tmptlb, *tlb =3D &env_tlb(env)->f[mmu_idx].table[i= ndex]; =20 - qemu_spin_lock(&env->tlb_c.lock); + qemu_spin_lock(&env_tlb(env)->c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_c.lock); + qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; - CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; + CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; + CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; return true; } @@ -1293,8 +1305,8 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, } } =20 - res =3D io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr, - retaddr, access_type, size); + res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], + mmu_idx, addr, retaddr, access_type, size); return handle_bswap(res, size, big_endian); } =20 @@ -1541,7 +1553,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, } } =20 - io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx, + io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, handle_bswap(val, size, big_endian), addr, retaddr, size); return; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 092f0df3c4..f5440e57dd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14134,7 +14134,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); + env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0); #endif } =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 9e1dad9696..90957593a3 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1637,12 +1637,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool = is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xffffff); =20 /* Load and compare a TLB entry, emitting the conditional jump to the @@ -1653,8 +1649,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_ofs =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 7316504c9d..38de6d59c7 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1220,12 +1220,8 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGRe= g argreg, =20 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0xfffff); =20 /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter @@ -1236,8 +1232,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c0443da4af..5f5b886c04 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,10 +1730,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_mask[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_table[mem_index])); + offsetof(CPUArchState, tlb_.f[mem_index].table)); =20 /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 7cafd4a790..ef6633587e 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1202,14 +1202,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int= i, TCGReg al, TCGReg ah) return i; } =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D 0x8000); - /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1223,8 +1215,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 30c095d3d5..d69c18ac1e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1498,10 +1498,6 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ @@ -1514,8 +1510,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemO= p opc, =3D (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 6497a4dab2..96c33bf621 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -962,14 +962,6 @@ static void * const qemu_st_helpers[16] =3D { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D 0x800); - static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -982,8 +974,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, int mask_off, table_off; TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); if (table_off > 0x7ff) { int mask_hi =3D mask_off - sextreg(mask_off, 0, 12); int table_hi =3D table_off - sextreg(table_off, 0, 12); diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 331d51852c..4d896d0b58 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1539,9 +1539,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, #include "tcg-ldst.inc.c" =20 /* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1]) - > 0x7ffff); -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) > 0x7ffff); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB @@ -1553,8 +1551,8 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg = addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); int ofs, a_off; uint64_t tlb_mask; =20 diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 83295955a7..066cb0e892 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1075,19 +1075,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int = count) The result of the TLB comparison is in %[ix]cc. The sanitized address is in the returned register, maybe %o0. The TLB addend is in %o1. */ =20 -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >=3D (1 << 13)); - static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg base =3D TCG_AREG0; const TCGReg r0 =3D TCG_REG_O0; const TCGReg r1 =3D TCG_REG_O1; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680589; cv=none; d=zoho.com; s=zohoarc; b=giyJMAO0DHLpcDQjBVNbgMYH9d67o4yIPJoNDa4m4m4tb/CFpAWBS6LVt28nkgDva5DpF29joDAs7kSwPCAqOKkkULxyoHBVWbL8cwuAPnedbKlZ5C3B2RKjl+9vdbgbMbl1bR4yY8PuDrLSVMnPVit4NVsEZHBtK1Bd6LIuOKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559680589; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=EmYLkcDIGbKn3Eu+glogkhw4R1ShZ/FLvb3Vj23ThZ4=; b=MpdRcHlFNQ0SUQzJGGV0w789NWofX1qJYGujrp7v3/djzQlxSOpoPxIU3HPCdBuqvR95zXQbviwwCahAveyUTL+NobCwx5EQBBgujtpvWmhtcBXmCcpAUynmqOvLQ6uudd21q/NimSYaOUdlxWap/AURO46f1Tw6RLBR+Fi26bo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559680589682564.3771552188465; Tue, 4 Jun 2019 13:36:29 -0700 (PDT) Received: from localhost ([127.0.0.1]:57617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGAL-0002Kl-GH for importer@patchew.org; Tue, 04 Jun 2019 16:36:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8D-0000xb-7r for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8B-00042m-7Z for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:05 -0400 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:38817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8B-00042Q-0N for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:03 -0400 Received: by mail-ot1-x343.google.com with SMTP id d17so6677714oth.5 for ; Tue, 04 Jun 2019 13:34:02 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.33.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=EmYLkcDIGbKn3Eu+glogkhw4R1ShZ/FLvb3Vj23ThZ4=; b=YqBUoRhaP+50SA4uiTr/hg7nf5TYAAB+bzH70ysRLOc34f6W81n0NAXYF56p3vhM1T a4tk5AOo8rDCVLeY6dXiNsV+KNbMXfAW+FwYHKM6M3TGxRC0wqeUaZQNhlV93R0i3iIK 7Gk24c9uKPxWsw5q0TQjNxJ9a1pZFXDgwFQRzjPMotu4rAZTx8NS4i5e4C8e2CNlxHzQ 4TeZKZ9jF+Wg//LyKT6FfDGm3+J14N3eODxRkzP2ZHCYrZBaQqLm+yYQ47b5nqlkx0y7 WE2tk64lF6VJXE/mP4i7vsXryiz9MExiGyyLG43ku4M7atuTNiTomUFgvYURaPSZlAi1 yQkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=EmYLkcDIGbKn3Eu+glogkhw4R1ShZ/FLvb3Vj23ThZ4=; b=D6Fo/i8j4u7sULuxibP6vgJ8W2tuCKVN0tn1ePA44ydapV+pPcJXoKOYH2x8JBK3H8 Z42+Pug7LYtI9atN26VG6+9wiEoB8f9QDAy4yTql0I3JBuin1L7z1QuCjjVLi6/2d7tG jsc8U2gZmNHtdSwg6kH/k2WYVAw6WOUHUAAs1XXh2+KsRyKf2WzrE5v7miaC35YcFTds 1WQq13LQZRQDZG8b48dw6i/lTBm+vlXllUQkyba4hN576mzjSacuxAL69/3PrgKRcyeF +7sVnNF0s9G6BT7tkHA2EypvYQIPFDrzas3d8Ecwo2eN/XAqWwONe+AqivT4Ll8tx+Ot ITXg== X-Gm-Message-State: APjAAAVQOUkgRIgZVTZZqR0rHk52NwnbyI98HyeyEGa4sjKC1HgfdI1B TsDBGSOfucxv3L99JWmhgBdu3UtDboUQyw== X-Google-Smtp-Source: APXvYqxaYPbkfHMxPIMT5Lb8E6KyUm+zx69SmiIwpjLfvIbn2lELLIzzw1lamopMcKgfZC/6L4NyQw== X-Received: by 2002:a9d:4d05:: with SMTP id n5mr6215027otf.361.1559680441681; Tue, 04 Jun 2019 13:34:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:16 -0500 Message-Id: <20190604203351.27778-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 04/39] cpu: Define CPUArchState with typedef X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 4 ++-- target/arm/cpu.h | 4 ++-- target/cris/cpu.h | 4 ++-- target/hppa/cpu.h | 4 ++-- target/i386/cpu.h | 5 ++--- target/lm32/cpu.h | 5 ++--- target/m68k/cpu.h | 4 ++-- target/microblaze/cpu.h | 5 ++--- target/mips/cpu.h | 6 ++---- target/moxie/cpu.h | 4 ++-- target/nios2/cpu.h | 5 ++--- target/openrisc/cpu.h | 4 ++-- target/ppc/cpu.h | 4 ++-- target/riscv/cpu.h | 4 ++-- target/s390x/cpu.h | 8 ++++---- target/sh4/cpu.h | 4 ++-- target/sparc/cpu.h | 4 ++-- target/tilegx/cpu.h | 4 ++-- target/tricore/cpu.h | 6 +----- target/unicore32/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- 21 files changed, 43 insertions(+), 53 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index dc1883f0f1..9ec92bf09d 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -26,8 +26,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUAlphaState - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 @@ -306,6 +304,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler =20 +typedef CPUAlphaState CPUArchState; + #include "exec/cpu-all.h" =20 enum { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f8020b4823..ccf581a84c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,8 +29,6 @@ /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUARMState - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -3127,6 +3125,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } } =20 +typedef CPUARMState CPUArchState; + #include "exec/cpu-all.h" =20 /* Bit usage in the TB flags field: bit 31 indicates whether we are diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 25408c2bf7..2ee5417ead 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -25,8 +25,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUCRISState - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -286,6 +284,8 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 +typedef CPUCRISState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *p= c, diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fb527eba88..7fd755a753 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -31,8 +31,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 -#define CPUArchState struct CPUHPPAState - #define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 @@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) =20 +typedef CPUHPPAState CPUArchState; + #include "exec/cpu-all.h" =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 36f5095768..81931fc510 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1,4 +1,3 @@ - /* * i386 virtual CPU header * @@ -44,8 +43,6 @@ #define ELF_MACHINE_UNAME "i686" #endif =20 -#define CPUArchState struct CPUX86State - enum { R_EAX =3D 0, R_ECX =3D 1, @@ -1755,6 +1752,8 @@ static inline target_long lshift(target_long x, int n) /* translate.c */ void tcg_x86_init(void); =20 +typedef CPUX86State CPUArchState; + #include "exec/cpu-all.h" #include "svm.h" =20 diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index e75110c4e0..86f6c7b0af 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -24,9 +24,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPULM32State - -struct CPULM32State; typedef struct CPULM32State CPULM32State; =20 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) @@ -259,6 +256,8 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +typedef CPULM32State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *p= c, diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index e99c102302..4465a66145 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -25,8 +25,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 -#define CPUArchState struct CPUM68KState - #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -538,6 +536,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); =20 +typedef CPUM68KState CPUArchState; + #include "exec/cpu-all.h" =20 /* TB flags */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b8db8ca9a3..6170fd452f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -25,9 +25,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 -#define CPUArchState struct CPUMBState - -struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -368,6 +365,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +typedef CPUMBState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 34e7aec4d0..6f65822bb1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -3,8 +3,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUMIPSState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" @@ -13,8 +11,6 @@ =20 #define TCG_GUEST_DEFAULT_MO (0) =20 -struct CPUMIPSState; - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 /* MSA Context */ @@ -1116,6 +1112,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) return hflags_mmu_index(env->hflags); } =20 +typedef CPUMIPSState CPUArchState; + #include "exec/cpu-all.h" =20 /* diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 7164dd7f5f..1de0515848 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUMoxieState - #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 #define MOXIE_EX_IRQ 2 @@ -119,6 +117,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) return 0; } =20 +typedef CPUMoxieState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *= pc, diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c4ccea9cf0..cc8e0ab771 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -25,9 +25,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUNios2State - -struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -249,6 +246,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) return env->regs[CR_STATUS] & CR_STATUS_PIE; } =20 +typedef CPUNios2State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 3727efabf3..98361cb041 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUOpenRISCState - /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; =20 @@ -365,6 +363,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 +typedef CPUOpenRISCState CPUArchState; + #include "exec/cpu-all.h" =20 #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 02ca453df3..6478fe7c91 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -34,8 +34,6 @@ #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 -#define CPUArchState struct CPUPPCState - #if defined(TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -1377,6 +1375,8 @@ void ppc_compat_add_property(Object *obj, const char = *name, Error **errp); #endif /* defined(TARGET_PPC64) */ =20 +typedef CPUPPCState CPUArchState; + #include "exec/cpu-all.h" =20 /*************************************************************************= ****/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bc517dbad8..509aae0613 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,8 +27,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define CPUArchState struct CPURISCVState - #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -336,6 +334,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 +typedef CPURISCVState CPUArchState; + #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 3a82ea53e1..5ca53f48f8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,13 +28,9 @@ =20 #define ELF_MACHINE_UNAME "S390X" =20 -#define CPUArchState struct CPUS390XState - /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#include "exec/cpu-all.h" - #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define MMU_MODE0_SUFFIX _primary @@ -797,4 +793,8 @@ void s390_init_sigp(void); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 +typedef CPUS390XState CPUArchState; + +#include "exec/cpu-all.h" + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 7af6ff5d57..d7a8723d39 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -36,8 +36,6 @@ #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) =20 -#define CPUArchState struct CPUSH4State - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -282,6 +280,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } } =20 +typedef CPUSH4State CPUArchState; + #include "exec/cpu-all.h" =20 /* Memory access type */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index bcfdf513cf..fc392c6e87 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -14,8 +14,6 @@ #define TARGET_DPREGS 32 #endif =20 -#define CPUArchState struct CPUSPARCState - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ @@ -731,6 +729,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 +typedef CPUSPARCState CPUArchState; + #include "exec/cpu-all.h" =20 #ifdef TARGET_SPARC64 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 429a6c6b43..2fbf14d508 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUTLGState - /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */ @@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 +typedef CPUTLGState CPUArchState; + #include "exec/cpu-all.h" =20 void tilegx_tcg_init(void); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index bccde45a07..5d3072f2db 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -25,10 +25,6 @@ #include "exec/cpu-defs.h" #include "tricore-defs.h" =20 -#define CPUArchState struct CPUTriCoreState - -struct CPUTriCoreState; - struct tricore_boot_info; =20 typedef struct tricore_def_t tricore_def_t; @@ -382,7 +378,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) return 0; } =20 - +typedef CPUTriCoreState CPUArchState; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index a4c4ea328e..48562949b1 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -16,8 +16,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUUniCore32State - typedef struct CPUUniCore32State { /* Regs for current mode. */ uint32_t regs[32]; @@ -153,6 +151,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) return (env->uncached_asr & ASR_M) =3D=3D ASR_MODE_USER ? 1 : 0; } =20 +typedef CPUUniCore32State CPUArchState; + #include "exec/cpu-all.h" =20 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 0c6afd43a4..e164e18f18 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -38,8 +38,6 @@ /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUXtensaState - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, @@ -801,6 +799,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } } =20 +typedef CPUXtensaState CPUArchState; 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X-Received-From: 2607:f8b0:4864:20::329 Subject: [Qemu-devel] [PATCH v4 05/39] cpu: Define ArchCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 21 files changed, 21 insertions(+) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 9ec92bf09d..5af0b6c542 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -305,6 +305,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_signal_handler cpu_alpha_signal_handler =20 typedef CPUAlphaState CPUArchState; +typedef AlphaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ccf581a84c..4ebb6349f1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3126,6 +3126,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } =20 typedef CPUARMState CPUArchState; +typedef ARMCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 2ee5417ead..e978eb9539 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -285,6 +285,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 typedef CPUCRISState CPUArchState; +typedef CRISCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7fd755a753..6eef107370 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -231,6 +231,7 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; +typedef HPPACPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 81931fc510..65f8f4d16c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1753,6 +1753,7 @@ static inline target_long lshift(target_long x, int n) void tcg_x86_init(void); =20 typedef CPUX86State CPUArchState; +typedef X86CPU ArchCPU; =20 #include "exec/cpu-all.h" #include "svm.h" diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 86f6c7b0af..08c360bd16 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -257,6 +257,7 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, bool probe, uintptr_t retaddr); =20 typedef CPULM32State CPUArchState; +typedef LM32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4465a66145..1d30b73bdf 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -537,6 +537,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); =20 typedef CPUM68KState CPUArchState; +typedef M68kCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 6170fd452f..5a7fe3cbf8 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -366,6 +366,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, bool probe, uintptr_t retaddr); =20 typedef CPUMBState CPUArchState; +typedef MicroBlazeCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6f65822bb1..12527ca104 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1113,6 +1113,7 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) } =20 typedef CPUMIPSState CPUArchState; +typedef MIPSCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 1de0515848..b27b0eabae 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -118,6 +118,7 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) } =20 typedef CPUMoxieState CPUArchState; +typedef MoxieCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index cc8e0ab771..5e51f1ae3f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -247,6 +247,7 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) } =20 typedef CPUNios2State CPUArchState; +typedef Nios2CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 98361cb041..496895693e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -364,6 +364,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 typedef CPUOpenRISCState CPUArchState; +typedef OpenRISCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6478fe7c91..17e7213be9 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1376,6 +1376,7 @@ void ppc_compat_add_property(Object *obj, const char = *name, #endif /* defined(TARGET_PPC64) */ =20 typedef CPUPPCState CPUArchState; +typedef PowerPCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 509aae0613..8ee5051119 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -335,6 +335,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5ca53f48f8..6d1b0f273a 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -794,6 +794,7 @@ void s390_init_sigp(void); S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 typedef CPUS390XState CPUArchState; +typedef S390CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d7a8723d39..1bdc997290 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -281,6 +281,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } =20 typedef CPUSH4State CPUArchState; +typedef SuperHCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index fc392c6e87..ba5904e05a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -730,6 +730,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) } =20 typedef CPUSPARCState CPUArchState; +typedef SPARCCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 2fbf14d508..042a7a0c71 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -151,6 +151,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 typedef CPUTLGState CPUArchState; +typedef TileGXCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 5d3072f2db..8d660df34a 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -379,6 +379,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) } =20 typedef CPUTriCoreState CPUArchState; +typedef TriCoreCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 48562949b1..5c9c4d98c0 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -152,6 +152,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) } =20 typedef CPUUniCore32State CPUArchState; +typedef UniCore32CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e164e18f18..6e6fb1d893 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -800,6 +800,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } =20 typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; =20 #include "exec/cpu-all.h" =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680819; 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X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 06/39] cpu: Replace ENV_GET_CPU with env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 8 +-- include/exec/cpu-all.h | 12 +++++ include/exec/cpu_ldst_template.h | 6 +-- include/exec/cpu_ldst_useronly_template.h | 6 +-- include/exec/softmmu-semi.h | 16 +++--- linux-user/cpu_loop-common.h | 2 +- target/alpha/cpu.h | 2 - target/arm/cpu.h | 2 - target/cris/cpu.h | 2 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 2 - target/lm32/cpu.h | 2 - target/m68k/cpu.h | 2 - target/microblaze/cpu.h | 2 - target/mips/cpu.h | 2 - target/moxie/cpu.h | 2 - target/nios2/cpu.h | 2 - target/openrisc/cpu.h | 2 - target/ppc/cpu.h | 2 - target/riscv/cpu.h | 1 - target/s390x/cpu.h | 2 - target/sh4/cpu.h | 2 - target/sparc/cpu.h | 2 - target/tilegx/cpu.h | 2 - target/tricore/cpu.h | 2 - target/unicore32/cpu.h | 2 - target/xtensa/cpu.h | 2 - accel/tcg/cputlb.c | 38 +++++++------- accel/tcg/tcg-runtime.c | 4 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/syscall.c | 6 +-- hw/semihosting/console.c | 2 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/cris/cpu_loop.c | 2 +- linux-user/elfload.c | 6 +-- linux-user/m68k/cpu_loop.c | 2 +- linux-user/main.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- linux-user/nios2/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/signal.c | 8 +-- linux-user/syscall.c | 18 +++---- linux-user/uname.c | 2 +- target/arm/helper.c | 42 ++++++++-------- target/hppa/op_helper.c | 2 +- target/i386/hax-all.c | 6 +-- target/i386/hvf/x86_decode.c | 22 ++++----- target/i386/hvf/x86_emu.c | 60 +++++++++++++---------- target/i386/mem_helper.c | 4 +- target/m68k/op_helper.c | 2 +- target/nios2/mmu.c | 4 +- target/nios2/op_helper.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/s390x/gdbstub.c | 24 ++++----- target/s390x/mem_helper.c | 2 +- target/sh4/op_helper.c | 2 +- docs/devel/tracing.txt | 4 +- scripts/tracetool/format/tcg_helper_c.py | 2 +- 59 files changed, 175 insertions(+), 197 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 685602b076..5aaf186253 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -62,21 +62,21 @@ #define ATOMIC_TRACE_RMW do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fal= se); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, \ info | TRACE_MEM_ST); \ } while (0) =20 #define ATOMIC_TRACE_LD do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, fal= se); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) =20 # define ATOMIC_TRACE_ST do { \ uint8_t info =3D glue(trace_mem_build_info_no_se, MEND)(SHIFT, tru= e); \ \ - trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \ + trace_guest_mem_before_exec(env_cpu(env), addr, info); \ } while (0) =20 /* Define host-endian atomic operations. Note that END is used within diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index da07ce311f..454f6d663f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,4 +371,16 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); + return &arch_cpu->parent_obj; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index 0f061d47ef..af7e0b49f2 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -89,7 +89,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArch= State *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif =20 @@ -128,7 +128,7 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUAr= chState *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif =20 @@ -170,7 +170,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, =20 #if !defined(SOFTMMU_CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif =20 diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_l= dst_useronly_template.h index 0fd6019af0..bc45e2b8d4 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -66,7 +66,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env,= abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); #endif return glue(glue(ld, USUFFIX), _p)(g2h(ptr)); @@ -90,7 +90,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env,= abi_ptr ptr) { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); #endif return glue(glue(lds, SUFFIX), _p)(g2h(ptr)); @@ -116,7 +116,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env= , abi_ptr ptr, { #if !defined(CODE_ACCESS) trace_guest_mem_before_exec( - ENV_GET_CPU(env), ptr, + env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); #endif glue(glue(st, SUFFIX), _p)(g2h(ptr), v); diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h index 7eefad8f39..970837992e 100644 --- a/include/exec/softmmu-semi.h +++ b/include/exec/softmmu-semi.h @@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, = target_ulong addr) { uint64_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 0); return tswap64(val); } =20 @@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, = target_ulong addr) { uint32_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 0); return tswap32(val); } =20 @@ -30,7 +30,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, t= arget_ulong addr) { uint8_t val; =20 - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &val, 1, 0); return val; } =20 @@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env, target_ulong addr, uint64_t val) { val =3D tswap64(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 1); } =20 static inline void softmmu_tput32(CPUArchState *env, target_ulong addr, uint32_t val) { val =3D tswap32(val); - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1); + cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 1); } #define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; }) #define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; }) @@ -63,7 +63,7 @@ static void *softmmu_lock_user(CPUArchState *env, /* TODO: Make this something that isn't fixed size. */ p =3D malloc(len); if (p && copy) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 0); } return p; } @@ -79,7 +79,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, = target_ulong addr) return NULL; } do { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0); + cpu_memory_rw_debug(env_cpu(env), addr, &c, 1, 0); addr++; *(p++) =3D c; } while (c); @@ -90,7 +90,7 @@ static void softmmu_unlock_user(CPUArchState *env, void *= p, target_ulong addr, target_ulong len) { if (len) { - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1); + cpu_memory_rw_debug(env_cpu(env), addr, p, len, 1); } free(p); } diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index c1d554a249..8828af28a4 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -24,7 +24,7 @@ =20 #define EXCP_DUMP(env, fmt, ...) \ do { \ - CPUState *cs =3D ENV_GET_CPU(env); \ + CPUState *cs =3D env_cpu(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ cpu_dump_state(cs, stderr, 0); \ if (qemu_log_separate()) { \ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 5af0b6c542..e391195be0 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,6 @@ static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState= *env) return container_of(env, AlphaCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e)) - #define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ebb6349f1..1afd1da491 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -922,8 +922,6 @@ void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); =20 -#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) - #define ENV_OFFSET offsetof(ARMCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/cris/cpu.h b/target/cris/cpu.h index e978eb9539..0746d19f38 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -188,8 +188,6 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState *e= nv) return container_of(env, CRISCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e)) - #define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6eef107370..0cb1fc8800 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -227,7 +227,6 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) return container_of(env, HPPACPU, env); } =20 -#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 65f8f4d16c..103fd709b0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1485,8 +1485,6 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *en= v) return container_of(env, X86CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) - #define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 08c360bd16..ad9452eb9f 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -200,8 +200,6 @@ static inline LM32CPU *lm32_env_get_cpu(CPULM32State *e= nv) return container_of(env, LM32CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 1d30b73bdf..2e53cde076 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,8 +168,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *e= nv) return container_of(env, M68kCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e)) - #define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 5a7fe3cbf8..6e68e00e1f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -315,8 +315,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState = *env) return container_of(env, MicroBlazeCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 12527ca104..e684572dda 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1076,8 +1076,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) return container_of(env, MIPSCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list(void); diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b27b0eabae..275fb9bfbb 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -95,8 +95,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *= env) return container_of(env, MoxieCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e)) - #define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 5e51f1ae3f..ae6cf1b4d1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -199,8 +199,6 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State= *env) return NIOS2_CPU(container_of(env, Nios2CPU, env)); } =20 -#define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e)) - #define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 496895693e..50f79d540b 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -322,8 +322,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpen= RISCState *env) return container_of(env, OpenRISCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(void); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 17e7213be9..ec92a8e7af 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1208,8 +1208,6 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState= *env) return container_of(env, PowerPCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8ee5051119..9ab038bac3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -244,7 +244,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; =20 -#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) #define ENV_OFFSET offsetof(RISCVCPU, env) =20 void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 6d1b0f273a..9cdd831a77 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -168,8 +168,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *= env) return container_of(env, S390CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) - #define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1bdc997290..8b17e6d63e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -212,8 +212,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *en= v) return container_of(env, SuperHCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ba5904e05a..e29421349b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -537,8 +537,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState= *env) return container_of(env, SPARCCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 042a7a0c71..135df63523 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -143,8 +143,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) return container_of(env, TileGXCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 8d660df34a..4a2a955cc5 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -213,8 +213,6 @@ static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCor= eState *env) return TRICORE_CPU(container_of(env, TriCoreCPU, env)); } =20 -#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e)) - #define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 5c9c4d98c0..e91cec4d2e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -81,8 +81,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32= State *env) return container_of(env, UniCore32CPU, env); } =20 -#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e)) - #define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6e6fb1d893..3de53cb5d0 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -564,8 +564,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) return container_of(env, XtensaCPU, env); } =20 -#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) - #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a3a39e9a77..baa3eb8f92 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -415,7 +415,7 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchSt= ate *env, int mmu_idx, CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; int k; =20 - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { if (tlb_flush_entry_locked(&d->vtable[k], page)) { tlb_n_used_entries_dec(env, mmu_idx); @@ -883,7 +883,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, int size) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -927,7 +927,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, int size) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -979,7 +979,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, { size_t vidx; =20 - assert_cpu_is_self(ENV_GET_CPU(env)); + assert_cpu_is_self(env_cpu(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; target_ulong cmp; @@ -1029,7 +1029,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, = target_ulong addr) =20 if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); + tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); } @@ -1067,7 +1067,7 @@ void probe_write(CPUArchState *env, target_ulong addr= , int size, int mmu_idx, if (!tlb_hit(tlb_addr_write(entry), addr)) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } } @@ -1101,7 +1101,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad= dr, uintptr_t index =3D tlb_index(env, mmu_idx, addr); =20 if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cs); =20 if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0))= { @@ -1144,7 +1144,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, /* Enforce guest required alignment. */ if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -1160,7 +1160,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, /* Check TLB entry and enforce page permissions. */ if (!tlb_hit(tlb_addr, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); tlbe =3D tlb_entry(env, mmu_idx, addr); @@ -1177,7 +1177,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 /* Let the guest notice RMW on a write-only page. */ if (unlikely(tlbe->addr_read !=3D (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD, + tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD, mmu_idx, retaddr); /* Since we don't support reads and writes to different addresses, and we do have the proper page loaded for write, this shouldn't @@ -1190,7 +1190,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, ndi->active =3D false; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { ndi->active =3D true; - memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr, + memory_notdirty_write_prepare(ndi, env_cpu(env), addr, qemu_ram_addr_from_host_nofail(hosta= ddr), 1 << s_bits); } @@ -1198,7 +1198,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, return hostaddr; =20 stop_the_world: - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } =20 #ifdef TARGET_WORDS_BIGENDIAN @@ -1263,7 +1263,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, =20 /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type, + cpu_unaligned_access(env_cpu(env), addr, access_type, mmu_idx, retaddr); } =20 @@ -1271,7 +1271,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), addr, size, + tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -1292,7 +1292,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - tlb_fill(ENV_GET_CPU(env), addr, size, + tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -1511,7 +1511,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -1519,7 +1519,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -1540,7 +1540,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); @@ -1580,7 +1580,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, if (!tlb_hit_page(tlb_addr2, page2) && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2 & TARGET_PAGE_MASK)) { - tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, + tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE, mmu_idx, retaddr); } =20 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0d4484406..8a1e408e31 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -146,7 +146,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) =20 void *HELPER(lookup_tb_ptr)(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -165,5 +165,5 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 void HELPER(exit_atomic)(CPUArchState *env) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 20b59f93f4..52d94facf0 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1732,7 +1732,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 tcg_func_start(tcg_ctx); =20 - tcg_ctx->cpu =3D ENV_GET_CPU(env); + tcg_ctx->cpu =3D env_cpu(env); gen_intermediate_code(cpu, tb, max_insns); tcg_ctx->cpu =3D NULL; =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8cfbeb1b56..cb5f4b19c5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -680,7 +680,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, { /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); + cpu_loop_exit_atomic(env_cpu(env), retaddr); } helper_retaddr =3D retaddr; return g2h(addr); diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index 66492aaf5d..1ee6195d9f 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -315,7 +315,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi= _long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 @@ -413,7 +413,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_= long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 @@ -488,7 +488,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi= _long arg1, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; void *p; =20 diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index 466ea6dade..4ab7533bb8 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -40,7 +40,7 @@ int qemu_semihosting_log_out(const char *s, int len) */ static GString *copy_user_string(CPUArchState *env, target_ulong addr, int= len) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); GString *s =3D g_string_sized_new(len ? len : 128); uint8_t c; bool done; diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ee68aa60bf..b7e7a6323c 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -423,7 +423,7 @@ void cpu_loop(CPUARMState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index af8c128bf8..7ec36cb0b5 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -83,7 +83,7 @@ void cpu_loop(CPUCRISState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a57b7049dd..5e9e3dee69 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3349,7 +3349,7 @@ static int write_note(struct memelfnote *men, int fd) =20 static void fill_thread_info(struct elf_note_info *info, const CPUArchStat= e *env) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu =3D env_cpu((CPUArchState *)env); TaskState *ts =3D (TaskState *)cpu->opaque; struct elf_thread_status *ets; =20 @@ -3379,7 +3379,7 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu =3D env_cpu((CPUArchState *)env); TaskState *ts =3D (TaskState *)cpu->opaque; int i; =20 @@ -3503,7 +3503,7 @@ static int write_note_info(struct elf_note_info *info= , int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)env); + const CPUState *cpu =3D env_cpu((CPUArchState *)env); const TaskState *ts =3D (const TaskState *)cpu->opaque; struct vm_area_struct *vma =3D NULL; char corefile[PATH_MAX]; diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index bfb41bbcc5..42d8d841ea 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -130,7 +130,7 @@ void cpu_loop(CPUM68KState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/main.c b/linux-user/main.c index 689bcf436d..97ca22bb04 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -180,7 +180,7 @@ void init_task_state(TaskState *ts) =20 CPUArchState *cpu_copy(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); CPUState *new_cpu =3D cpu_create(cpu_type); CPUArchState *new_env =3D new_cpu->env_ptr; CPUBreakpoint *bp; diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 61dc90d51c..828137cd84 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -654,7 +654,7 @@ error: =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 5aa1eca740..9869083fa1 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUNios2State *env) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D NIOS2_CPU(cs); target_siginfo_t info; int trapnr, ret; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index a9bac4ca79..31700f75d0 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -116,7 +116,7 @@ void cpu_loop(CPURISCVState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; struct image_info *info =3D ts->info; =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index 44b2d3b35a..7c5588adff 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -626,7 +626,7 @@ static void QEMU_NORETURN dump_core_and_abort(int targe= t_sig) int queue_signal(CPUArchState *env, int sig, int si_type, target_siginfo_t *info) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; =20 trace_user_queue_signal(env, sig); @@ -651,7 +651,7 @@ static void host_signal_handler(int host_signum, siginf= o_t *info, void *puc) { CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D cpu->opaque; =20 int sig; @@ -842,7 +842,7 @@ int do_sigaction(int sig, const struct target_sigaction= *act, static void handle_pending_signal(CPUArchState *cpu_env, int sig, struct emulated_sigtable *k) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_ulong handler; sigset_t set; target_sigset_t target_old_set; @@ -927,7 +927,7 @@ static void handle_pending_signal(CPUArchState *cpu_env= , int sig, =20 void process_pending_signals(CPUArchState *cpu_env) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); int sig; TaskState *ts =3D cpu->opaque; sigset_t set; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5e29e675e9..d1a2c7831f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -5484,7 +5484,7 @@ static void *clone_func(void *arg) rcu_register_thread(); tcg_register_thread(); env =3D info->env; - cpu =3D ENV_GET_CPU(env); + cpu =3D env_cpu(env); thread_cpu =3D cpu; ts =3D (TaskState *)cpu->opaque; info->tid =3D sys_gettid(); @@ -5514,7 +5514,7 @@ static int do_fork(CPUArchState *env, unsigned int fl= ags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); int ret; TaskState *ts; CPUState *new_cpu; @@ -5547,7 +5547,7 @@ static int do_fork(CPUArchState *env, unsigned int fl= ags, abi_ulong newsp, new_env =3D cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_cpu =3D ENV_GET_CPU(new_env); + new_cpu =3D env_cpu(new_env); new_cpu->opaque =3D ts; ts->bprm =3D parent_ts->bprm; ts->info =3D parent_ts->info; @@ -6654,7 +6654,7 @@ int host_to_target_waitstatus(int status) =20 static int open_self_cmdline(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); struct linux_binprm *bprm =3D ((TaskState *)cpu->opaque)->bprm; int i; =20 @@ -6671,7 +6671,7 @@ static int open_self_cmdline(void *cpu_env, int fd) =20 static int open_self_maps(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; FILE *fp; char *line =3D NULL; @@ -6720,7 +6720,7 @@ static int open_self_maps(void *cpu_env, int fd) =20 static int open_self_stat(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; abi_ulong start_stack =3D ts->info->start_stack; int i; @@ -6757,7 +6757,7 @@ static int open_self_stat(void *cpu_env, int fd) =20 static int open_self_auxv(void *cpu_env, int fd) { - CPUState *cpu =3D ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu =3D env_cpu((CPUArchState *)cpu_env); TaskState *ts =3D cpu->opaque; abi_ulong auxv =3D ts->info->saved_auxv; abi_ulong len =3D ts->info->auxv_len; @@ -7042,7 +7042,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; #if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \ || defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \ @@ -11706,7 +11706,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu =3D ENV_GET_CPU(cpu_env); + CPUState *cpu =3D env_cpu(cpu_env); abi_long ret; =20 #ifdef DEBUG_ERESTARTSYS diff --git a/linux-user/uname.c b/linux-user/uname.c index 1c05f95387..a09ffe1ea7 100644 --- a/linux-user/uname.c +++ b/linux-user/uname.c @@ -54,7 +54,7 @@ const char *cpu_to_uname_machine(void *cpu_env) return "armv5te" utsname_suffix; #elif defined(TARGET_I386) && !defined(TARGET_X86_64) /* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */ - CPUState *cpu =3D ENV_GET_CPU((CPUX86State *)cpu_env); + CPUState *cpu =3D env_cpu((CPUX86State *)cpu_env); int family =3D object_property_get_int(OBJECT(cpu), "family", NULL); if (family =3D=3D 4) { return "i486"; diff --git a/target/arm/helper.c b/target/arm/helper.c index 719fb92e60..f23989febf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -587,7 +587,7 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_all_cpus_synced(cs); } @@ -595,7 +595,7 @@ static void tlbiall_is_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_all_cpus_synced(cs); } @@ -603,7 +603,7 @@ static void tlbiasid_is_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -611,7 +611,7 @@ static void tlbimva_is_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); } @@ -686,7 +686,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S12NSE1 | @@ -697,7 +697,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S12NSE1 | @@ -714,7 +714,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { @@ -729,7 +729,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { @@ -745,7 +745,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); } @@ -753,7 +753,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -761,7 +761,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); @@ -770,7 +770,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -1921,7 +1921,7 @@ static void csselr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); uint64_t ret =3D 0; =20 @@ -3773,7 +3773,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState= *env, static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); bool sec =3D arm_is_secure_below_el3(env); =20 if (sec) { @@ -3790,7 +3790,7 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *en= v, const ARMCPRegInfo *ri, static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); @@ -3861,7 +3861,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,= const ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); bool sec =3D arm_is_secure_below_el3(env); bool has_el2 =3D arm_feature(env, ARM_FEATURE_EL2); =20 @@ -3884,7 +3884,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); } @@ -3892,7 +3892,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); } @@ -3975,7 +3975,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -3985,7 +3985,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, @@ -4017,7 +4017,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, uint64_t value) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); uint64_t pageaddr; =20 if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS= )) { diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a55a5dfc02..952e97a7d7 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, } #else /* FIXME -- we can do better. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); #endif } =20 diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index 44b89c1d74..64fd51ad4a 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -67,7 +67,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D ENV_GET_CPU(env)->hax_vcpu; + struct hax_vcpu_state *vcpu =3D env_cpu(env)->hax_vcpu; if (!vcpu) { return HAX_INVALID_FD; } @@ -409,7 +409,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, =20 static int hax_vcpu_interrupt(CPUArchState *env) { - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; struct hax_tunnel *ht =3D vcpu->tunnel; =20 @@ -461,7 +461,7 @@ void hax_raise_event(CPUState *cpu) static int hax_vcpu_hax_exec(CPUArchState *env) { int ret =3D 0; - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; struct hax_tunnel *ht =3D vcpu->tunnel; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 9ef7d7513f..822fa1866e 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -75,8 +75,8 @@ static inline uint64_t decode_bytes(CPUX86State *env, str= uct x86_decode *decode, VM_PANIC_EX("%s invalid size %d\n", __func__, size); break; } - target_ulong va =3D linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->= len; - vmx_read_mem(ENV_GET_CPU(env), &val, va, size); + target_ulong va =3D linear_rip(env_cpu(env), RIP(env)) + decode->len; + vmx_read_mem(env_cpu(env), &val, va, size); decode->len +=3D size; =20 return val; @@ -1772,7 +1772,7 @@ void calc_modrm_operand32(CPUX86State *env, struct x8= 6_decode *decode, if (4 =3D=3D decode->modrm.rm) { ptr +=3D get_sib_val(env, decode, &seg); } else if (!decode->modrm.mod && 5 =3D=3D decode->modrm.rm) { - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { ptr +=3D RIP(env) + decode->len; } else { ptr =3D decode->displacement; @@ -1877,7 +1877,7 @@ static void decode_prefix(CPUX86State *env, struct x8= 6_decode *decode) decode->addr_size_override =3D byte; break; case PREFIX_REX ... (PREFIX_REX + 0xf): - if (x86_is_long_mode(ENV_GET_CPU(env))) { + if (x86_is_long_mode(env_cpu(env))) { decode->rex.rex =3D byte; break; } @@ -1892,16 +1892,16 @@ static void decode_prefix(CPUX86State *env, struct = x86_decode *decode) void set_addressing_size(CPUX86State *env, struct x86_decode *decode) { decode->addressing_size =3D -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->addr_size_override) { decode->addressing_size =3D 4; } else { decode->addressing_size =3D 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->addr_size_override) { @@ -1929,16 +1929,16 @@ void set_addressing_size(CPUX86State *env, struct x= 86_decode *decode) void set_operand_size(CPUX86State *env, struct x86_decode *decode) { decode->operand_size =3D -1; - if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) { + if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) { if (decode->op_size_override) { decode->operand_size =3D 4; } else { decode->operand_size =3D 2; } - } else if (!x86_is_long_mode(ENV_GET_CPU(env))) { + } else if (!x86_is_long_mode(env_cpu(env))) { /* protected */ struct vmx_segment cs; - vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS); + vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS); /* check db */ if ((cs.ar >> 14) & 1) { if (decode->op_size_override) { @@ -2188,5 +2188,5 @@ target_ulong decode_linear_addr(CPUX86State *env, str= uct x86_decode *decode, default: break; } - return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_siz= e, seg); + return linear_addr_size(env_cpu(env), addr, decode->addressing_size, s= eg); } diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3ea18edc68..1b04bd7e94 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -182,12 +182,12 @@ void write_val_ext(struct CPUX86State *env, target_ul= ong ptr, target_ulong val, write_val_to_reg(ptr, val, size); return; } - vmx_write_mem(ENV_GET_CPU(env), ptr, &val, size); + vmx_write_mem(env_cpu(env), ptr, &val, size); } =20 uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes) { - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, ptr, bytes); + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, ptr, bytes); return env->hvf_emul->mmio_buf; } =20 @@ -399,17 +399,18 @@ static void exec_out(struct CPUX86State *env, struct = x86_decode *decode) { switch (decode->opcode[0]) { case 0xe6: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 1, 1,= 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1); break; case 0xe7: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &RAX(env), 1, + hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1, decode->operand_size, 1); break; case 0xee: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 1, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1); break; case 0xef: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->ope= rand_size, 1); + hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1, + decode->operand_size, 1); break; default: VM_PANIC("Bad out opcode\n"); @@ -423,10 +424,11 @@ static void exec_in(struct CPUX86State *env, struct x= 86_decode *decode) target_ulong val =3D 0; switch (decode->opcode[0]) { case 0xe4: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 0, 1,= 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1); break; case 0xe5: - hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode= ->operand_size, 1); + hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0, + decode->operand_size, 1); if (decode->operand_size =3D=3D 2) { AX(env) =3D val; } else { @@ -434,10 +436,10 @@ static void exec_in(struct CPUX86State *env, struct x= 86_decode *decode) } break; case 0xec: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 0, 1, 1); + hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1); break; case 0xed: - hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_= size, 1); + hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size= , 1); if (decode->operand_size =3D=3D 2) { AX(env) =3D val; } else { @@ -484,12 +486,13 @@ static inline void string_rep(struct CPUX86State *env= , struct x86_decode *decode =20 static void exec_ins_single(struct CPUX86State *env, struct x86_decode *de= code) { - target_ulong addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), dec= ode->addressing_size, - R_ES); + target_ulong addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0, + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 0, decode->operand_size, 1); - vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode-= >operand_size); + vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf, + decode->operand_size); =20 string_increment_reg(env, R_EDI, decode); } @@ -509,8 +512,9 @@ static void exec_outs_single(struct CPUX86State *env, s= truct x86_decode *decode) { target_ulong addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); =20 - vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->= operand_size); - hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1, + vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr, + decode->operand_size); + hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 1, decode->operand_size, 1); =20 string_increment_reg(env, R_ESI, decode); @@ -534,8 +538,8 @@ static void exec_movs_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong val; =20 src_addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addr= essing_size, - R_ES); + dst_addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 val =3D read_val_ext(env, src_addr, decode->operand_size); write_val_ext(env, dst_addr, val, decode->operand_size); @@ -561,8 +565,8 @@ static void exec_cmps_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong dst_addr; =20 src_addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - dst_addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addr= essing_size, - R_ES); + dst_addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); =20 decode->op[0].type =3D X86_VAR_IMMEDIATE; decode->op[0].val =3D read_val_ext(env, src_addr, decode->operand_size= ); @@ -591,9 +595,10 @@ static void exec_stos_single(struct CPUX86State *env, = struct x86_decode *decode) target_ulong addr; target_ulong val; =20 - addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressi= ng_size, R_ES); + addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); val =3D read_reg(env, R_EAX, decode->operand_size); - vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size); + vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size); =20 string_increment_reg(env, R_EDI, decode); } @@ -614,9 +619,10 @@ static void exec_scas_single(struct CPUX86State *env, = struct x86_decode *decode) { target_ulong addr; =20 - addr =3D linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressi= ng_size, R_ES); + addr =3D linear_addr_size(env_cpu(env), RDI(env), + decode->addressing_size, R_ES); decode->op[1].type =3D X86_VAR_IMMEDIATE; - vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->opera= nd_size); + vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_s= ize); =20 EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false); string_increment_reg(env, R_EDI, decode); @@ -641,7 +647,7 @@ static void exec_lods_single(struct CPUX86State *env, s= truct x86_decode *decode) target_ulong val =3D 0; =20 addr =3D decode_linear_addr(env, decode, RSI(env), R_DS); - vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size); + vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size); write_reg(env, R_EAX, val, decode->operand_size); =20 string_increment_reg(env, R_ESI, decode); @@ -753,7 +759,7 @@ void simulate_rdmsr(struct CPUState *cpu) =20 static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(ENV_GET_CPU(env)); + simulate_rdmsr(env_cpu(env)); RIP(env) +=3D decode->len; } =20 @@ -851,7 +857,7 @@ void simulate_wrmsr(struct CPUState *cpu) =20 static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(ENV_GET_CPU(env)); + simulate_wrmsr(env_cpu(env)); RIP(env) +=3D decode->len; } =20 diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 1885df29d2..d50d4b0c40 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -89,7 +89,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) } CC_SRC =3D eflags; #else - cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); + cpu_loop_exit_atomic(env_cpu(env), GETPC()); #endif /* CONFIG_ATOMIC64 */ } =20 @@ -158,7 +158,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) } CC_SRC =3D eflags; } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } #endif diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index bde2d551ff..3d1aa23a02 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -781,7 +781,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, #endif { /* Tell the main loop we need to serialize this insn. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } else { /* We're executing in a serial context -- no need to be atomic. */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 47fa474efb..53ed6413b4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -102,7 +102,7 @@ unsigned int mmu_translate(CPUNios2State *env, =20 static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D nios2_env_get_cpu(env); int idx; MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); @@ -126,7 +126,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t = pid) =20 void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D nios2_env_get_cpu(env); =20 MMU_LOG(qemu_log("mmu_write %08X =3D %08X\n", rn, v)); diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 529ec6ac0e..a60730faac 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -46,7 +46,7 @@ void helper_check_interrupts(CPUNios2State *env) =20 void helper_raise_exception(CPUNios2State *env, uint32_t index) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); cs->exception_index =3D index; cpu_loop_exit(cs); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e605efa883..e3149e4d3f 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -522,7 +522,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env,= mmu_ctx_t *ctx, ret =3D ppc6xx_tlb_check(env, ctx, eaddr, rw, type); #if defined(DUMP_PAGE_TABLES) if (qemu_loglevel_mask(CPU_LOG_MMU)) { - CPUState *cs =3D ENV_GET_CPU(env); + CPUState *cs =3D env_cpu(env); hwaddr curaddr; uint32_t a0, a1, a2, a3; =20 diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index df147596ce..1e6d99287b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -96,7 +96,7 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *= mem_buf, int n) switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] =3D ldl_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 4; default: return 0; @@ -201,9 +201,9 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] =3D ldtul_p(mem_buf); if (tcg_enabled()) { - tlb_flush(ENV_GET_CPU(env)); + tlb_flush(env_cpu(env)); } - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -251,35 +251,35 @@ static int cpu_write_virt_reg(CPUS390XState *env, uin= t8_t *mem_buf, int n) switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_BEA_REGNUM: env->gbea =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PP_REGNUM: env->pp =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFT_REGNUM: env->pfault_token =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFS_REGNUM: env->pfault_select =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; case S390_VIRT_PFC_REGNUM: env->pfault_compare =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; default: return 0; @@ -303,7 +303,7 @@ static int cpu_read_gs_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { env->gscb[n] =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(ENV_GET_CPU(env)); + cpu_synchronize_post_init(env_cpu(env)); return 8; } =20 diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index ffd5f02fbe..4a0161602f 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1461,7 +1461,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, #endif if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || (HAVE_ATOMIC128 ? 0 : sc > max)) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + cpu_loop_exit_atomic(env_cpu(env), ra); } } =20 diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index bd5d782b50..932aa7a7c7 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -107,7 +107,7 @@ void helper_trapa(CPUSH4State *env, uint32_t tra) void helper_exclusive(CPUSH4State *env) { /* We do not want cpu_restore_state to run. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), 0); + cpu_loop_exit_atomic(env_cpu(env), 0); } =20 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value) diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt index 056aa56496..76e492a489 100644 --- a/docs/devel/tracing.txt +++ b/docs/devel/tracing.txt @@ -434,9 +434,9 @@ Can be used as: /* trace emitted at this point */ trace_foo(0xd1); /* trace emitted at this point */ - trace_bar(ENV_GET_CPU(env), 0xd2); + trace_bar(env_cpu(env), 0xd2); /* trace emitted at this point (env) and when guest code is execut= ed (cpu_env) */ - trace_baz_tcg(ENV_GET_CPU(env), cpu_env, 0xd3); + trace_baz_tcg(env_cpu(env), cpu_env, 0xd3); } =20 If the translating vCPU has address 0xc1 and code is later executed by vCPU diff --git a/scripts/tracetool/format/tcg_helper_c.py b/scripts/tracetool/f= ormat/tcg_helper_c.py index bbbd6ad0f4..79aa63eada 100644 --- a/scripts/tracetool/format/tcg_helper_c.py +++ b/scripts/tracetool/format/tcg_helper_c.py @@ -25,7 +25,7 @@ def vcpu_transform_args(args, mode): if mode =3D=3D "code": return Arguments([ # Does cast from helper requirements to tracing types - ("CPUState *", "ENV_GET_CPU(%s)" % args.names()[0]), + ("CPUState *", "env_cpu(%s)" % args.names()[0]), ]) else: args =3D Arguments([ --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681064; cv=none; d=zoho.com; s=zohoarc; b=VXg8bhzjTHactskT44R2do7ApwibIyEhdDp+S27ttEZg0EBTiBgJO9GHD1IUMfPHbFp6YgCN5fpA2SQfanfPfA2l/tpneGtGwudVNZ8VzEKkhi/NnKH+7yVwGHlpgMW4XI4Vuoj7LndTfG7akptUiVIQRUkGmH0Kc0qhlkGvAHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559681064; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=9aukZSJTtaEX+E6TYMtemh6Y/79Nrv8IxJ0VQThpXlk=; b=jLkJO3EsgIL4Vfs5IMrj6MwkBmxYMqq7j98UEsUV7fOZnjC1FwqsiCK0yrSKBEQ6qI4O09/VORGQtnpSfKHecY4ptVCGxhPTyxsKB+jgyoDXXAgWetiqfE+AG8+zmGOAKYyVncFOQQAEB9inZdq6OvDEdGMMuTvrMdOvQhrHiUU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155968106490318.308619853273512; Tue, 4 Jun 2019 13:44:24 -0700 (PDT) Received: from localhost ([127.0.0.1]:57716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGI9-00017i-PU for importer@patchew.org; Tue, 04 Jun 2019 16:44:21 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8G-0000yV-HS for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8F-00046T-KU for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:08 -0400 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:38818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8F-00045x-Fe for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:07 -0400 Received: by mail-ot1-x342.google.com with SMTP id d17so6677929oth.5 for ; Tue, 04 Jun 2019 13:34:07 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=9aukZSJTtaEX+E6TYMtemh6Y/79Nrv8IxJ0VQThpXlk=; b=JbPs+X2MMT/f49HY2N+lxgxvEwKiCxhfb+t7JeSZ2reShq8ly+M/bzNWvbtLTEQ4FK Qh0UMWaBFq0GWCv4dC/vkSHtZWe5/V1ofH/bwB8B1mOAgrRA8SpPvuAH7Pc3xAvrcS4N ZoNOZkVgPyqw8Clr2vd1lPXvh3enyGEL6OHOGmLiL6CWRLARPeQeetqt3wOYRiyK6w9Y 2FEN38qiyC3as9vPWIZbufQbIyp0WXpYUUe+7SK6qnk4bizC2lkC/fEnjpcX/XmqghuM g03kOgYSTH8SvP4X9Ih9drcgzn4jOrIMidinHKatN/9JLaMtJ8b629NFSlUp8BxasFGG C5kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=9aukZSJTtaEX+E6TYMtemh6Y/79Nrv8IxJ0VQThpXlk=; b=kAtPyDWwF0TsM/2WS3BsVFvAJBDdm9zjYFQnuFJleliLAz3gWuuyJsv58DzfadB5Ha 2yJL2b8nnMnX4lHQt8Dar+Fa09xtiZ/LO6fQItjxVI9Z1eoNEr/YCEWJmJMZSq8soTLZ mYNa1a1f+4D9BpmHJbClDd33beg0ESrcTcscQSj1EwdJIfMSI0yoMpoqV1wEvya4Qbxp xJOeYwbFlwnZvF8pqTNI6TbRiVY4Bgt6fgFQEi+SzZZfYn0vkuZjKNU5fHrFfPG1RfWQ 2IasN20BUWiHEZ9kKqK8Ce8u33XuMdY5Vb8z2tvQX+9WlnJaiBtONJm5yuY0ApQU5idt ZraQ== X-Gm-Message-State: APjAAAXBwCGDAJcyf6ImjTbi+fx1A3sprJhPQGRXtbYkhJ6apiDPpE/K Xu+/oG4WFTFFROpZeyv1GmiT1qyW65VUww== X-Google-Smtp-Source: APXvYqzxFcZ5+HzMLMCjRs2nOz2anTjtWqnUFybw2rMwxfrcqqCpM/R1RolTCbCvcLIxB+nPHbxUbQ== X-Received: by 2002:a9d:32c2:: with SMTP id u60mr6298514otb.70.1559680446550; Tue, 04 Jun 2019 13:34:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:19 -0500 Message-Id: <20190604203351.27778-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 07/39] cpu: Introduce env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will replace foo_env_get_cpu with a generic definition. No changes to the target specific code so far. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 454f6d663f..c62f07b354 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return container_of(env, ArchCPU, env); +} + /** * env_cpu(env) * @env: The architecture environment @@ -379,8 +390,7 @@ int cpu_exec(CPUState *cpu); */ static inline CPUState *env_cpu(CPUArchState *env) { - ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); - return &arch_cpu->parent_obj; + return &env_archcpu(env)->parent_obj; } =20 #endif /* CPU_ALL_H */ --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680639; cv=none; d=zoho.com; s=zohoarc; b=HWRziwvHD/VrqvSYjsRHm5+rcGsosT99/MybpvydGOXLqGY5wmf+G4pgSSvxWW+BJrNCkPDnapjG9bHP4OSW63uXbTwhqy2LDzBMeN/DhGU0KnjP/Ltkx3VBM0fM1VVdNUSGon4gnwHsDCKyzeTWCsSOsuDXR+7hlfBB8S+spAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559680639; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=98JOxuqlJVZoGMNI/F+3Atqcd/SU0QC/Vy6EmOYsiac=; b=dC8rNIn6Rj947e49FKM3OPiFvQ4fI4bD8qYO4Atf4HdmkxoiW/WnK+jTDBeS4QSKxkg+2SBReHAo8RlYlxyyQJoY2HyCWVXZflxQ+CIMhfhwNOHqxIgAEKlLvRVrsFfzOX9GR8FDxksShCMiUZ2QopFDAVBkzf/P+YeXu4JaiPY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559680639867798.9440508156316; Tue, 4 Jun 2019 13:37:19 -0700 (PDT) Received: from localhost ([127.0.0.1]:57620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGBF-0003Ch-RA for importer@patchew.org; Tue, 04 Jun 2019 16:37:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8I-00010K-Lb for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8H-00047e-IG for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:10 -0400 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:42143) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8H-00047B-Cr for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:09 -0400 Received: by mail-oi1-x242.google.com with SMTP id s184so5590511oie.9 for ; Tue, 04 Jun 2019 13:34:09 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=98JOxuqlJVZoGMNI/F+3Atqcd/SU0QC/Vy6EmOYsiac=; b=VnTpZ6bdb7MM+iod+J2HKdFaLyn1EOd/hOxQkdXbAOmsNm19WZ9OLXuMA48QV0w+zH DajQbhYH406NkMw1RUtH17EGfWt0u8qfxdPbbb+gROqv4lJwYvvja7PnOHSGRelV7ZdJ 7gvqgJ25EdoEii2zpD9h3eX7jxpvQiyXK1SmldCKuRH0FtxyEdEZQ0QFpGQS+fPQzxNO 0aOJoeWEV0RkKCxSY9dhqrts7srlwUkXNGvHxELMehj3hFGcFvHbr6IlnUzwXlHOVysA crhyem6BgwrVrwa5xQFLJ65lx9YChdSeJthnEDxbeVb2oj0BP8Xfhy+ntmc+ZOF+bRQl my1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=98JOxuqlJVZoGMNI/F+3Atqcd/SU0QC/Vy6EmOYsiac=; b=odsnGFS345WeHMVKz7oWN00hm8bJbYgvzl3wfyIgrcbXPPQWo9pZYYvrOksMVv7u/f qsK8OMD0ovaBhTalgP+zAetRfV9PilsNYJBoIBf3SO2ycYyyryqH1XU5WVjCLNSEffPB 7GMQgbevM77IVW5nxKGbYXO7HKIJ0K12j0vjG4lcS7nQw1uTPlczyiyHzgX40NIhme/X ud1aaf99Lxi6XV7r4vNIrJ75MENuigZEZakLey1Udr6SVdR1vpox7CcfvpHTzNwBzPfx gdDhYYsQ+edkUpike/EYd91PI+nUos/sKHkxzdzjKvWDKgWDN5gdMHn9ekjEt5xSHL2g 7c+A== X-Gm-Message-State: APjAAAWoAixE6jWgZqcJuhLQbQp2o3cBzrrGN8rq7Gyo/HKLjE8ellVY z3RiyMJ3bEwDBP/necbiQaiJGF3U26ltjw== X-Google-Smtp-Source: APXvYqyoTDg28I6UJbS+TaOxwsQqphAXju5hEafGZer80OPP0BppIr8fqQJJOiIRSd9ySlKLlfJubA== X-Received: by 2002:aca:4708:: with SMTP id u8mr5680448oia.166.1559680448152; Tue, 04 Jun 2019 13:34:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:20 -0500 Message-Id: <20190604203351.27778-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v4 08/39] target/alpha: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace alpha_env_get_cpu with env_archcpu. The combination CPU(alpha_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 ----- linux-user/alpha/cpu_loop.c | 2 +- target/alpha/helper.c | 8 +++----- target/alpha/sys_helper.c | 8 ++++---- 4 files changed, 8 insertions(+), 15 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e391195be0..86d3e953b9 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -278,11 +278,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; =20 -static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) -{ - return container_of(env, AlphaCPU, env); -} - #define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 61992571e1..7a94eee84c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUAlphaState *env) { - CPUState *cs =3D CPU(alpha_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; target_siginfo_t info; abi_long sysret; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2134ee1e9d..93b8e788b1 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -136,7 +136,7 @@ static int get_physical_address(CPUAlphaState *env, tar= get_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { - CPUState *cs =3D CPU(alpha_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_long saddr =3D addr; target_ulong phys =3D 0; target_ulong L1pte, L2pte, L3pte; @@ -486,8 +486,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; env->error_code =3D error; @@ -498,8 +497,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int = excp, int error) void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; env->error_code =3D error; diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index ac22323191..f9c34b1144 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -44,17 +44,17 @@ uint64_t helper_load_pcc(CPUAlphaState *env) #ifndef CONFIG_USER_ONLY void helper_tbia(CPUAlphaState *env) { - tlb_flush(CPU(alpha_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } =20 void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); + tlb_flush_page(env_cpu(env), p); } =20 void helper_tb_flush(CPUAlphaState *env) { - tb_flush(CPU(alpha_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 void helper_halt(uint64_t restart) @@ -78,7 +78,7 @@ uint64_t helper_get_walltime(void) =20 void helper_set_alarm(CPUAlphaState *env, uint64_t expire) { - AlphaCPU *cpu =3D alpha_env_get_cpu(env); + AlphaCPU *cpu =3D env_archcpu(env); =20 if (expire) { env->alarm_expire =3D expire; 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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 09/39] target/arm: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace arm_env_get_cpu with env_archcpu. The combination CPU(arm_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 -- linux-user/aarch64/cpu_loop.c | 6 +- linux-user/aarch64/signal.c | 4 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/syscall.c | 8 +-- target/arm/arm-semi.c | 4 +- target/arm/cpu64.c | 2 +- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 120 +++++++++++++++++----------------- target/arm/op_helper.c | 21 +++--- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/arm/vfp_helper.c | 2 +- 13 files changed, 88 insertions(+), 94 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1afd1da491..c7df3816b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -913,11 +913,6 @@ struct ARMCPU { uint32_t sve_max_vq; }; =20 -static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) -{ - return container_of(env, ARMCPU, env); -} - void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2f2f63e3e8..18db6f80f0 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -73,7 +73,7 @@ /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; @@ -150,8 +150,8 @@ void cpu_loop(CPUARMState *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..cd521ee42d 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b7e7a6323c..ece4cf335e 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env) =20 void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; unsigned int n, insn; target_siginfo_t info; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d1a2c7831f..ac3b5dc393 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9781,10 +9781,10 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, * even though the current architectural maximum is VQ=3D16. */ ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env)) + if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t vq, old_vq; =20 old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; @@ -9801,7 +9801,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_SVE_GET_VL: ret =3D -TARGET_EINVAL; { - ARMCPU *cpu =3D arm_env_get_cpu(cpu_env); + ARMCPU *cpu =3D env_archcpu(cpu_env); if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; } @@ -9810,7 +9810,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_PAC_RESET_KEYS: { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 53e807ab72..07af8d35da 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -257,8 +257,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_sy= scall_complete_cb cb, */ target_ulong do_arm_semihosting(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0ec8cd41f1..b8bd1e88a5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -43,7 +43,7 @@ static inline void unset_feature(CPUARMState *env, int fe= ature) #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Number of cores is in [25:24]; otherwise we RAZ */ return (cpu->core_count - 1) << 24; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 796ef34b55..44e45a8037 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) } =20 qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 if (!return_to_aa64) { @@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 return; diff --git a/target/arm/helper.c b/target/arm/helper.c index f23989febf..188fb1950e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -227,7 +227,7 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); const ARMCPRegInfo *ri; uint32_t key; =20 @@ -548,7 +548,7 @@ static CPAccessResult access_tpm(CPUARMState *env, cons= t ARMCPRegInfo *ri, =20 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 raw_write(env, ri, value); tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ @@ -556,7 +556,7 @@ static void dacr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) =20 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { /* Unlike real hardware the qemu TLB uses virtual addresses, @@ -570,7 +570,7 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { @@ -631,7 +631,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiall_is_write(env, NULL, value); @@ -645,7 +645,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimva_is_write(env, NULL, value); @@ -659,7 +659,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiasid_is_write(env, NULL, value); @@ -673,7 +673,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimvaa_is_write(env, NULL, value); @@ -1353,7 +1353,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) =20 static void pmu_update_irq(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } @@ -1408,7 +1408,7 @@ static void pmccntr_op_finish(CPUARMState *env) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1457,7 +1457,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint= 8_t counter) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1865,7 +1865,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arm_el_is_aa64(env, 3)) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1902,7 +1902,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) =20 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank @@ -2452,7 +2452,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 timer_del(cpu->gt_timer[timeridx]); } @@ -2473,7 +2473,7 @@ static void gt_cval_write(CPUARMState *env, const ARM= CPRegInfo *ri, { trace_arm_gt_cval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D value; - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2494,14 +2494,14 @@ static void gt_tval_write(CPUARMState *env, const A= RMCPRegInfo *ri, trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + sextract64(value, 0, 32); - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; =20 trace_arm_gt_ctl_write(timeridx, value); @@ -2579,7 +2579,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 trace_arm_gt_cntvoff_write(value); raw_write(env, ri, value); @@ -3212,7 +3212,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A= RMCPRegInfo *ri) static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); =20 if (!u32p) { @@ -3227,7 +3227,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t nrgs =3D cpu->pmsav7_dregion; =20 if (value >=3D nrgs) { @@ -3355,7 +3355,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3384,7 +3384,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ @@ -3398,7 +3398,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); } raw_write(env, ri, value); @@ -3407,7 +3407,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ @@ -3497,7 +3497,7 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, uint64_t value) { /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); } =20 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3650,7 +3650,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); =20 @@ -3662,7 +3662,7 @@ static uint64_t midr_read(CPUARMState *env, const ARM= CPRegInfo *ri) =20 static uint64_t mpidr_read_val(CPUARMState *env) { - ARMCPU *cpu =3D ARM_CPU(arm_env_get_cpu(env)); + ARMCPU *cpu =3D env_archcpu(env); uint64_t mpidr =3D cpu->mp_affinity; =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { @@ -3815,7 +3815,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 if (arm_is_secure_below_el3(env)) { @@ -3839,7 +3839,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); @@ -3848,7 +3848,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); @@ -3904,7 +3904,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3918,7 +3918,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3928,7 +3928,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); bool sec =3D arm_is_secure_below_el3(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); @@ -3952,7 +3952,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -4001,7 +4001,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr; =20 @@ -4044,7 +4044,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *en= v, const ARMCPRegInfo *ri, =20 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int dzp_bit =3D 1 << 4; =20 /* DZP indicates whether DC ZVA access is allowed */ @@ -4079,7 +4079,7 @@ static void spsel_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t val) static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) =3D=3D value) { /* Skip the TLB flush if nothing actually changed; Linux likes @@ -4571,7 +4571,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D HCR_MASK; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -5238,7 +5238,7 @@ int sve_exception_el(CPUARMState *env, int el) */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; =20 if (el <=3D 1) { @@ -5406,7 +5406,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu) static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the @@ -5422,7 +5422,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5524,7 +5524,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu) static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5534,7 +5534,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only @@ -5630,7 +5630,7 @@ static void define_debug_regs(ARMCPU *cpu) */ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr1 =3D cpu->id_pfr1; =20 if (env->gicv3state) { @@ -5641,7 +5641,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) =20 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; =20 if (env->gicv3state) { @@ -7421,14 +7421,14 @@ uint32_t HELPER(rbit)(uint32_t x) /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; @@ -7488,7 +7488,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) =20 static void switch_mode(CPUARMState *env, int mode) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (mode !=3D ARM_CPU_MODE_USR) { cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); @@ -7831,7 +7831,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) * PreserveFPState() pseudocode. * We may throw an exception if the stacking fails. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; bool negpri =3D !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); bool is_priv =3D !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); @@ -10938,7 +10938,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -11059,7 +11059,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -11444,7 +11444,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type =3D ARMFault_Translation; @@ -11802,7 +11802,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 @@ -12006,7 +12006,7 @@ static void v8m_security_lookup(CPUARMState *env, u= int32_t address, * pseudocode SecurityCheck() function. * We assume the caller has zero-initialized *sattrs. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int r; bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; int idau_region =3D IREGION_NOTVALID; @@ -12119,7 +12119,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uin= t32_t address, * We set is_subpage to true if the region hit doesn't cover the * entire TARGET_PAGE the address is within. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; @@ -12899,7 +12899,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; =20 if (val < limit) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, GETPC(), true); raise_exception(env, EXCP_STKOF, 0, 1); @@ -13180,7 +13180,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) * alignment faults or any memory attribute handling). */ =20 - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t blocklen =3D 4 << cpu->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); =20 @@ -13680,7 +13680,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, uint32_t flags =3D 0; =20 if (is_a64(env)) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t sctlr; =20 *pc =3D env->pc; @@ -13853,7 +13853,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D arm_env_get_cpu(env)->sve_max_vq); + assert(vq <=3D env_archcpu(env)->sve_max_vq); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { @@ -13879,7 +13879,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int old_len, new_len; bool old_a64, new_a64; =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8ee15a4bd4..4db254876d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -31,7 +31,7 @@ static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (target_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -224,7 +224,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t = newvalue) * raising an exception if the limit is breached. */ if (newvalue < v7m_sp_limit(env)) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* * Stack limit exceptions are a rare case, so rather than syncing @@ -427,7 +427,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) =20 void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int target_el =3D check_wfx_trap(env, false); =20 if (cpu_has_work(cs)) { @@ -462,8 +462,7 @@ void HELPER(wfe)(CPUARMState *env) =20 void HELPER(yield)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the @@ -481,7 +480,7 @@ void HELPER(yield)(CPUARMState *env) */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 assert(excp_is_internal(excp)); cs->exception_index =3D excp; @@ -524,7 +523,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val,= uint32_t mask) void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); @@ -537,7 +536,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t= val) env->regs[15] &=3D (env->thumb ? ~1 : ~3); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); } =20 @@ -842,7 +841,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *r= ip) =20 void HELPER(pre_hvc)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); /* FIXME: Use actual secure state. */ bool secure =3D false; @@ -882,7 +881,7 @@ void HELPER(pre_hvc)(CPUARMState *env) =20 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); bool smd_flag =3D env->cp15.scr_el3 & SCR_SMD; @@ -1156,7 +1155,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (check_breakpoints(cpu)) { HELPER(exception_internal(env, EXCP_DEBUG)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f5440e57dd..8a3bf204d3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14289,7 +14289,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; - ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + ARMCPU *arm_cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; int bound, core_mmu_idx; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index d240c1b714..d25e19ef11 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13408,7 +13408,7 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; uint32_t condexec, core_mmu_idx; =20 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 7a46d99148..d3e83b627b 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { val &=3D ~FPCR_FZ16; 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X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 10/39] target/cris: Reindent mmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix all of the coding style errors in this file at once. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/cris/mmu.c | 479 +++++++++++++++++++++++----------------------- 1 file changed, 237 insertions(+), 242 deletions(-) diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b8db908823..9cb73bbfec 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -33,96 +33,99 @@ =20 void cris_mmu_init(CPUCRISState *env) { - env->mmu_rand_lfsr =3D 0xcccc; + env->mmu_rand_lfsr =3D 0xcccc; } =20 #define SR_POLYNOM 0x8805 static inline unsigned int compute_polynom(unsigned int sr) { - unsigned int i; - unsigned int f; + unsigned int i; + unsigned int f; =20 - f =3D 0; - for (i =3D 0; i < 16; i++) - f +=3D ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); + f =3D 0; + for (i =3D 0; i < 16; i++) { + f +=3D ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); + } =20 - return f; + return f; } =20 static void cris_mmu_update_rand_lfsr(CPUCRISState *env) { - unsigned int f; + unsigned int f; =20 - /* Update lfsr at every fault. */ - f =3D compute_polynom(env->mmu_rand_lfsr); - env->mmu_rand_lfsr >>=3D 1; - env->mmu_rand_lfsr |=3D (f << 15); - env->mmu_rand_lfsr &=3D 0xffff; + /* Update lfsr at every fault. */ + f =3D compute_polynom(env->mmu_rand_lfsr); + env->mmu_rand_lfsr >>=3D 1; + env->mmu_rand_lfsr |=3D (f << 15); + env->mmu_rand_lfsr &=3D 0xffff; } =20 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) { - return (rw_gc_cfg & 12) !=3D 0; + return (rw_gc_cfg & 12) !=3D 0; } =20 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) { - return (1 << seg) & rw_mm_cfg; + return (1 << seg) & rw_mm_cfg; } =20 static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg) { - uint32_t base; - int i; + uint32_t base; + int i; =20 - if (seg < 8) - base =3D env->sregs[SFR_RW_MM_KBASE_LO]; - else - base =3D env->sregs[SFR_RW_MM_KBASE_HI]; + if (seg < 8) { + base =3D env->sregs[SFR_RW_MM_KBASE_LO]; + } else { + base =3D env->sregs[SFR_RW_MM_KBASE_HI]; + } =20 - i =3D seg & 7; - base >>=3D i * 4; - base &=3D 15; + i =3D seg & 7; + base >>=3D i * 4; + base &=3D 15; =20 - base <<=3D 28; - return base; + base <<=3D 28; + return base; } -/* Used by the tlb decoder. */ -#define EXTRACT_FIELD(src, start, end) \ - (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 -static inline void set_field(uint32_t *dst, unsigned int val,=20 +/* Used by the tlb decoder. */ +#define EXTRACT_FIELD(src, start, end) \ + (((src) >> start) & ((1 << (end - start + 1)) - 1)) + +static inline void set_field(uint32_t *dst, unsigned int val, unsigned int offset, unsigned int width) { - uint32_t mask; + uint32_t mask; =20 - mask =3D (1 << width) - 1; - mask <<=3D offset; - val <<=3D offset; + mask =3D (1 << width) - 1; + mask <<=3D offset; + val <<=3D offset; =20 - val &=3D mask; - *dst &=3D ~(mask); - *dst |=3D val; + val &=3D mask; + *dst &=3D ~(mask); + *dst |=3D val; } =20 #ifdef DEBUG static void dump_tlb(CPUCRISState *env, int mmu) { - int set; - int idx; - uint32_t hi, lo, tlb_vpn, tlb_pfn; + int set; + int idx; + uint32_t hi, lo, tlb_vpn, tlb_pfn; =20 - for (set =3D 0; set < 4; set++) { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + for (set =3D 0; set < 4; set++) { + for (idx =3D 0; idx < 16; idx++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; + tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); + tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); =20 - printf ("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n",=20 - set, idx, hi, lo, tlb_vpn, tlb_pfn); - } - } + printf("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n", + set, idx, hi, lo, tlb_vpn, tlb_pfn); + } + } } #endif =20 @@ -131,232 +134,224 @@ static int cris_mmu_translate_page(struct cris_mmu_= result *res, CPUCRISState *env, uint32_t vaddr, int rw, int usermode, int debug) { - unsigned int vpage; - unsigned int idx; - uint32_t pid, lo, hi; - uint32_t tlb_vpn, tlb_pfn =3D 0; - int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x; - int cfg_v, cfg_k, cfg_w, cfg_x;=09 - int set, match =3D 0; - uint32_t r_cause; - uint32_t r_cfg; - int rwcause; - int mmu =3D 1; /* Data mmu is default. */ - int vect_base; + unsigned int vpage; + unsigned int idx; + uint32_t pid, lo, hi; + uint32_t tlb_vpn, tlb_pfn =3D 0; + int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x; + int cfg_v, cfg_k, cfg_w, cfg_x; + int set, match =3D 0; + uint32_t r_cause; + uint32_t r_cfg; + int rwcause; + int mmu =3D 1; /* Data mmu is default. */ + int vect_base; =20 - r_cause =3D env->sregs[SFR_R_MM_CAUSE]; - r_cfg =3D env->sregs[SFR_RW_MM_CFG]; - pid =3D env->pregs[PR_PID] & 0xff; + r_cause =3D env->sregs[SFR_R_MM_CAUSE]; + r_cfg =3D env->sregs[SFR_RW_MM_CFG]; + pid =3D env->pregs[PR_PID] & 0xff; =20 - switch (rw) { - case 2: rwcause =3D CRIS_MMU_ERR_EXEC; mmu =3D 0; break; - case 1: rwcause =3D CRIS_MMU_ERR_WRITE; break; - default: - case 0: rwcause =3D CRIS_MMU_ERR_READ; break; - } + switch (rw) { + case 2: + rwcause =3D CRIS_MMU_ERR_EXEC; + mmu =3D 0; + break; + case 1: + rwcause =3D CRIS_MMU_ERR_WRITE; + break; + default: + case 0: + rwcause =3D CRIS_MMU_ERR_READ; + break; + } =20 - /* I exception vectors 4 - 7, D 8 - 11. */ - vect_base =3D (mmu + 1) * 4; + /* I exception vectors 4 - 7, D 8 - 11. */ + vect_base =3D (mmu + 1) * 4; =20 - vpage =3D vaddr >> 13; + vpage =3D vaddr >> 13; =20 - /* We know the index which to check on each set. - Scan both I and D. */ -#if 0 - for (set =3D 0; set < 4; set++) { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + /* + * We know the index which to check on each set. + * Scan both I and D. + */ + idx =3D vpage & 15; + for (set =3D 0; set < 4; set++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; =20 - printf ("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n",=20 - set, idx, hi, lo, tlb_vpn, tlb_pfn); - } - } -#endif + tlb_vpn =3D hi >> 13; + tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); + tlb_g =3D EXTRACT_FIELD(lo, 4, 4); =20 - idx =3D vpage & 15; - for (set =3D 0; set < 4; set++) - { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; + D_LOG("TLB[%d][%d][%d] v=3D%x vpage=3D%x lo=3D%x hi=3D%x\n", + mmu, set, idx, tlb_vpn, vpage, lo, hi); + if ((tlb_g || (tlb_pid =3D=3D pid)) && tlb_vpn =3D=3D vpage) { + match =3D 1; + break; + } + } =20 - tlb_vpn =3D hi >> 13; - tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); - tlb_g =3D EXTRACT_FIELD(lo, 4, 4); + res->bf_vec =3D vect_base; + if (match) { + cfg_w =3D EXTRACT_FIELD(r_cfg, 19, 19); + cfg_k =3D EXTRACT_FIELD(r_cfg, 18, 18); + cfg_x =3D EXTRACT_FIELD(r_cfg, 17, 17); + cfg_v =3D EXTRACT_FIELD(r_cfg, 16, 16); =20 - D_LOG("TLB[%d][%d][%d] v=3D%x vpage=3D%x lo=3D%x hi=3D%x\n",=20 - mmu, set, idx, tlb_vpn, vpage, lo, hi); - if ((tlb_g || (tlb_pid =3D=3D pid)) - && tlb_vpn =3D=3D vpage) { - match =3D 1; - break; - } - } + tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + tlb_k =3D EXTRACT_FIELD(lo, 2, 2); + tlb_w =3D EXTRACT_FIELD(lo, 1, 1); + tlb_x =3D EXTRACT_FIELD(lo, 0, 0); =20 - res->bf_vec =3D vect_base; - if (match) { - cfg_w =3D EXTRACT_FIELD(r_cfg, 19, 19); - cfg_k =3D EXTRACT_FIELD(r_cfg, 18, 18); - cfg_x =3D EXTRACT_FIELD(r_cfg, 17, 17); - cfg_v =3D EXTRACT_FIELD(r_cfg, 16, 16); + /* + * set_exception_vector(0x04, i_mmu_refill); + * set_exception_vector(0x05, i_mmu_invalid); + * set_exception_vector(0x06, i_mmu_access); + * set_exception_vector(0x07, i_mmu_execute); + * set_exception_vector(0x08, d_mmu_refill); + * set_exception_vector(0x09, d_mmu_invalid); + * set_exception_vector(0x0a, d_mmu_access); + * set_exception_vector(0x0b, d_mmu_write); + */ + if (cfg_k && tlb_k && usermode) { + D(printf("tlb: kernel protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + res->bf_vec =3D vect_base + 2; + } else if (rw =3D=3D 1 && cfg_w && !tlb_w) { + D(printf("tlb: write protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + /* write accesses never go through the I mmu. */ + res->bf_vec =3D vect_base + 3; + } else if (rw =3D=3D 2 && cfg_x && !tlb_x) { + D(printf("tlb: exec protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + res->bf_vec =3D vect_base + 3; + } else if (cfg_v && !tlb_v) { + D(printf("tlb: invalid %x\n", vaddr)); + match =3D 0; + res->bf_vec =3D vect_base + 1; + } =20 - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); - tlb_v =3D EXTRACT_FIELD(lo, 3, 3); - tlb_k =3D EXTRACT_FIELD(lo, 2, 2); - tlb_w =3D EXTRACT_FIELD(lo, 1, 1); - tlb_x =3D EXTRACT_FIELD(lo, 0, 0); + res->prot =3D 0; + if (match) { + res->prot |=3D PAGE_READ; + if (tlb_w) { + res->prot |=3D PAGE_WRITE; + } + if (mmu =3D=3D 0 && (cfg_x || tlb_x)) { + res->prot |=3D PAGE_EXEC; + } + } else { + D(dump_tlb(env, mmu)); + } + } else { + /* If refill, provide a randomized set. */ + set =3D env->mmu_rand_lfsr & 3; + } =20 - /* - set_exception_vector(0x04, i_mmu_refill); - set_exception_vector(0x05, i_mmu_invalid); - set_exception_vector(0x06, i_mmu_access); - set_exception_vector(0x07, i_mmu_execute); - set_exception_vector(0x08, d_mmu_refill); - set_exception_vector(0x09, d_mmu_invalid); - set_exception_vector(0x0a, d_mmu_access); - set_exception_vector(0x0b, d_mmu_write); - */ - if (cfg_k && tlb_k && usermode) { - D(printf ("tlb: kernel protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - res->bf_vec =3D vect_base + 2; - } else if (rw =3D=3D 1 && cfg_w && !tlb_w) { - D(printf ("tlb: write protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - /* write accesses never go through the I mmu. */ - res->bf_vec =3D vect_base + 3; - } else if (rw =3D=3D 2 && cfg_x && !tlb_x) { - D(printf ("tlb: exec protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - res->bf_vec =3D vect_base + 3; - } else if (cfg_v && !tlb_v) { - D(printf ("tlb: invalid %x\n", vaddr)); - match =3D 0; - res->bf_vec =3D vect_base + 1; - } + if (!match && !debug) { + cris_mmu_update_rand_lfsr(env); =20 - res->prot =3D 0; - if (match) { - res->prot |=3D PAGE_READ; - if (tlb_w) - res->prot |=3D PAGE_WRITE; - if (mmu =3D=3D 0 && (cfg_x || tlb_x)) - res->prot |=3D PAGE_EXEC; - } - else - D(dump_tlb(env, mmu)); - } else { - /* If refill, provide a randomized set. */ - set =3D env->mmu_rand_lfsr & 3; - } + /* Compute index. */ + idx =3D vpage & 15; =20 - if (!match && !debug) { - cris_mmu_update_rand_lfsr(env); + /* Update RW_MM_TLB_SEL. */ + env->sregs[SFR_RW_MM_TLB_SEL] =3D 0; + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); =20 - /* Compute index. */ - idx =3D vpage & 15; + /* Update RW_MM_CAUSE. */ + set_field(&r_cause, rwcause, 8, 2); + set_field(&r_cause, vpage, 13, 19); + set_field(&r_cause, pid, 0, 8); + env->sregs[SFR_R_MM_CAUSE] =3D r_cause; + D(printf("refill vaddr=3D%x pc=3D%x\n", vaddr, env->pc)); + } =20 - /* Update RW_MM_TLB_SEL. */ - env->sregs[SFR_RW_MM_TLB_SEL] =3D 0; - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); + D(printf("%s rw=3D%d mtch=3D%d pc=3D%x va=3D%x vpn=3D%x tlbvpn=3D%x pf= n=3D%x pid=3D%x" + " %x cause=3D%x sel=3D%x sp=3D%x %x %x\n", + __func__, rw, match, env->pc, + vaddr, vpage, + tlb_vpn, tlb_pfn, tlb_pid, + pid, + r_cause, + env->sregs[SFR_RW_MM_TLB_SEL], + env->regs[R_SP], env->pregs[PR_USP], env->ksp)); =20 - /* Update RW_MM_CAUSE. */ - set_field(&r_cause, rwcause, 8, 2); - set_field(&r_cause, vpage, 13, 19); - set_field(&r_cause, pid, 0, 8); - env->sregs[SFR_R_MM_CAUSE] =3D r_cause; - D(printf("refill vaddr=3D%x pc=3D%x\n", vaddr, env->pc)); - } - - D(printf ("%s rw=3D%d mtch=3D%d pc=3D%x va=3D%x vpn=3D%x tlbvpn=3D%x pfn= =3D%x pid=3D%x" - " %x cause=3D%x sel=3D%x sp=3D%x %x %x\n", - __func__, rw, match, env->pc, - vaddr, vpage, - tlb_vpn, tlb_pfn, tlb_pid,=20 - pid, - r_cause, - env->sregs[SFR_RW_MM_TLB_SEL], - env->regs[R_SP], env->pregs[PR_USP], env->ksp)); - - res->phy =3D tlb_pfn << TARGET_PAGE_BITS; - return !match; + res->phy =3D tlb_pfn << TARGET_PAGE_BITS; + return !match; } =20 void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { CRISCPU *cpu =3D cris_env_get_cpu(env); - target_ulong vaddr; - unsigned int idx; - uint32_t lo, hi; - uint32_t tlb_vpn; - int tlb_pid, tlb_g, tlb_v; - unsigned int set; - unsigned int mmu; + target_ulong vaddr; + unsigned int idx; + uint32_t lo, hi; + uint32_t tlb_vpn; + int tlb_pid, tlb_g, tlb_v; + unsigned int set; + unsigned int mmu; =20 - pid &=3D 0xff; - for (mmu =3D 0; mmu < 2; mmu++) { - for (set =3D 0; set < 4; set++) - { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - =09 - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); - tlb_g =3D EXTRACT_FIELD(lo, 4, 4); - tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + pid &=3D 0xff; + for (mmu =3D 0; mmu < 2; mmu++) { + for (set =3D 0; set < 4; set++) { + for (idx =3D 0; idx < 16; idx++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; =20 - if (tlb_v && !tlb_g && (tlb_pid =3D=3D pid)) { - vaddr =3D tlb_vpn << TARGET_PAGE_BITS; - D_LOG("flush pid=3D%x vaddr=3D%x\n",=20 - pid, vaddr); + tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); + tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); + tlb_g =3D EXTRACT_FIELD(lo, 4, 4); + tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + + if (tlb_v && !tlb_g && (tlb_pid =3D=3D pid)) { + vaddr =3D tlb_vpn << TARGET_PAGE_BITS; + D_LOG("flush pid=3D%x vaddr=3D%x\n", pid, vaddr); tlb_flush_page(CPU(cpu), vaddr); - } - } - } - } + } + } + } + } } =20 int cris_mmu_translate(struct cris_mmu_result *res, CPUCRISState *env, uint32_t vaddr, int rw, int mmu_idx, int debug) { - int seg; - int miss =3D 0; - int is_user =3D mmu_idx =3D=3D MMU_USER_IDX; - uint32_t old_srs; + int seg; + int miss =3D 0; + int is_user =3D mmu_idx =3D=3D MMU_USER_IDX; + uint32_t old_srs; =20 - old_srs=3D env->pregs[PR_SRS]; + old_srs =3D env->pregs[PR_SRS]; =20 - /* rw =3D=3D 2 means exec, map the access to the insn mmu. */ - env->pregs[PR_SRS] =3D rw =3D=3D 2 ? 1 : 2; + /* rw =3D=3D 2 means exec, map the access to the insn mmu. */ + env->pregs[PR_SRS] =3D rw =3D=3D 2 ? 1 : 2; =20 - if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { - res->phy =3D vaddr; - res->prot =3D PAGE_BITS; - goto done; - } + if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { + res->phy =3D vaddr; + res->prot =3D PAGE_BITS; + goto done; + } =20 - seg =3D vaddr >> 28; - if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) - { - uint32_t base; + seg =3D vaddr >> 28; + if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]= )) { + uint32_t base; =20 - miss =3D 0; - base =3D cris_mmu_translate_seg(env, seg); - res->phy =3D base | (0x0fffffff & vaddr); - res->prot =3D PAGE_BITS; - } else { - miss =3D cris_mmu_translate_page(res, env, vaddr, rw, - is_user, debug); - } - done: - env->pregs[PR_SRS] =3D old_srs; - return miss; + miss =3D 0; + base =3D cris_mmu_translate_seg(env, seg); + res->phy =3D base | (0x0fffffff & vaddr); + res->prot =3D PAGE_BITS; + } else { + miss =3D cris_mmu_translate_page(res, env, vaddr, rw, + is_user, debug); + } + done: + env->pregs[PR_SRS] =3D old_srs; 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X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 11/39] target/cris: Reindent op_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Fix all of the coding style errors in this file at once. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/cris/op_helper.c | 817 +++++++++++++++++++--------------------- 1 file changed, 398 insertions(+), 419 deletions(-) diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 26a395b413..e4c6942922 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -48,9 +48,10 @@ void helper_raise_exception(CPUCRISState *env, uint32_t = index) void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) { #if !defined(CONFIG_USER_ONLY) - pid &=3D 0xff; - if (pid !=3D (env->pregs[PR_PID] & 0xff)) - cris_mmu_flush_pid(env, env->pregs[PR_PID]); + pid &=3D 0xff; + if (pid !=3D (env->pregs[PR_PID] & 0xff)) { + cris_mmu_flush_pid(env, env->pregs[PR_PID]); + } #endif } =20 @@ -66,541 +67,519 @@ void helper_spc_write(CPUCRISState *env, uint32_t new= _spc) } =20 /* Used by the tlb decoder. */ -#define EXTRACT_FIELD(src, start, end) \ - (((src) >> start) & ((1 << (end - start + 1)) - 1)) +#define EXTRACT_FIELD(src, start, end) \ + (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { #if !defined(CONFIG_USER_ONLY) CRISCPU *cpu =3D cris_env_get_cpu(env); #endif - uint32_t srs; - srs =3D env->pregs[PR_SRS]; - srs &=3D 3; - env->sregs[srs][sreg] =3D env->regs[reg]; + uint32_t srs; + srs =3D env->pregs[PR_SRS]; + srs &=3D 3; + env->sregs[srs][sreg] =3D env->regs[reg]; =20 #if !defined(CONFIG_USER_ONLY) - if (srs =3D=3D 1 || srs =3D=3D 2) { - if (sreg =3D=3D 6) { - /* Writes to tlb-hi write to mm_cause as a side=20 - effect. */ - env->sregs[SFR_RW_MM_TLB_HI] =3D env->regs[reg]; - env->sregs[SFR_R_MM_CAUSE] =3D env->regs[reg]; - } - else if (sreg =3D=3D 5) { - uint32_t set; - uint32_t idx; - uint32_t lo, hi; - uint32_t vaddr; - int tlb_v; + if (srs =3D=3D 1 || srs =3D=3D 2) { + if (sreg =3D=3D 6) { + /* Writes to tlb-hi write to mm_cause as a side effect. */ + env->sregs[SFR_RW_MM_TLB_HI] =3D env->regs[reg]; + env->sregs[SFR_R_MM_CAUSE] =3D env->regs[reg]; + } else if (sreg =3D=3D 5) { + uint32_t set; + uint32_t idx; + uint32_t lo, hi; + uint32_t vaddr; + int tlb_v; =20 - idx =3D set =3D env->sregs[SFR_RW_MM_TLB_SEL]; - set >>=3D 4; - set &=3D 3; + idx =3D set =3D env->sregs[SFR_RW_MM_TLB_SEL]; + set >>=3D 4; + set &=3D 3; =20 - idx &=3D 15; - /* We've just made a write to tlb_lo. */ - lo =3D env->sregs[SFR_RW_MM_TLB_LO]; - /* Writes are done via r_mm_cause. */ - hi =3D env->sregs[SFR_R_MM_CAUSE]; + idx &=3D 15; + /* We've just made a write to tlb_lo. */ + lo =3D env->sregs[SFR_RW_MM_TLB_LO]; + /* Writes are done via r_mm_cause. */ + hi =3D env->sregs[SFR_R_MM_CAUSE]; =20 - vaddr =3D EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi, - 13, 31); - vaddr <<=3D TARGET_PAGE_BITS; - tlb_v =3D EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo, - 3, 3); - env->tlbsets[srs - 1][set][idx].lo =3D lo; - env->tlbsets[srs - 1][set][idx].hi =3D hi; + vaddr =3D EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].hi, 13= , 31); + vaddr <<=3D TARGET_PAGE_BITS; + tlb_v =3D EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].lo, 3,= 3); + env->tlbsets[srs - 1][set][idx].lo =3D lo; + env->tlbsets[srs - 1][set][idx].hi =3D hi; =20 - D_LOG("tlb flush vaddr=3D%x v=3D%d pc=3D%x\n",=20 - vaddr, tlb_v, env->pc); - if (tlb_v) { + D_LOG("tlb flush vaddr=3D%x v=3D%d pc=3D%x\n", + vaddr, tlb_v, env->pc); + if (tlb_v) { tlb_flush_page(CPU(cpu), vaddr); - } - } - } + } + } + } #endif } =20 void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg) { - uint32_t srs; - env->pregs[PR_SRS] &=3D 3; - srs =3D env->pregs[PR_SRS]; -=09 + uint32_t srs; + env->pregs[PR_SRS] &=3D 3; + srs =3D env->pregs[PR_SRS]; + #if !defined(CONFIG_USER_ONLY) - if (srs =3D=3D 1 || srs =3D=3D 2) - { - uint32_t set; - uint32_t idx; - uint32_t lo, hi; + if (srs =3D=3D 1 || srs =3D=3D 2) { + uint32_t set; + uint32_t idx; + uint32_t lo, hi; =20 - idx =3D set =3D env->sregs[SFR_RW_MM_TLB_SEL]; - set >>=3D 4; - set &=3D 3; - idx &=3D 15; + idx =3D set =3D env->sregs[SFR_RW_MM_TLB_SEL]; + set >>=3D 4; + set &=3D 3; + idx &=3D 15; =20 - /* Update the mirror regs. */ - hi =3D env->tlbsets[srs - 1][set][idx].hi; - lo =3D env->tlbsets[srs - 1][set][idx].lo; - env->sregs[SFR_RW_MM_TLB_HI] =3D hi; - env->sregs[SFR_RW_MM_TLB_LO] =3D lo; - } + /* Update the mirror regs. */ + hi =3D env->tlbsets[srs - 1][set][idx].hi; + lo =3D env->tlbsets[srs - 1][set][idx].lo; + env->sregs[SFR_RW_MM_TLB_HI] =3D hi; + env->sregs[SFR_RW_MM_TLB_LO] =3D lo; + } #endif - env->regs[reg] =3D env->sregs[srs][sreg]; + env->regs[reg] =3D env->sregs[srs][sreg]; } =20 static void cris_ccs_rshift(CPUCRISState *env) { - uint32_t ccs; + uint32_t ccs; =20 - /* Apply the ccs shift. */ - ccs =3D env->pregs[PR_CCS]; - ccs =3D (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10); - if (ccs & U_FLAG) - { - /* Enter user mode. */ - env->ksp =3D env->regs[R_SP]; - env->regs[R_SP] =3D env->pregs[PR_USP]; - } + /* Apply the ccs shift. */ + ccs =3D env->pregs[PR_CCS]; + ccs =3D (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10); + if (ccs & U_FLAG) { + /* Enter user mode. */ + env->ksp =3D env->regs[R_SP]; + env->regs[R_SP] =3D env->pregs[PR_USP]; + } =20 - env->pregs[PR_CCS] =3D ccs; + env->pregs[PR_CCS] =3D ccs; } =20 void helper_rfe(CPUCRISState *env) { - int rflag =3D env->pregs[PR_CCS] & R_FLAG; + int rflag =3D env->pregs[PR_CCS] & R_FLAG; =20 - D_LOG("rfe: erp=3D%x pid=3D%x ccs=3D%x btarget=3D%x\n",=20 - env->pregs[PR_ERP], env->pregs[PR_PID], - env->pregs[PR_CCS], - env->btarget); + D_LOG("rfe: erp=3D%x pid=3D%x ccs=3D%x btarget=3D%x\n", + env->pregs[PR_ERP], env->pregs[PR_PID], + env->pregs[PR_CCS], + env->btarget); =20 - cris_ccs_rshift(env); + cris_ccs_rshift(env); =20 - /* RFE sets the P_FLAG only if the R_FLAG is not set. */ - if (!rflag) - env->pregs[PR_CCS] |=3D P_FLAG; + /* RFE sets the P_FLAG only if the R_FLAG is not set. */ + if (!rflag) { + env->pregs[PR_CCS] |=3D P_FLAG; + } } =20 void helper_rfn(CPUCRISState *env) { - int rflag =3D env->pregs[PR_CCS] & R_FLAG; + int rflag =3D env->pregs[PR_CCS] & R_FLAG; =20 - D_LOG("rfn: erp=3D%x pid=3D%x ccs=3D%x btarget=3D%x\n",=20 - env->pregs[PR_ERP], env->pregs[PR_PID], - env->pregs[PR_CCS], - env->btarget); + D_LOG("rfn: erp=3D%x pid=3D%x ccs=3D%x btarget=3D%x\n", + env->pregs[PR_ERP], env->pregs[PR_PID], + env->pregs[PR_CCS], + env->btarget); =20 - cris_ccs_rshift(env); + cris_ccs_rshift(env); =20 - /* Set the P_FLAG only if the R_FLAG is not set. */ - if (!rflag) - env->pregs[PR_CCS] |=3D P_FLAG; + /* Set the P_FLAG only if the R_FLAG is not set. */ + if (!rflag) { + env->pregs[PR_CCS] |=3D P_FLAG; + } =20 - /* Always set the M flag. */ - env->pregs[PR_CCS] |=3D M_FLAG_V32; + /* Always set the M flag. */ + env->pregs[PR_CCS] |=3D M_FLAG_V32; } =20 uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t= ccs) { - /* FIXME: clean this up. */ + /* FIXME: clean this up. */ =20 - /* des ref: - The N flag is set according to the selected bit in the dest reg. - The Z flag is set if the selected bit and all bits to the right are - zero. - The X flag is cleared. - Other flags are left untouched. - The destination reg is not affected.*/ - unsigned int fz, sbit, bset, mask, masked_t0; + /* + * des ref: + * The N flag is set according to the selected bit in the dest reg. + * The Z flag is set if the selected bit and all bits to the right are + * zero. + * The X flag is cleared. + * Other flags are left untouched. + * The destination reg is not affected. + */ + unsigned int fz, sbit, bset, mask, masked_t0; =20 - sbit =3D t1 & 31; - bset =3D !!(t0 & (1 << sbit)); - mask =3D sbit =3D=3D 31 ? -1 : (1 << (sbit + 1)) - 1; - masked_t0 =3D t0 & mask; - fz =3D !(masked_t0 | bset); + sbit =3D t1 & 31; + bset =3D !!(t0 & (1 << sbit)); + mask =3D sbit =3D=3D 31 ? -1 : (1 << (sbit + 1)) - 1; + masked_t0 =3D t0 & mask; + fz =3D !(masked_t0 | bset); =20 - /* Clear the X, N and Z flags. */ - ccs =3D ccs & ~(X_FLAG | N_FLAG | Z_FLAG); - if (env->pregs[PR_VR] < 32) - ccs &=3D ~(V_FLAG | C_FLAG); - /* Set the N and Z flags accordingly. */ - ccs |=3D (bset << 3) | (fz << 2); - return ccs; + /* Clear the X, N and Z flags. */ + ccs =3D ccs & ~(X_FLAG | N_FLAG | Z_FLAG); + if (env->pregs[PR_VR] < 32) { + ccs &=3D ~(V_FLAG | C_FLAG); + } + /* Set the N and Z flags accordingly. */ + ccs |=3D (bset << 3) | (fz << 2); + return ccs; } =20 static inline uint32_t evaluate_flags_writeback(CPUCRISState *env, uint32_t flags, uint32_t c= cs) { - unsigned int x, z, mask; + unsigned int x, z, mask; =20 - /* Extended arithmetics, leave the z flag alone. */ - x =3D env->cc_x; - mask =3D env->cc_mask | X_FLAG; - if (x) { - z =3D flags & Z_FLAG; - mask =3D mask & ~z; - } - flags &=3D mask; + /* Extended arithmetics, leave the z flag alone. */ + x =3D env->cc_x; + mask =3D env->cc_mask | X_FLAG; + if (x) { + z =3D flags & Z_FLAG; + mask =3D mask & ~z; + } + flags &=3D mask; =20 - /* all insn clear the x-flag except setf or clrf. */ - ccs &=3D ~mask; - ccs |=3D flags; - return ccs; + /* all insn clear the x-flag except setf or clrf. */ + ccs &=3D ~mask; + ccs |=3D flags; + return ccs; } =20 uint32_t helper_evaluate_flags_muls(CPUCRISState *env, uint32_t ccs, uint32_t res, uint32_t m= of) { - uint32_t flags =3D 0; - int64_t tmp; - int dneg; + uint32_t flags =3D 0; + int64_t tmp; + int dneg; =20 - dneg =3D ((int32_t)res) < 0; + dneg =3D ((int32_t)res) < 0; =20 - tmp =3D mof; - tmp <<=3D 32; - tmp |=3D res; - if (tmp =3D=3D 0) - flags |=3D Z_FLAG; - else if (tmp < 0) - flags |=3D N_FLAG; - if ((dneg && mof !=3D -1) - || (!dneg && mof !=3D 0)) - flags |=3D V_FLAG; - return evaluate_flags_writeback(env, flags, ccs); + tmp =3D mof; + tmp <<=3D 32; + tmp |=3D res; + if (tmp =3D=3D 0) { + flags |=3D Z_FLAG; + } else if (tmp < 0) { + flags |=3D N_FLAG; + } + if ((dneg && mof !=3D -1) || (!dneg && mof !=3D 0)) { + flags |=3D V_FLAG; + } + return evaluate_flags_writeback(env, flags, ccs); } =20 uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, uint32_t ccs, uint32_t res, uint32_t m= of) { - uint32_t flags =3D 0; - uint64_t tmp; + uint32_t flags =3D 0; + uint64_t tmp; =20 - tmp =3D mof; - tmp <<=3D 32; - tmp |=3D res; - if (tmp =3D=3D 0) - flags |=3D Z_FLAG; - else if (tmp >> 63) - flags |=3D N_FLAG; - if (mof) - flags |=3D V_FLAG; + tmp =3D mof; + tmp <<=3D 32; + tmp |=3D res; + if (tmp =3D=3D 0) { + flags |=3D Z_FLAG; + } else if (tmp >> 63) { + flags |=3D N_FLAG; + } + if (mof) { + flags |=3D V_FLAG; + } =20 - return evaluate_flags_writeback(env, flags, ccs); + return evaluate_flags_writeback(env, flags, ccs); } =20 uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs, uint32_t src, uint32_t dst, uint32_t res) { - uint32_t flags =3D 0; + uint32_t flags =3D 0; =20 - src =3D src & 0x80000000; - dst =3D dst & 0x80000000; + src =3D src & 0x80000000; + dst =3D dst & 0x80000000; =20 - if ((res & 0x80000000L) !=3D 0L) - { - flags |=3D N_FLAG; - if (!src && !dst) - flags |=3D V_FLAG; - else if (src & dst) - flags |=3D R_FLAG; - } - else - { - if (res =3D=3D 0L) - flags |=3D Z_FLAG; - if (src & dst)=20 - flags |=3D V_FLAG; - if (dst | src)=20 - flags |=3D R_FLAG; - } + if ((res & 0x80000000L) !=3D 0L) { + flags |=3D N_FLAG; + if (!src && !dst) { + flags |=3D V_FLAG; + } else if (src & dst) { + flags |=3D R_FLAG; + } + } else { + if (res =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (src & dst) { + flags |=3D V_FLAG; + } + if (dst | src) { + flags |=3D R_FLAG; + } + } =20 - return evaluate_flags_writeback(env, flags, ccs); + return evaluate_flags_writeback(env, flags, ccs); } =20 uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs, uint32_t src, uint32_t dst, uint32_t res) { - uint32_t flags =3D 0; + uint32_t flags =3D 0; =20 - src =3D src & 0x80000000; - dst =3D dst & 0x80000000; + src =3D src & 0x80000000; + dst =3D dst & 0x80000000; =20 - if ((res & 0x80000000L) !=3D 0L) - { - flags |=3D N_FLAG; - if (!src && !dst) - flags |=3D V_FLAG; - else if (src & dst) - flags |=3D C_FLAG; - } - else - { - if (res =3D=3D 0L) - flags |=3D Z_FLAG; - if (src & dst)=20 - flags |=3D V_FLAG; - if (dst | src)=20 - flags |=3D C_FLAG; - } + if ((res & 0x80000000L) !=3D 0L) { + flags |=3D N_FLAG; + if (!src && !dst) { + flags |=3D V_FLAG; + } else if (src & dst) { + flags |=3D C_FLAG; + } + } else { + if (res =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (src & dst) { + flags |=3D V_FLAG; + } + if (dst | src) { + flags |=3D C_FLAG; + } + } =20 - return evaluate_flags_writeback(env, flags, ccs); + return evaluate_flags_writeback(env, flags, ccs); } =20 uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs, uint32_t src, uint32_t dst, uint32_t res) { - uint32_t flags =3D 0; + uint32_t flags =3D 0; =20 - src =3D (~src) & 0x80000000; - dst =3D dst & 0x80000000; + src =3D (~src) & 0x80000000; + dst =3D dst & 0x80000000; =20 - if ((res & 0x80000000L) !=3D 0L) - { - flags |=3D N_FLAG; - if (!src && !dst) - flags |=3D V_FLAG; - else if (src & dst) - flags |=3D C_FLAG; - } - else - { - if (res =3D=3D 0L) - flags |=3D Z_FLAG; - if (src & dst)=20 - flags |=3D V_FLAG; - if (dst | src)=20 - flags |=3D C_FLAG; - } + if ((res & 0x80000000L) !=3D 0L) { + flags |=3D N_FLAG; + if (!src && !dst) { + flags |=3D V_FLAG; + } else if (src & dst) { + flags |=3D C_FLAG; + } + } else { + if (res =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (src & dst) { + flags |=3D V_FLAG; + } + if (dst | src) { + flags |=3D C_FLAG; + } + } =20 - flags ^=3D C_FLAG; - return evaluate_flags_writeback(env, flags, ccs); + flags ^=3D C_FLAG; + return evaluate_flags_writeback(env, flags, ccs); } =20 uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, uint32_t ccs, uint32_t res) { - uint32_t flags =3D 0; + uint32_t flags =3D 0; =20 - if ((int32_t)res < 0) - flags |=3D N_FLAG; - else if (res =3D=3D 0L) - flags |=3D Z_FLAG; + if ((int32_t)res < 0) { + flags |=3D N_FLAG; + } else if (res =3D=3D 0L) { + flags |=3D Z_FLAG; + } =20 - return evaluate_flags_writeback(env, flags, ccs); + return evaluate_flags_writeback(env, flags, ccs); } + uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, uint32_t ccs, uint32_t res) { - uint32_t flags =3D 0; + uint32_t flags =3D 0; =20 - if ((int16_t)res < 0L) - flags |=3D N_FLAG; - else if (res =3D=3D 0) - flags |=3D Z_FLAG; + if ((int16_t)res < 0L) { + flags |=3D N_FLAG; + } else if (res =3D=3D 0) { + flags |=3D Z_FLAG; + } =20 - return evaluate_flags_writeback(env, flags, ccs); + return evaluate_flags_writeback(env, flags, ccs); } =20 -/* TODO: This is expensive. We could split things up and only evaluate par= t of - CCR on a need to know basis. For now, we simply re-evaluate everything.= */ +/* + * TODO: This is expensive. We could split things up and only evaluate par= t of + * CCR on a need to know basis. For now, we simply re-evaluate everything. + */ void helper_evaluate_flags(CPUCRISState *env) { - uint32_t src, dst, res; - uint32_t flags =3D 0; + uint32_t src, dst, res; + uint32_t flags =3D 0; =20 - src =3D env->cc_src; - dst =3D env->cc_dest; - res =3D env->cc_result; + src =3D env->cc_src; + dst =3D env->cc_dest; + res =3D env->cc_result; =20 - if (env->cc_op =3D=3D CC_OP_SUB || env->cc_op =3D=3D CC_OP_CMP) - src =3D ~src; + if (env->cc_op =3D=3D CC_OP_SUB || env->cc_op =3D=3D CC_OP_CMP) { + src =3D ~src; + } =20 - /* Now, evaluate the flags. This stuff is based on - Per Zander's CRISv10 simulator. */ - switch (env->cc_size) - { - case 1: - if ((res & 0x80L) !=3D 0L) - { - flags |=3D N_FLAG; - if (((src & 0x80L) =3D=3D 0L) - && ((dst & 0x80L) =3D=3D 0L)) - { - flags |=3D V_FLAG; - } - else if (((src & 0x80L) !=3D 0L) - && ((dst & 0x80L) !=3D 0L)) - { - flags |=3D C_FLAG; - } - } - else - { - if ((res & 0xFFL) =3D=3D 0L) - { - flags |=3D Z_FLAG; - } - if (((src & 0x80L) !=3D 0L) - && ((dst & 0x80L) !=3D 0L)) - { - flags |=3D V_FLAG; - } - if ((dst & 0x80L) !=3D 0L - || (src & 0x80L) !=3D 0L) - { - flags |=3D C_FLAG; - } - } - break; - case 2: - if ((res & 0x8000L) !=3D 0L) - { - flags |=3D N_FLAG; - if (((src & 0x8000L) =3D=3D 0L) - && ((dst & 0x8000L) =3D=3D 0L)) - { - flags |=3D V_FLAG; - } - else if (((src & 0x8000L) !=3D 0L) - && ((dst & 0x8000L) !=3D 0L)) - { - flags |=3D C_FLAG; - } - } - else - { - if ((res & 0xFFFFL) =3D=3D 0L) - { - flags |=3D Z_FLAG; - } - if (((src & 0x8000L) !=3D 0L) - && ((dst & 0x8000L) !=3D 0L)) - { - flags |=3D V_FLAG; - } - if ((dst & 0x8000L) !=3D 0L - || (src & 0x8000L) !=3D 0L) - { - flags |=3D C_FLAG; - } - } - break; - case 4: - if ((res & 0x80000000L) !=3D 0L) - { - flags |=3D N_FLAG; - if (((src & 0x80000000L) =3D=3D 0L) - && ((dst & 0x80000000L) =3D=3D 0L)) - { - flags |=3D V_FLAG; - } - else if (((src & 0x80000000L) !=3D 0L) && - ((dst & 0x80000000L) !=3D 0L)) - { - flags |=3D C_FLAG; - } - } - else - { - if (res =3D=3D 0L) - flags |=3D Z_FLAG; - if (((src & 0x80000000L) !=3D 0L) - && ((dst & 0x80000000L) !=3D 0L)) - flags |=3D V_FLAG; - if ((dst & 0x80000000L) !=3D 0L - || (src & 0x80000000L) !=3D 0L) - flags |=3D C_FLAG; - } - break; - default: - break; - } + /* + * Now, evaluate the flags. This stuff is based on + * Per Zander's CRISv10 simulator. + */ + switch (env->cc_size) { + case 1: + if ((res & 0x80L) !=3D 0L) { + flags |=3D N_FLAG; + if (((src & 0x80L) =3D=3D 0L) && ((dst & 0x80L) =3D=3D 0L)) { + flags |=3D V_FLAG; + } else if (((src & 0x80L) !=3D 0L) && ((dst & 0x80L) !=3D 0L))= { + flags |=3D C_FLAG; + } + } else { + if ((res & 0xFFL) =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (((src & 0x80L) !=3D 0L) && ((dst & 0x80L) !=3D 0L)) { + flags |=3D V_FLAG; + } + if ((dst & 0x80L) !=3D 0L || (src & 0x80L) !=3D 0L) { + flags |=3D C_FLAG; + } + } + break; + case 2: + if ((res & 0x8000L) !=3D 0L) { + flags |=3D N_FLAG; + if (((src & 0x8000L) =3D=3D 0L) && ((dst & 0x8000L) =3D=3D 0L)= ) { + flags |=3D V_FLAG; + } else if (((src & 0x8000L) !=3D 0L) && ((dst & 0x8000L) !=3D = 0L)) { + flags |=3D C_FLAG; + } + } else { + if ((res & 0xFFFFL) =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (((src & 0x8000L) !=3D 0L) && ((dst & 0x8000L) !=3D 0L)) { + flags |=3D V_FLAG; + } + if ((dst & 0x8000L) !=3D 0L || (src & 0x8000L) !=3D 0L) { + flags |=3D C_FLAG; + } + } + break; + case 4: + if ((res & 0x80000000L) !=3D 0L) { + flags |=3D N_FLAG; + if (((src & 0x80000000L) =3D=3D 0L) && ((dst & 0x80000000L) = =3D=3D 0L)) { + flags |=3D V_FLAG; + } else if (((src & 0x80000000L) !=3D 0L) && + ((dst & 0x80000000L) !=3D 0L)) { + flags |=3D C_FLAG; + } + } else { + if (res =3D=3D 0L) { + flags |=3D Z_FLAG; + } + if (((src & 0x80000000L) !=3D 0L) && ((dst & 0x80000000L) !=3D= 0L)) { + flags |=3D V_FLAG; + } + if ((dst & 0x80000000L) !=3D 0L || (src & 0x80000000L) !=3D 0L= ) { + flags |=3D C_FLAG; + } + } + break; + default: + break; + } =20 - if (env->cc_op =3D=3D CC_OP_SUB || env->cc_op =3D=3D CC_OP_CMP) - flags ^=3D C_FLAG; + if (env->cc_op =3D=3D CC_OP_SUB || env->cc_op =3D=3D CC_OP_CMP) { + flags ^=3D C_FLAG; + } =20 - env->pregs[PR_CCS] =3D evaluate_flags_writeback(env, flags, - env->pregs[PR_CCS]); + env->pregs[PR_CCS] =3D evaluate_flags_writeback(env, flags, + env->pregs[PR_CCS]); } =20 void helper_top_evaluate_flags(CPUCRISState *env) { - switch (env->cc_op) - { - case CC_OP_MCP: - env->pregs[PR_CCS] =3D helper_evaluate_flags_mcp(e= nv, - env->pregs[PR_CCS], env->cc_src, - env->cc_dest, env->cc_result); - break; - case CC_OP_MULS: - env->pregs[PR_CCS] =3D helper_evaluate_flags_muls(= env, - env->pregs[PR_CCS], env->cc_result, - env->pregs[PR_MOF]); - break; - case CC_OP_MULU: - env->pregs[PR_CCS] =3D helper_evaluate_flags_mulu(= env, - env->pregs[PR_CCS], env->cc_result, - env->pregs[PR_MOF]); - break; - case CC_OP_MOVE: - case CC_OP_AND: - case CC_OP_OR: - case CC_OP_XOR: - case CC_OP_ASR: - case CC_OP_LSR: - case CC_OP_LSL: - switch (env->cc_size) - { - case 4: - env->pregs[PR_CCS] =3D - helper_evaluate_flags_move_4(env, - env->pregs[PR_CCS], - env->cc_result); - break; - case 2: - env->pregs[PR_CCS] =3D - helper_evaluate_flags_move_2(env, - env->pregs[PR_CCS], - env->cc_result); - break; - default: - helper_evaluate_flags(env); - break; - } - break; - case CC_OP_FLAGS: - /* live. */ - break; - case CC_OP_SUB: - case CC_OP_CMP: - if (env->cc_size =3D=3D 4) - env->pregs[PR_CCS] =3D - helper_evaluate_flags_sub_4(env, - env->pregs[PR_CCS], - env->cc_src, env->cc_dest, - env->cc_result); - else - helper_evaluate_flags(env); - break; - default: - { - switch (env->cc_size) - { - case 4: - env->pregs[PR_CCS] =3D - helper_evaluate_flags_alu_4(env, - env->pregs[PR_CCS], - env->cc_src, env->cc_dest, - env->cc_result); - break; - default: - helper_evaluate_flags(env); - break; - } - } - break; - } + switch (env->cc_op) { + case CC_OP_MCP: + env->pregs[PR_CCS] + =3D helper_evaluate_flags_mcp(env, env->pregs[PR_CCS], + env->cc_src, env->cc_dest, + env->cc_result); + break; + case CC_OP_MULS: + env->pregs[PR_CCS] + =3D helper_evaluate_flags_muls(env, env->pregs[PR_CCS], + env->cc_result, env->pregs[PR_MOF= ]); + break; + case CC_OP_MULU: + env->pregs[PR_CCS] + =3D helper_evaluate_flags_mulu(env, env->pregs[PR_CCS], + env->cc_result, env->pregs[PR_MOF= ]); + break; + case CC_OP_MOVE: + case CC_OP_AND: + case CC_OP_OR: + case CC_OP_XOR: + case CC_OP_ASR: + case CC_OP_LSR: + case CC_OP_LSL: + switch (env->cc_size) { + case 4: + env->pregs[PR_CCS] =3D + helper_evaluate_flags_move_4(env, + env->pregs[PR_CCS], + env->cc_result); + break; + case 2: + env->pregs[PR_CCS] =3D + helper_evaluate_flags_move_2(env, + env->pregs[PR_CCS], + env->cc_result); + break; + default: + helper_evaluate_flags(env); + break; + } + break; + case CC_OP_FLAGS: + /* live. */ + break; + case CC_OP_SUB: + case CC_OP_CMP: + if (env->cc_size =3D=3D 4) { + env->pregs[PR_CCS] =3D + helper_evaluate_flags_sub_4(env, + env->pregs[PR_CCS], + env->cc_src, env->cc_dest, + env->cc_result); + } else { + helper_evaluate_flags(env); + } + break; + default: + switch (env->cc_size) { + case 4: + env->pregs[PR_CCS] =3D + helper_evaluate_flags_alu_4(env, + env->pregs[PR_CCS], + env->cc_src, env->cc_dest, + env->cc_result); + break; + default: + helper_evaluate_flags(env); + break; + } + break; + } } --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 12/39] target/cris: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace cris_env_get_cpu with env_archcpu. The combination CPU(cris_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/cris/cpu.h | 5 ----- linux-user/cris/cpu_loop.c | 2 +- target/cris/mmu.c | 3 +-- target/cris/op_helper.c | 10 +++------- target/cris/translate.c | 2 +- 5 files changed, 6 insertions(+), 16 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 0746d19f38..e9e4e39a40 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,11 +183,6 @@ struct CRISCPU { CPUCRISState env; }; =20 -static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) -{ - return container_of(env, CRISCPU, env); -} - #define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index 7ec36cb0b5..86e711108d 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUCRISState *env) { - CPUState *cs =3D CPU(cris_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/cris/mmu.c b/target/cris/mmu.c index 9cb73bbfec..2acbcfd1c7 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -288,7 +288,6 @@ static int cris_mmu_translate_page(struct cris_mmu_resu= lt *res, =20 void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { - CRISCPU *cpu =3D cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -312,7 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) if (tlb_v && !tlb_g && (tlb_pid =3D=3D pid)) { vaddr =3D tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=3D%x vaddr=3D%x\n", pid, vaddr); - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index e4c6942922..6b1e7ae4a8 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -39,7 +39,7 @@ =20 void helper_raise_exception(CPUCRISState *env, uint32_t index) { - CPUState *cs =3D CPU(cris_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); @@ -58,8 +58,7 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu =3D cris_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 tlb_flush_page(cs, env->pregs[PR_SPC]); tlb_flush_page(cs, new_spc); @@ -72,9 +71,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc) =20 void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { -#if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu =3D cris_env_get_cpu(env); -#endif uint32_t srs; srs =3D env->pregs[PR_SRS]; srs &=3D 3; @@ -112,7 +108,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t s= reg, uint32_t reg) D_LOG("tlb flush vaddr=3D%x v=3D%d pc=3D%x\n", vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/translate.c b/target/cris/translate.c index 31b40a57f9..3429a3b768 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3097,7 +3097,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) * delayslot, like in real hw. */ pc_start =3D tb->pc & ~1; - dc->cpu =3D cris_env_get_cpu(env); + dc->cpu =3D env_archcpu(env); dc->tb =3D tb; =20 dc->is_jmp =3D DISAS_NEXT; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681056; cv=none; d=zoho.com; s=zohoarc; b=ncSarBWYo/p1N3sYCk+qreQFqD77nHbRZSaQL/h9qdo9ldTAhlqtLG5QarMjIKFeIVjcaUWoJG1iN/YEUHgPm4NFl22Ptr+i3eBh/0cvb+v5PV0kcYNuk2ZDrkQSy4yWRgRXA1O8Mujj1YOfsZ7GnkVbodKH/3+ESEj3KnBpHSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559681056; 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X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v4 13/39] target/hppa: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace hppa_env_get_cpu with env_archcpu. The combination CPU(hppa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 ----- linux-user/hppa/cpu_loop.c | 2 +- target/hppa/helper.c | 3 +-- target/hppa/int_helper.c | 4 ++-- target/hppa/mem_helper.c | 10 ++++------ target/hppa/op_helper.c | 8 +++----- 6 files changed, 11 insertions(+), 21 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 0cb1fc8800..75e6a91a5e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,11 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 -static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) -{ - return container_of(env, HPPACPU, env); -} - #define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 880955fdef..9915456a1d 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -105,7 +105,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) =20 void cpu_loop(CPUHPPAState *env) { - CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 11c61b3ca2..0dcd105b88 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -71,8 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) /* If PSW_P changes, it affects how we translate addresses. */ if ((psw ^ old_psw) & PSW_P) { #ifndef CONFIG_USER_ONLY - CPUState *src =3D CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); #endif } } diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 8d5edd3a20..89241c31e7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -77,7 +77,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg va= l) { env->cr[CR_EIRR] &=3D ~val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } =20 @@ -85,7 +85,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg va= l) { env->cr[CR_EIEM] =3D val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 0fd3ac6645..b12c5b5054 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -56,7 +56,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, v= addr addr) =20 static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) { - CPUState *cs =3D CPU(hppa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned i, n =3D 1 << (2 * ent->page_size); uint64_t addr =3D ent->va_b; =20 @@ -329,7 +329,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data da= ta) =20 void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); + CPUState *src =3D env_cpu(env); CPUState *cpu; trace_hppa_tlb_ptlb(env); run_on_cpu_data data =3D RUN_ON_CPU_TARGET_PTR(addr); @@ -346,17 +346,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong add= r) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } =20 void cpu_hppa_change_prot_id(CPUHPPAState *env) { if (env->psw & PSW_P) { - CPUState *src =3D CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } } =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 952e97a7d7..04d23c1b22 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -29,8 +29,7 @@ =20 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); @@ -38,8 +37,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int ex= cp) =20 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit_restore(cs, ra); @@ -630,7 +628,7 @@ target_ureg HELPER(read_interval_timer)(void) #ifndef CONFIG_USER_ONLY void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) { - HPPACPU *cpu =3D hppa_env_get_cpu(env); + HPPACPU *cpu =3D env_archcpu(env); uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t timeout; =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681231; cv=none; d=zoho.com; s=zohoarc; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.16 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=defirvbA6023UE6OqyQA+R97OV+NvBSzbYLljfjvZQ0=; b=zMKhz2Ad/5PUXsNRnXgMocuYeFUOAbsdwXdNH7AmFajX37lMvRlI3unA3Eqri47YBv RZCwMeUz5qYdBmOwYy/WtCcCZ4U8ze+WzjJ9d7kSkpxXjedniXh/4KoCgAAd63wd6Vy/ 8qHRdFdq7rjRw6R3UQWr6nJgoBk5KJCWi96dgGDcnmR4Q2lQpYrSg/DYtlBb7WpsQViX POIPPxYruYqg646JMfoOqFpgxR9UX6Wl48K3zE90K5rAk5Xkc8a5wIsDMIjhldw6L2Ih fqEVC1yMHaspf9dYhgrHsuVME8XwWgHfJ4F9N+/URtlCpGhWxVtQ7A1w9OOiuDzvaFGd 4RpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=defirvbA6023UE6OqyQA+R97OV+NvBSzbYLljfjvZQ0=; b=JLrXSA+1srwfx3VlBe616Xitrk26XpHkfVoTOQhk00Ig3O/C8E7rESVBGMivARB126 Ki1azKuY9WZvMBZeArVoWtgceK15m4+L0VVaoZUCo6cYVHtwHd2HpI2diaSm398yDnAC uu/lVjMFq01IhJrZlAJlwr+Ob773GDJlpn/rqh2DZgT0hgtquF5CWR6hrCweVNP5GT16 JKM4/thfTo88pfUXx6UTsE95UrZ5eisWCP0Xo617t0raczp6wG3ukzXGHDmh0z+imAcC GB/op2zfOvTBkXP88CiyWbsxd9LsJ1O83rvN+AJLeTDIsdqjTofEjArZ5ffX9MLPeUTm LU8w== X-Gm-Message-State: APjAAAWCG27R7/NXYw3La1dVu6tHejUjgTusoiEE70nZt6p6LjPwnSBr avdfEMtI8T+PJeJFi06PFvD625Si9nQtNA== X-Google-Smtp-Source: APXvYqzrbBFYjJpKC+xtOpsniBYlv4lkfzfHCYy2zhj2WSWGURcpwtNNbZJxR0Z0k7hlvnMOGC74uw== X-Received: by 2002:aca:845:: with SMTP id 66mr3638609oii.163.1559680458481; Tue, 04 Jun 2019 13:34:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:26 -0500 Message-Id: <20190604203351.27778-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v4 14/39] target/i386: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace x86_env_get_cpu with env_archcpu. The combination CPU(x86_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/i386/cpu.h | 5 ----- bsd-user/main.c | 3 +-- hw/i386/kvmvapic.c | 4 ++-- hw/i386/pc.c | 2 +- linux-user/i386/cpu_loop.c | 2 +- linux-user/i386/signal.c | 2 +- linux-user/vm86.c | 18 +++++++++--------- target/i386/bpt_helper.c | 4 ++-- target/i386/cpu.c | 4 ++-- target/i386/excp_helper.c | 2 +- target/i386/fpu_helper.c | 2 +- target/i386/helper.c | 16 ++++++---------- target/i386/misc_helper.c | 24 +++++++++++------------- target/i386/seg_helper.c | 14 +++++++------- target/i386/smm_helper.c | 4 ++-- target/i386/svm_helper.c | 22 +++++++++++----------- 16 files changed, 58 insertions(+), 70 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 103fd709b0..709d88cfcf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1480,11 +1480,6 @@ struct X86CPU { int32_t hv_max_vps; }; =20 -static inline X86CPU *x86_env_get_cpu(CPUX86State *env) -{ - return container_of(env, X86CPU, env); -} - #define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/bsd-user/main.c b/bsd-user/main.c index 6192e9d91e..bfdcae4269 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -140,8 +140,7 @@ static void set_idt(int n, unsigned int dpl) =20 void cpu_loop(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(cpu); int trapnr; abi_ulong pc; //target_siginfo_t info; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 70f6f26a94..fe5b12ef6e 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -152,7 +152,7 @@ static void update_guest_rom_state(VAPICROMState *s) =20 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr paddr; target_ulong addr; =20 @@ -279,7 +279,7 @@ instruction_ok: =20 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_u= long ip) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr paddr; uint32_t rom_state_vaddr; uint32_t pos, patch, offset; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index edc240bcbf..1b08b56362 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -406,7 +406,7 @@ uint64_t cpu_get_tsc(CPUX86State *env) /* IRQ handling */ int cpu_get_pic_interrupt(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int intno; =20 if (!kvm_irqchip_in_kernel()) { diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 51cfa006c9..71da24384f 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -82,7 +82,7 @@ static void set_idt(int n, unsigned int dpl) =20 void cpu_loop(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_ulong pc; abi_ulong ret; diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index fecb4c99c3..97a39204cc 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -198,7 +198,7 @@ static void setup_sigcontext(struct target_sigcontext *= sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); #ifndef TARGET_X86_64 uint16_t magic; =20 diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 9c393df424..2fa7a89edc 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,7 @@ static inline unsigned int vm_getl(CPUX86State *env, =20 void save_v86_state(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct target_vm86plus_struct * target_v86; =20 @@ -132,7 +132,7 @@ static inline void return_to_32bit(CPUX86State *env, in= t retval) =20 static inline int set_IF(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->v86flags |=3D VIF_MASK; @@ -145,7 +145,7 @@ static inline int set_IF(CPUX86State *env) =20 static inline void clear_IF(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->v86flags &=3D ~VIF_MASK; @@ -163,7 +163,7 @@ static inline void clear_AC(CPUX86State *env) =20 static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 set_flags(ts->v86flags, eflags, ts->v86mask); @@ -177,7 +177,7 @@ static inline int set_vflags_long(unsigned long eflags,= CPUX86State *env) =20 static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); @@ -191,7 +191,7 @@ static inline int set_vflags_short(unsigned short flags= , CPUX86State *env) =20 static inline unsigned int get_vflags(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; unsigned int flags; =20 @@ -208,7 +208,7 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -267,7 +267,7 @@ void handle_vm86_trap(CPUX86State *env, int trapno) =20 void handle_vm86_fault(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; @@ -392,7 +392,7 @@ void handle_vm86_fault(CPUX86State *env) =20 int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target/i386/bpt_helper.c b/target/i386/bpt_helper.c index b3efdc77ec..c3a8ea73c9 100644 --- a/target/i386/bpt_helper.c +++ b/target/i386/bpt_helper.c @@ -53,7 +53,7 @@ static inline int hw_breakpoint_len(unsigned long dr7, in= t index) =20 static int hw_breakpoint_insert(CPUX86State *env, int index) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong dr7 =3D env->dr[7]; target_ulong drN =3D env->dr[index]; int err =3D 0; @@ -97,7 +97,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) =20 static void hw_breakpoint_remove(CPUX86State *env, int index) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c1ab86d63e..a461d8d92c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4222,8 +4222,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); uint32_t pkg_offset; uint32_t limit; uint32_t signature[3]; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index fa1ead6404..a9bca7c28b 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -90,7 +90,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *e= nv, int intno, int next_eip_addend, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index ea5a0c4861..005f1f68f8 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -1477,7 +1477,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr= , uint64_t rfbm) env->pkru =3D 0; } if (env->pkru !=3D old_pkru) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); tlb_flush(cs); } } diff --git a/target/i386/helper.c b/target/i386/helper.c index 96336055f3..ff3a60c7cf 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -622,7 +622,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) =20 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int pe_state; =20 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=3D0x%08x\n", new_cr0); @@ -664,19 +664,16 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t ne= w_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { - X86CPU *cpu =3D x86_env_get_cpu(env); - env->cr[3] =3D new_cr3; if (env->cr[0] & CR0_PG_MASK) { qemu_log_mask(CPU_LOG_MMU, "CR3 update: CR3=3D" TARGET_FMT_lx "\n", new_cr3); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { - X86CPU *cpu =3D x86_env_get_cpu(env); uint32_t hflags; =20 #if defined(DEBUG_MMU) @@ -685,7 +682,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 /* Clear bits we're going to recompute. */ @@ -977,8 +974,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int = bank, =20 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 if (kvm_enabled() || whpx_enabled()) { env->tpr_access_type =3D access; @@ -996,8 +993,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned = int selector, target_ulong *base, unsigned int *limit, unsigned int *flags) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); SegmentCache *dt; target_ulong ptr; uint32_t e1, e2; diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 78f2020ef2..3eff6885f8 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -133,7 +133,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - val =3D cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state); + val =3D cpu_get_apic_tpr(env_archcpu(env)->apic_state); } else { val =3D env->v_tpr; } @@ -158,7 +158,7 @@ void helper_write_crN(CPUX86State *env, int reg, target= _ulong t0) case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { qemu_mutex_lock_iothread(); - cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0); + cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0); qemu_mutex_unlock_iothread(); } env->v_tpr =3D t0 & 0x0f; @@ -180,7 +180,7 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) =20 void helper_invlpg(CPUX86State *env, target_ulong addr) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); tlb_flush_page(CPU(cpu), addr); @@ -247,7 +247,7 @@ void helper_wrmsr(CPUX86State *env) env->sysenter_eip =3D val; break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); + cpu_set_apic_base(env_archcpu(env)->apic_state, val); break; case MSR_EFER: { @@ -404,7 +404,7 @@ void helper_rdmsr(CPUX86State *env) val =3D env->sysenter_eip; break; case MSR_IA32_APICBASE: - val =3D cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); + val =3D cpu_get_apic_base(env_archcpu(env)->apic_state); break; case MSR_EFER: val =3D env->efer; @@ -561,7 +561,7 @@ static void do_hlt(X86CPU *cpu) =20 void helper_hlt(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip +=3D next_eip_addend; @@ -580,8 +580,8 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) =20 void helper_mwait(CPUX86State *env, int next_eip_addend) { - CPUState *cs; - X86CPU *cpu; + CPUState *cs =3D env_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 if ((uint32_t)env->regs[R_ECX] !=3D 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -589,8 +589,6 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); env->eip +=3D next_eip_addend; =20 - cpu =3D x86_env_get_cpu(env); - cs =3D CPU(cpu); /* XXX: not complete but not completely erroneous */ if (cs->cpu_index !=3D 0 || CPU_NEXT(cs) !=3D NULL) { do_pause(cpu); @@ -601,7 +599,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) =20 void helper_pause(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); =20 cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip +=3D next_eip_addend; @@ -611,7 +609,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend) =20 void helper_debug(CPUX86State *env) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); @@ -631,7 +629,7 @@ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) =20 void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if ((env->cr[4] & CR4_PKE_MASK) =3D=3D 0) { raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 63e265cb38..87a627f9dc 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -137,7 +137,7 @@ static inline void get_ss_esp_from_tss(CPUX86State *env= , uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl, uintptr_t retaddr) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int type, index, shift; =20 #if 0 @@ -830,7 +830,7 @@ static void do_interrupt_protected(CPUX86State *env, in= t intno, int is_int, =20 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); int index; =20 #if 0 @@ -972,7 +972,7 @@ static void do_interrupt64(CPUX86State *env, int intno,= int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_SYSCALL; env->exception_next_eip =3D env->eip + next_eip_addend; @@ -1172,7 +1172,7 @@ static void do_interrupt_user(CPUX86State *env, int i= ntno, int is_int, static void handle_even_inj(CPUX86State *env, int intno, int is_int, int error_code, int is_hw, int rm) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t event_inj =3D x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct= vmcb, control.event_in= j)); =20 @@ -1312,7 +1312,7 @@ void x86_cpu_do_interrupt(CPUState *cs) =20 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) { - do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); + do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } =20 bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -1763,7 +1763,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, target_ulong ssp, old_ssp, offset, sp; =20 LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=3D%d\n", new_cs, new_eip, sh= ift); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } @@ -2167,7 +2167,7 @@ static inline void helper_ret_protected(CPUX86State *= env, int shift, } LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=3D%d addend=3D0x%x\n", new_cs, new_eip, shift, addend); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); } diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c index c1c34a75db..eb5aa6eb3d 100644 --- a/target/i386/smm_helper.c +++ b/target/i386/smm_helper.c @@ -204,8 +204,8 @@ void do_smm_enter(X86CPU *cpu) =20 void helper_rsm(CPUX86State *env) { - X86CPU *cpu =3D x86_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + X86CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 9fd22a883b..7b8105a1c3 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -84,7 +84,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port,= uint32_t param, static inline void svm_save_seg(CPUX86State *env, hwaddr addr, const SegmentCache *sc) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector), sc->selector); @@ -99,7 +99,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr = addr, static inline void svm_load_seg(CPUX86State *env, hwaddr addr, SegmentCache *sc) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int flags; =20 sc->selector =3D x86_lduw_phys(cs, @@ -122,7 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env,= hwaddr addr, =20 void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; uint64_t nested_ctl; uint32_t event_inj; @@ -314,7 +314,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next= _eip_addend) env->hflags2 |=3D HF2_GIF_MASK; =20 if (int_ctl & V_IRQ_MASK) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ; } @@ -379,7 +379,7 @@ void helper_vmmcall(CPUX86State *env) =20 void helper_vmload(CPUX86State *env, int aflag) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); @@ -419,7 +419,7 @@ void helper_vmload(CPUX86State *env, int aflag) =20 void helper_vmsave(CPUX86State *env, int aflag) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); @@ -482,7 +482,7 @@ void helper_skinit(CPUX86State *env) =20 void helper_invlpga(CPUX86State *env, int aflag) { - X86CPU *cpu =3D x86_env_get_cpu(env); + X86CPU *cpu =3D env_archcpu(env); target_ulong addr; =20 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC()); @@ -501,7 +501,7 @@ void helper_invlpga(CPUX86State *env, int aflag) void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (likely(!(env->hflags & HF_GUEST_MASK))) { return; @@ -583,7 +583,7 @@ void helper_svm_check_intercept_param(CPUX86State *env,= uint32_t type, void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, uint32_t next_eip_addend) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ @@ -604,7 +604,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t por= t, uint32_t param, void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, retaddr, true); =20 @@ -625,7 +625,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, =20 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t int_ctl; =20 if (env->hflags & HF_INHIBIT_IRQ_MASK) { --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 15/39] target/lm32: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace lm32_env_get_cpu with env_archcpu. The combination CPU(lm32_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/lm32/cpu.h | 5 ----- target/lm32/helper.c | 19 ++++++------------- target/lm32/op_helper.c | 6 +++--- target/lm32/translate.c | 2 +- 4 files changed, 10 insertions(+), 22 deletions(-) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ad9452eb9f..7fb65fb4b6 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -195,11 +195,6 @@ struct LM32CPU { uint32_t features; }; =20 -static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) -{ - return container_of(env, LM32CPU, env); -} - #define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 8cd4840052..9f3b107474 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -58,28 +58,23 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) =20 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong addre= ss) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - - cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + cpu_breakpoint_insert(env_cpu(env), address, BP_CPU, &env->cpu_breakpoint[idx]); } =20 void lm32_breakpoint_remove(CPULM32State *env, int idx) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - if (!env->cpu_breakpoint[idx]) { return; } =20 - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); + cpu_breakpoint_remove_by_ref(env_cpu(env), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] =3D NULL; } =20 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong addre= ss, lm32_wp_t wp_type) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); int flags =3D 0; =20 switch (wp_type) { @@ -98,26 +93,24 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx,= target_ulong address, } =20 if (flags !=3D 0) { - cpu_watchpoint_insert(CPU(cpu), address, 1, flags, - &env->cpu_watchpoint[idx]); + cpu_watchpoint_insert(env_cpu(env), address, 1, flags, + &env->cpu_watchpoint[idx]); } } =20 void lm32_watchpoint_remove(CPULM32State *env, int idx) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); - if (!env->cpu_watchpoint[idx]) { return; } =20 - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); + cpu_watchpoint_remove_by_ref(env_cpu(env), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] =3D NULL; } =20 static bool check_watchpoints(CPULM32State *env) { - LM32CPU *cpu =3D lm32_env_get_cpu(env); + LM32CPU *cpu =3D env_archcpu(env); int i; =20 for (i =3D 0; i < cpu->num_watchpoints; i++) { diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index be12b11b02..d184550a7b 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -16,7 +16,7 @@ #if !defined(CONFIG_USER_ONLY) void raise_exception(CPULM32State *env, int index) { - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); @@ -29,7 +29,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t = index) =20 void HELPER(hlt)(CPULM32State *env) { - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; @@ -39,7 +39,7 @@ void HELPER(hlt)(CPULM32State *env) void HELPER(ill)(CPULM32State *env) { #ifndef CONFIG_USER_ONLY - CPUState *cs =3D CPU(lm32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); fprintf(stderr, "VM paused due to illegal instruction. " "Connect a debugger or switch to the monitor console " "to find out more.\n"); diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f0e0e7058e..b9f2f2c4a7 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1053,7 +1053,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPULM32State *env =3D cs->env_ptr; - LM32CPU *cpu =3D lm32_env_get_cpu(env); + LM32CPU *cpu =3D env_archcpu(env); struct DisasContext ctx, *dc =3D &ctx; uint32_t pc_start; uint32_t page_start; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680822; cv=none; d=zoho.com; s=zohoarc; b=hRPdqrg7eRNkSscv6koGxeFQLTdN225BdNrIVVCo3KB6/OzWWbo0lf0Hk8fMLHXLa+S2VJ/PwkARGMey4W3aMuAv3Mf/tF5PrmxdN3XjITY3g+7I4XNV6XyEMu1t/MaUfXpR91JcG0zoQXXD6LwQ66/jVdJzB8TltXwTrDWKJLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559680822; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=r2euVyUV+cLCvC2LxVd/hVa/8V0irmgvDixd4QUTeBo=; b=i7a2uXDteSvsQXmsx2SxNBMmd9kBZb8PE92lkqidiynWWBoRkCkNO9a0peblE0XMd2+P16nh9f8ozXbmjW9nX/uSraLikQK7gEw3jZ/iZo5DrZkMkJEcq0+fJhhX9sh+VUl9vt6MvB7XysmKUpJNUjj7jN3z9bwPyCK81UANQ/U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559680822152853.5537861414816; Tue, 4 Jun 2019 13:40:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:57646 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGED-0005pp-0r for importer@patchew.org; Tue, 04 Jun 2019 16:40:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8W-0001Bb-3k for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8U-0004Hr-E8 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:24 -0400 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]:46443) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8U-0004HU-89 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:22 -0400 Received: by mail-oi1-x242.google.com with SMTP id 203so16575667oid.13 for ; Tue, 04 Jun 2019 13:34:22 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. 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X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v4 16/39] target/m68k: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace m68k_env_get_cpu with env_archcpu. The combination CPU(m68k_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Acked-by: Laurent Vivier --- linux-user/m68k/target_cpu.h | 2 +- target/m68k/cpu.h | 5 ----- linux-user/m68k-sim.c | 3 +-- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/helper.c | 33 ++++++++++++--------------------- target/m68k/m68k-semi.c | 4 ++-- target/m68k/op_helper.c | 12 ++++++------ target/m68k/translate.c | 4 +--- 8 files changed, 24 insertions(+), 41 deletions(-) diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index 7a26f3c3fc..bc7446fbaf 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, targ= et_ulong newsp) =20 static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->tp_value =3D newtls; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 2e53cde076..7f3fa8d141 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,11 +163,6 @@ struct M68kCPU { CPUM68KState env; }; =20 -static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) -{ - return container_of(env, M68kCPU, env); -} - #define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index 34d332d8b1..9bc6ff3d3a 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -91,7 +91,6 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); uint32_t *args; =20 args =3D (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -159,6 +158,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 42d8d841ea..f2c33057b3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUM68KState *env) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; unsigned int n; target_siginfo_t info; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 6db93bdd81..31aacb51c6 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -168,8 +168,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) =20 void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { case M68K_CR_CACR: env->cacr =3D val; @@ -186,7 +184,7 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t re= g, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(CPU(cpu), + cpu_abort(env_cpu(env), "Unimplemented control register write 0x%x =3D 0x%x\n", reg, val); } @@ -194,8 +192,6 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t re= g, uint32_t val) =20 void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -248,14 +244,13 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_= t reg, uint32_t val) env->mmu.ttr[M68K_DTTR1] =3D val; return; } - cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x =3D 0x%= x\n", + cpu_abort(env_cpu(env), + "Unimplemented control register write 0x%x =3D 0x%x\n", reg, val); } =20 uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -292,7 +287,7 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uin= t32_t reg) case M68K_CR_DTT1: return env->mmu.ttr[M68K_DTTR1]; } - cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", reg); } =20 @@ -388,8 +383,7 @@ static void dump_address_map(CPUM68KState *env, uint32_= t root_pointer) uint32_t last_logical, last_physical; int32_t size; int last_attr =3D -1, attr =3D -1; - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); MemTxResult txres; =20 if (env->mmu.tcr & M68K_TCR_PAGE_8K) { @@ -630,8 +624,7 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, int *prot, target_ulong address, int access_type, target_ulong *page_size) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); uint32_t entry; uint32_t next; target_ulong page_mask; @@ -1175,7 +1168,7 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_= t acc) z =3D n; = \ break; = \ default: = \ - cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); = \ + cpu_abort(env_cpu(env), "Bad CC_OP %d", op); = \ } = \ } while (0) =20 @@ -1358,8 +1351,6 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t= val, uint32_t acc) #if defined(CONFIG_SOFTMMU) void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); hwaddr physical; int access_type; int prot; @@ -1384,7 +1375,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) if (ret =3D=3D 0) { addr &=3D TARGET_PAGE_MASK; physical +=3D addr & (page_size - 1); - tlb_set_page(cs, addr, physical, + tlb_set_page(env_cpu(env), addr, physical, prot, access_type & ACCESS_SUPER ? MMU_KERNEL_IDX : MMU_USER_IDX, page_size); } @@ -1392,18 +1383,18 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr= , uint32_t is_read) =20 void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D env_cpu(env); =20 switch (opmode) { case 0: /* Flush page entry if not global */ case 1: /* Flush page entry */ - tlb_flush_page(CPU(cpu), addr); + tlb_flush_page(cs, addr); break; case 2: /* Flush all except global entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 3: /* Flush all entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; } } diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 1402145c8f..6716b93b5a 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -421,7 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { @@ -454,7 +454,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting sys= call %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported semihosting syscall %d\n", nr= ); result =3D 0; } failed: diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 3d1aa23a02..ebcfe3dfdd 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -196,7 +196,7 @@ static const char *m68k_exception_name(int index) =20 static void cf_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t sp; uint32_t sr; uint32_t fmt; @@ -274,7 +274,7 @@ static inline void do_stack_frame(CPUM68KState *env, ui= nt32_t *sp, { if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) { /* all except 68000 */ - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); switch (format) { case 4: *sp -=3D 4; @@ -299,7 +299,7 @@ static inline void do_stack_frame(CPUM68KState *env, ui= nt32_t *sp, =20 static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t sp; uint32_t retaddr; uint32_t vector; @@ -507,7 +507,7 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit_restore(cs, raddr); @@ -1037,7 +1037,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int3= 2_t ub) env->cc_c =3D 0 <=3D ub ? val < 0 || val > ub : val > ub && val < 0; =20 if (val < 0 || val > ub) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); @@ -1068,7 +1068,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int= 32_t lb, int32_t ub) env->cc_c =3D lb <=3D ub ? val < lb || val > ub : val > ub && val < lb; =20 if (env->cc_c) { - CPUState *cs =3D CPU(m68k_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f0534a4ba0..2ae537461f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4777,14 +4777,12 @@ DISAS_INSN(wddata) =20 DISAS_INSN(wdebug) { - M68kCPU *cpu =3D m68k_env_get_cpu(env); - if (IS_USER(s)) { gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - cpu_abort(CPU(cpu), "WDEBUG not implemented"); + cpu_abort(env_cpu(env), "WDEBUG not implemented"); } #endif =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681673; cv=none; d=zoho.com; s=zohoarc; b=WfXknNqpd9ayAzqaD7+f6DYyEltWjscCeNeaTeGcOJjsjEpGY501nuzRY2GjqJvlYkX+teOFDOP+Xzhz5YvBDrwxdMAr0cl0HvfxmCtnsDMveiu2SVBFLq5NDGrCyxwelFTs85SS0a4OpJSG18hrFL4Pfoa3qsC9vDVIs7RgtAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559681673; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1kOvtkiHCUjgMw+1Z+kL1S4IV3z9pyM77bVL+IO/D5Y=; b=gslZUCGmNGI3KwFioHIwbnr2l+/3Dc9tyzFpBMZkGhkm3hCXb5TWkB16hPShS02Jggs+u6DJCv+iJpjq/pQSHSVOHOhjO5q1W6fGZ40rISVmWYXf45znQ8q95ohuOPGNag/bzGrHeqa3kijZNZKEu5bnZWEwLZeDNBeGH80LHzE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559681673831200.63651751301006; Tue, 4 Jun 2019 13:54:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:57860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGRx-0000oa-MB for importer@patchew.org; Tue, 04 Jun 2019 16:54:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8W-0001CN-Tg for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8V-0004Il-MI for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:24 -0400 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:37815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8V-0004IH-HN for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:23 -0400 Received: by mail-oi1-x243.google.com with SMTP id t76so1580574oih.4 for ; Tue, 04 Jun 2019 13:34:23 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=1kOvtkiHCUjgMw+1Z+kL1S4IV3z9pyM77bVL+IO/D5Y=; b=bdTDWCxtSqUpS+kyfe3TeH3lAbfUVkcPRvUG2YsYteUy2L4WkzD7KZKUfAs8ioQnpx xDm7KIkLdQR5kdbWJVyorLt10TS+cLgdoNNLJEyuKFOBvCnW2zKQ0prCuTpgT+/6HWla VzXp/T6lX686GWn736949LGtdaWd+dZvg4xukX9c/ul7kcY6kFVAGFU0C0NgcXAA0FXp 9XvzhrfTuk+IRpWhbFV9cN7K7aK55nQv1M/RizzBlHigqmZoYO2Zcu2KtFf1qIWAoh0f hlkNUQRbZlRCE4qcJ3+nopUKa7BDhnXJSynS0Rkkmbi3GRPA8VlpeRxziOIiSXd0LHmY hZ7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=1kOvtkiHCUjgMw+1Z+kL1S4IV3z9pyM77bVL+IO/D5Y=; b=nNstdii8n/mBv8+k0lHoJZwm4swLbTFNrrsMI0O7NNU7KWnNaxF686O65Wrr+nTild sN3S0Au3j75lN2+IaxvRP4VPCRd0plpYEADqhN+24YHhWTSUnCTphAunUilK42o0wtoI SeWgdIwZFtPZp5v9r+dRclE1vO8053cQXij8bFbkg7iWKoFE/EqRYVgPEoLD1LOsH8WC D5NF8y36XxVW7LFmDp/EVeR59Kbd7mkS3UjbUQbgP8Ic3HES1253r579uwbXha0u5JLL 9+x7nnnAvqqQLj6gmPXdZ3FB9ojcUL2AYp3w3O+eEkmUNccQyynwy5+0X81UQPX1wssG u2Iw== X-Gm-Message-State: APjAAAVV3mDaI5d9j8G4DoaC5LMSaEWCCbxMDm56ekyJN5Jhw/HDCT+e o7NL6uJ2OJVaBFZILoubnB2pDbPsrJJqbw== X-Google-Smtp-Source: APXvYqxWszT5UGsqqoXCbbf08VS1w6ZWxoaf7kBSPujNrbxeLd8cyPCSafWWLxoy+H5UixvwrJVA/Q== X-Received: by 2002:aca:f183:: with SMTP id p125mr5626484oih.13.1559680462440; Tue, 04 Jun 2019 13:34:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:29 -0500 Message-Id: <20190604203351.27778-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v4 17/39] target/microblaze: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace mb_env_get_cpu with env_archcpu. The combination CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_mmu_index below the include of "exec/cpu-all.h", so that the definition of env_archcpu is available. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 35 ++++++++++++++------------------ linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/mmu.c | 5 ++--- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 2 +- 5 files changed, 20 insertions(+), 26 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 6e68e00e1f..8402cc81f6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,11 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; =20 -static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) -{ - return container_of(env, MicroBlazeCPU, env); -} - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); @@ -344,21 +339,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); - - /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->sregs[SR_MSR] & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -384,4 +364,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 +static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu =3D env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->sregs[SR_MSR] & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #endif diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_l= oop.c index 076bdb9a61..a6ea71401d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUMBState *env) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index fcf86b12d5..6763421ba2 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) =20 static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); struct microblaze_mmu *mmu =3D &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t r= n) =20 void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); uint64_t tmp64; unsigned int i; qemu_log_mask(CPU_LOG_MMU, @@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, = uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v !=3D env->mmu.regs[rn]) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } env->mmu.regs[rn] =3D v; break; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index b5dbb90d05..18677ddfca 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -65,7 +65,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) =20 void helper_raise_exception(CPUMBState *env, uint32_t index) { - CPUState *cs =3D CPU(mb_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit(cs); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 885fc44b51..9ce65f3bcf 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1604,7 +1604,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMBState *env =3D cs->env_ptr; - MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); + MicroBlazeCPU *cpu =3D env_archcpu(env); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc =3D &ctx; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559680991; cv=none; d=zoho.com; s=zohoarc; b=lbrOAz6xzyeduhDvowrL9cERZzMJQDxDZ+h2s9cyGQuVHDJTBFyDs1p4ag6eupCw7f6llJ5C00jLJIFuXCdHBdN/2fBhWQeBfJ0sDVlv5wzWs2pcPkp2JzFPRYjlrGrNDe2SENqt1JISvX1Nv3R/+5xaiuS7UnSFk5uWRsh/zAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559680991; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YlNyMLJrebyqTNe9alCGCP+GtKEH43Bwhp0Gyfzj14A=; b=aASfCHGNm4EFVUVx0RQbnmSkSqU76fbiQ2SqfGOXQRXS8s8Nzynqawh07kzVe8UsOE7D1IA1TbnkNGAQrjk3kGrl6X3x/7N99ISO9+oUNkLXI0ZFxbINmCaidQYrK1rF291wPiAg3VkQU6oJOusGDBhGNPNbXjNzIrzhtPMHSZs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559680991840417.9491644139731; Tue, 4 Jun 2019 13:43:11 -0700 (PDT) Received: from localhost ([127.0.0.1]:57703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGGs-0008ON-IJ for importer@patchew.org; Tue, 04 Jun 2019 16:43:02 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8Z-0001EZ-4G for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8X-0004LJ-Ho for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:27 -0400 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:36212) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8X-0004Ko-BI for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:25 -0400 Received: by mail-oi1-x241.google.com with SMTP id w7so5244503oic.3 for ; Tue, 04 Jun 2019 13:34:25 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YlNyMLJrebyqTNe9alCGCP+GtKEH43Bwhp0Gyfzj14A=; b=yAZKSF7R+C/1FHcIIS5yKKRJNkEiLcI3uJYegZlcBYem+T0rBrKw7xkDvCcEkqVkT9 d3KRe3098cxD0t3H9nJi3rV6fGFdU+Y84ae6Vg76s5+Tw5pYegaDyeAlBeaIgUS7O0w+ QkY5G73Zz8xqmNsf7Wr2+V2rxjCtrLMJr9JJ12mC9p3L/5WvbIyw+AlBIi7Cm2SVvmga XIwNu1sAXKXqHl5jcES/BNVSuU1MMVr77NuoIIgwSkCEVm0JHThLfDrFRyczhQkZr989 yWzicY2sKn6jv6zKf7Nnt4H8GaODqzPXqYWYGh0drWcdO+xlDqiPmHEK4znYqMfrCjCA B6xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YlNyMLJrebyqTNe9alCGCP+GtKEH43Bwhp0Gyfzj14A=; b=exFxd/AOtaq2VizrEGKeK6/ODTvsQM10tLoYhqZ+xd4/qVUEIJ8BeRJ+wnbogEoQ+G MAypM3wieRKATRwOlRR7TBcuuwp7WGwW+rg8C1AQfkGYHfgKjqw2llIaHec9KV0Z5bYv hEnVE8S/npAGhPSj9OgizoBbPbXkkNV1v2fn22qfEjOwFz7xJS0ZznNsiLJBIgPe+mBK kXDSiUVh4b9nH4C832+IR4LM1vpUVQY2bgO4y3iosg335fzl7xrxmhwzZ6HPbsPo8FvW Std0XR4VEHL2SjO1cu+9FwB/UozoIchoUve9SHGksUQHynofQck3Mt2/UH2P+KsiW3hZ OWug== X-Gm-Message-State: APjAAAVdyFN/avyiUoZC8iBNf9eVvYokE6ro6eUnvBnssP1Hk0o10Pdy X1Ozo0xC1ONwops2HRjX+wEMYyxojNA6hw== X-Google-Smtp-Source: APXvYqy69HTCo8KZ7blNxFdNd0wtDo8pxm4APYG8Nk3pO7l8jqs9UElL92MAhAbOx1sXDN3edeFzbQ== X-Received: by 2002:aca:c695:: with SMTP id w143mr1113212oif.11.1559680464138; Tue, 04 Jun 2019 13:34:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:30 -0500 Message-Id: <20190604203351.27778-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v4 18/39] target/mips: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/cpu.h | 5 ----- hw/intc/mips_gic.c | 2 +- hw/mips/mips_int.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/helper.c | 15 +++++---------- target/mips/op_helper.c | 25 +++++++++++-------------- target/mips/translate.c | 3 +-- target/mips/translate_init.inc.c | 4 +--- 8 files changed, 21 insertions(+), 37 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e684572dda..cb09425476 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1071,11 +1071,6 @@ struct MIPSCPU { CPUMIPSState env; }; =20 -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - #define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list(void); diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 15e6e40f9f..8f509493ea 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp= , int pin) GIC_VP_MASK_CMP_SHF; } if (kvm_enabled()) { - kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env), + kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), pin + GIC_CPU_PIN_OFFSET, ored_level); } else { diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 5ddeb15848..f899f6ceb3 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu) qemu_irq *qi; int i; =20 - qi =3D qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env),= 8); + qi =3D qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8); for (i =3D 0; i < 8; i++) { env->irq[i] =3D qi[i]; } diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 828137cd84..ac6c6d1504 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env, target_siginfo_t= *info, =20 void cpu_loop(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; int trapnr; abi_long ret; diff --git a/target/mips/helper.c b/target/mips/helper.c index 68e44df4da..6e6a44292f 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -339,10 +339,8 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, =20 void cpu_mips_tlb_flush(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 @@ -404,7 +402,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { @@ -449,7 +447,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int exception =3D 0, error_code =3D 0; =20 if (rw =3D=3D MMU_INST_FETCH) { @@ -1394,8 +1392,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs; + CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -1421,7 +1418,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) /* 1k pages are not supported. */ mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { - cs =3D CPU(cpu); addr =3D tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1435,7 +1431,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, = int use_extra) } } if (tlb->V1) { - cs =3D CPU(cpu); addr =3D (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >=3D (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1456,7 +1451,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSStat= e *env, int error_code, uintptr_t pc) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", __func__, exception, error_code); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 39180275b5..9e2e02f858 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -350,7 +350,7 @@ static inline hwaddr do_translate_address(CPUMIPSState = *env, int rw, uintptr_t re= taddr) { hwaddr paddr; - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 paddr =3D cpu_mips_translate_address(env, address, rw); =20 @@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env,= int *tc) return env; } =20 - cs =3D CPU(mips_env_get_cpu(env)); + cs =3D env_cpu(env); vpe_idx =3D tc_idx / cs->nr_threads; *tc =3D tc_idx % cs->nr_threads; other_cs =3D qemu_get_cpu(vpe_idx); @@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target= _ulong arg1) =20 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); + MIPSCPU *cpu =3D env_archcpu(env); =20 env->active_tc.CP0_TCHalt =3D arg1 & 0x1; =20 @@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ul= ong arg1) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - MIPSCPU *other_cpu =3D mips_env_get_cpu(other); + MIPSCPU *other_cpu =3D env_archcpu(other); =20 // TODO: Halt TC / Restart (if allocated+active) TC. =20 @@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_= ulong arg1) =20 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl0 =3D arg1 & CP0SC0_MASK; tlb_flush(cs); @@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl1 =3D arg1 & CP0SC1_MASK; tlb_flush(cs); @@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->CP0_SegCtl2 =3D arg1 & CP0SC2_MASK; tlb_flush(cs); @@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) !=3D (val & env->CP0_EntryHi_ASID_mask)) { - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } =20 @@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ul= ong arg1) =20 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); uint32_t val, old; =20 old =3D env->CP0_Status; @@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env) =20 static void debug_post_eret(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function) =20 void helper_wait(CPUMIPSState *env) { - CPUState *cs =3D CPU(mips_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); diff --git a/target/mips/translate.c b/target/mips/translate.c index e37722dfff..a3cf976ab6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -30119,8 +30119,7 @@ void cpu_set_exception_base(int vp_index, target_ul= ong address) =20 void cpu_state_reset(CPUMIPSState *env) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index 1c2d017d36..6d145a905a 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -871,8 +871,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips= _def_t *def) =20 static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { - MIPSCPU *cpu =3D mips_env_get_cpu(env); - env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); =20 switch (def->mmu_type) { @@ -889,7 +887,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def= _t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(CPU(cpu), "MMU type not supported\n"); + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=QgB0Nu+t0mnNwyHYnQWVmh0yxCdODZBJfwH8/zBCUgo=; b=A3fO8J5+4OJIc7888KLjwbp2SWTw7/dH4ziVpWKdpR4hVx8U/lDOqI8KA+884s9j+a sl55Ev/nPWyEy1SE4eFW471ZBPQuTYpP2qOJs5Talcs1GyXvCVBXl5OzrHS36fEVjgOA EsyhJU3v3z9tdETt/49LfDE0tIqy+k4qbfkGYtk8zKnujdUuGLrMyUuCBEv1S/dgMVFp DHOhBbn5hz47mgy07q6KLd1igkCuVcPOr1yXVGIj2B+ex5zucAkmTwA+KMapEdZkhxUc xKobWq2uniRODN2EL6DpCg18zPpjj1rMUbhTqiqcLFtSSCTODg2+OeOD7EgQ1i6pcIka J9Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=QgB0Nu+t0mnNwyHYnQWVmh0yxCdODZBJfwH8/zBCUgo=; b=FXsq38KG8nno/KOMAkNLI55b6zI4TAC2IQ+KI7sXZ6FyuaOFu68s+Af7JvKFryrxtT 4N8V5qrcxRP236+ei5FfCOPoBhMKz2LMOmKKIQ+7DjwRMYRu+OGKZgtbNdCGWd2FHWEt 1L/bM0UfR94ueELntsb9upuxpc3xTGWIGPDNTkDiCdeta7mrRV7nmU5T5t3GfKK2S2Tp wjOBRNVFLx14q8M38Vx3LidhMMneeqQWZ3k2rLQ0oAtbb7Q5AZNHlPjdK8p073lzjTLq fqAazn8D92xGUkhijtlbMX7xr5R1jhJm+V22L16bfwvIGW+YlEwAsljJYQj3w9BbqCZ1 7s+w== X-Gm-Message-State: APjAAAVoCTIJoBzQF9cMd8OyGfinZ4WL8DkaaozBP/pFW45xyAuXXSco 2oL2uNR87z7DGKDLEP+virOiRb7llk72GQ== X-Google-Smtp-Source: APXvYqwKYk2gMzWA2+bQSbYVjvQUSOUaJdFCu5+s1NqzFR33r/18MS8Vav4HcvvOB1DT/2YO46G6xQ== X-Received: by 2002:a9d:806:: with SMTP id 6mr1889115oty.15.1559680465423; Tue, 04 Jun 2019 13:34:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:31 -0500 Message-Id: <20190604203351.27778-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 19/39] target/moxie: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace moxie_env_get_cpu with env_archcpu. The combination CPU(moxie_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/moxie/cpu.h | 5 ----- target/moxie/helper.c | 4 ++-- target/moxie/translate.c | 2 +- 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 275fb9bfbb..b9f5635e50 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -90,11 +90,6 @@ typedef struct MoxieCPU { CPUMoxieState env; } MoxieCPU; =20 -static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env) -{ - return container_of(env, MoxieCPU, env); -} - #define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); diff --git a/target/moxie/helper.c b/target/moxie/helper.c index f5c1d4181c..b1919f62b3 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -28,7 +28,7 @@ =20 void helper_raise_exception(CPUMoxieState *env, int ex) { - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D ex; /* Stash the exception type. */ @@ -65,7 +65,7 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint= 32_t b) =20 void helper_debug(CPUMoxieState *env) { - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); diff --git a/target/moxie/translate.c b/target/moxie/translate.c index c668178f2c..c87e9ec2b1 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -816,7 +816,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMoxieState *env =3D cs->env_ptr; - MoxieCPU *cpu =3D moxie_env_get_cpu(env); + MoxieCPU *cpu =3D env_archcpu(env); DisasContext ctx; target_ulong pc_start; int num_insns; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681147; cv=none; d=zoho.com; s=zohoarc; b=GXsUK2XTvAmzViYr8PzuoGlQWFcc9ai7i0OX3e0kIkqJRY8PUwBqn/XjORi/Iweu5BruNS6tp8tzF06YceJkYqAq0oAx7z7wLeZxBDnDyrTHp3aVN+3yWZQhKRrswpsXnMb8J6xhxBpSDeKth07QzLfMPK9GlYh6UJcKQw/Y8pA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559681147; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pnOBaWOuZI6RQh/0O1nDjt3Ap0L8f++M/zWc9l2w1jE=; b=g/JLBYZxgAG10zJYzbh4NCngc7M+0L56F/ITcl9To7LjqIbGzhQ041VGVL4KHU96GGbDFbSDRnzB4Pnd92cgAmEF12NyNyDJzUe+i0jnkhkXQDf09qXqRJnrLMmM6iFIbFi+b/L9BRL+Zo+0r1z1H4Lor3xyWSezV2jxAw79w2A= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559681147469907.6426754044156; Tue, 4 Jun 2019 13:45:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:57745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGJR-0002GZ-CF for importer@patchew.org; Tue, 04 Jun 2019 16:45:41 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8b-0001Ix-4V for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8a-0004No-2n for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:29 -0400 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:43481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8Z-0004ND-UP for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:28 -0400 Received: by mail-oi1-x244.google.com with SMTP id w79so7536730oif.10 for ; Tue, 04 Jun 2019 13:34:27 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=pnOBaWOuZI6RQh/0O1nDjt3Ap0L8f++M/zWc9l2w1jE=; b=ZVThC9fvSeJE7W+JVmKtAVtQVEboSApjL1uni4bSucp1nj3W9UkCrr5rPcgGItZBiz DNOp+3EDUqzJNhvzA9nLuI2XX307HfS/+haXIPvZps1//uc/3TbHts6rLgIJAYyW4+SI pdk5kyDb4T6wTcZLrmJmeCi8qOhFPGTkNuItIdK/M9NEZQLHmQ7apLqaiZv2joFw3oVl XWnpmYNbetfWdBgzCOmWygJOyC0UU2eMtlRiHBgwLU+Ulcqyls9KekelSOHkV+2uzCMn V0nCLirOYBceBekCmay0gmA4iCyzA/4PttrXGn1zfgmn6CcUudHTFBnZt1B8JwNE0Imd 4VDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=pnOBaWOuZI6RQh/0O1nDjt3Ap0L8f++M/zWc9l2w1jE=; b=qEviuKEW4rhj4RwDRTZ8EZHahIyXNJ6h8xSRq4VCw+Zcvs/9YDA8iklff0/p6x+/Uh VHL5+Dawg2NLqX22kSmVoKwynrVLJNdwDkhoeVkxI1ZiwbDLfzxk8BkTDzlgUfjIKuEd cukKBshHAiflJ15nZl64WGIc40cMMdMsdxA5JsYVf3S4hLbraILMf7HHUdF0+x87rM77 PVZAfwLYkg2FPAhy4G7sgxu6tYcoXouxgW4BHTULXSYxZwB0SfwjI1+snuBaIX2QUW2X sH6GugAbh8UWzxP/8LvNra247w8Lukg84hNQNGwlsoGhZTaua57zGI3tg3WgAq8KMFig kUfg== X-Gm-Message-State: APjAAAWYgT08Lt/ibHCPwVfv5ZS60yvP82DUzukx9fkNN5edle0za+5C qUTEOCjEWfZVKsUiiuojmFOabHmE//yysA== X-Google-Smtp-Source: APXvYqwfPWqvLW5gLaRRqHjn4qvuxgAWLFWGKRjcSUSaRak51rMY69SstMDgzR2VnnE/1FEIAya2Jg== X-Received: by 2002:aca:5b57:: with SMTP id p84mr5550599oib.4.1559680466947; Tue, 04 Jun 2019 13:34:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:32 -0500 Message-Id: <20190604203351.27778-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH v4 20/39] target/nios2: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace nios2_env_get_cpu with env_archcpu. The combination CPU(nios2_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 ----- hw/nios2/cpu_pic.c | 5 +---- target/nios2/mmu.c | 10 +++++----- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ae6cf1b4d1..9490ba83e4 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -194,11 +194,6 @@ typedef struct Nios2CPU { uint32_t fast_tlb_miss_addr; } Nios2CPU; =20 -static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env) -{ - return NIOS2_CPU(container_of(env, Nios2CPU, env)); -} - #define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c index 6bccce2f32..9e39955bd1 100644 --- a/hw/nios2/cpu_pic.c +++ b/hw/nios2/cpu_pic.c @@ -54,12 +54,9 @@ static void nios2_pic_cpu_handler(void *opaque, int irq,= int level) =20 void nios2_check_interrupts(CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - if (env->irq_pending) { env->irq_pending =3D 0; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); } } =20 diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 53ed6413b4..9a0bafe786 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -61,7 +61,7 @@ unsigned int mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, target_ulong vaddr, int rw, int mmu_idx) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int vpn =3D vaddr >> 12; =20 @@ -103,7 +103,7 @@ unsigned int mmu_translate(CPUNios2State *env, static void mmu_flush_pid(CPUNios2State *env, uint32_t pid) { CPUState *cs =3D env_cpu(env); - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int idx; MMU_LOG(qemu_log("TLB Flush PID %d\n", pid)); =20 @@ -127,7 +127,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t = pid) void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) { CPUState *cs =3D env_cpu(env); - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); =20 MMU_LOG(qemu_log("mmu_write %08X =3D %08X\n", rn, v)); =20 @@ -244,7 +244,7 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_= t v) =20 void mmu_init(CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); Nios2MMU *mmu =3D &env->mmu; =20 MMU_LOG(qemu_log("mmu_init\n")); @@ -255,7 +255,7 @@ void mmu_init(CPUNios2State *env) =20 void dump_mmu(CPUNios2State *env) { - Nios2CPU *cpu =3D nios2_env_get_cpu(env); + Nios2CPU *cpu =3D env_archcpu(env); int i; =20 qemu_printf("MMU: ways %d, entries %d, pid bits %d\n", --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=tSiI4G5J5ouiA/gsVkWkdNcl9+jS6pdNMYuFN+MKcoA=; b=jiF+zYDfziQIWsSLbY3qDc8I+sLKQVvgdJtiOLtlpnKPGRm1QzKc9pMKi1Y4LqCC1e b3PxHsP33RiaC33MXSMSD58AmDey5CU2u+8kOaZ1D8Y3Ds/8+CsSDC+yPF/LiwppZ194 x6BZNurk2Vzyfs3BIf+ArQSTjkGkfuJ1WZhbdZWUclCZf2QeSHNdGjxRP125zFMDeUsx r+4P8uZB44u/THcDynkL9XYeU0Z1knvS4oSQdx9ijnmBrv3OkBTjNq3RrbLkKXLVHxxJ l72XRQNAG3kYPVOfOSrdx3DShwD7N8ZDesZpgsf/9ICiCUxpvV/EhAPRpGCI+WFiXXch gSeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=tSiI4G5J5ouiA/gsVkWkdNcl9+jS6pdNMYuFN+MKcoA=; b=saHF9L5Xr+REGykqdw/dBfeuN4oD6pqF93mbxY2UAsErBqilzqDdb+g3rIGUuFqIC+ Ff2/Tg2iHZySWkTqp/IL1/mq1oo4Ylp3kOAv2HqLRPzVUcgIcBdpdYgEHSInnNqqXFNg vtaCK8IS9/s/hbD2Wwie+FWj5p3QaAtuU7e10HI9Rb+zagswnQrlOtRsEAapPyW1maGa fHrHS5dspVAd+gQqrBe+JrgLYJYKg63g9dOFRpqZy03IwOjUzN3Keb79Ddo790jd5dA6 emSYdCn+r0uN0gOapiSc9wOVNaP80IILa5475ucyfSjQJfbY2ASTB1cCr/F16dh93EFU oPaw== X-Gm-Message-State: APjAAAUrp3NGBA8g73BBz4+6vLNhtVjmtrhRTHHb6fnsUY60eKlI6/z3 6V2DPQRg5uL7d6umXB9IgR2dJhsV6psa0g== X-Google-Smtp-Source: APXvYqyry3ccnGol7smOk24OC2BSLzUQ/KENwsFf4iV3iSFSRjf14JlsSKCkVhV8Zk5+56N4N0VIcg== X-Received: by 2002:aca:5f8b:: with SMTP id t133mr5736686oib.85.1559680468104; Tue, 04 Jun 2019 13:34:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:33 -0500 Message-Id: <20190604203351.27778-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v4 21/39] target/openrisc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace openrisc_env_get_cpu with env_archcpu. The combination CPU(openrisc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 5 ----- linux-user/openrisc/cpu_loop.c | 2 +- target/openrisc/exception_helper.c | 5 ++--- target/openrisc/sys_helper.c | 8 ++++---- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 50f79d540b..9e46ac5266 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,11 +317,6 @@ typedef struct OpenRISCCPU { =20 } OpenRISCCPU; =20 -static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) -{ - return container_of(env, OpenRISCCPU, env); -} - #define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(void); diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f496e4b48a..4b8165b261 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUOpenRISCState *env) { - CPUState *cs =3D CPU(openrisc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception= _helper.c index 0797cc9d38..d02a1cf0aa 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -25,15 +25,14 @@ =20 void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); + OpenRISCCPU *cpu =3D env_archcpu(env); =20 raise_exception(cpu, excp); } =20 static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc) { - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_RANGE; cpu_loop_exit_restore(cs, pc); diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 05f66c455b..8f11cb8202 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -30,8 +30,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong r= b) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + OpenRISCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong mr; int idx; =20 @@ -194,8 +194,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, target_ulong spr) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu =3D openrisc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + OpenRISCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); int idx; =20 switch (spr) { --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=lf5icV2lVCkIWEYrBl+I62jKJuQAE3cwX0XZzw8SlLo=; b=FFkovk0R4KCwBUpWOPHE0x9s8PQS0yNl/4hv/bdFGwUZVeWbBQ1nIrAlwyW6E3ajZl 8Qq+iJVZBUHwUIXH1ZclBIMwsXlXfiQPcjvANpABGq8JyqcuoJmHO1+HeQw87W+eaZVK 6dmyBRNVTLIBeI5kZfFaSQnvq3AwXt4FfN5iSOuBdRTChlkQjolMib9v9SDFYyi3Hm/m ATwGwTbdFGDCliTgDVoSSax484QJZ4cu2uWaOY7Ioz7q12+hi3D0njt21W4th0sdtved lhAXbBEHV+v3chg7483HBhFId2pkrhOp29YHE8mnGvzJyUc60Xo2nloonHwNxySa4YnR sJ/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lf5icV2lVCkIWEYrBl+I62jKJuQAE3cwX0XZzw8SlLo=; b=bbhm9A0KEcYaCNrwuEMh1TCnhjNNuttlVgyUUmGRJ90ag+cCIKCuHmg/WwvI38LBe5 JZGpATibAM8SrvbZpSErIihATeVSU/+usjXq3Q308oV6pmDPFmvedzFvd+pPQSwJDoZC 7+JuHbJrV4GmpxneIyHiL3PeUIcAPrOaHpkYirOyl+TZySQ/iESBPamUIFzwu0e9f/QJ qdsPX3HZVBExb6H7yIBp0HklNdJTBJ4Vd4esFZ0R0dj7aSvfP9mVfmekTmIGsbPSW/Mh VRvAjNWQqi866BbJ4yhq5RYhuLqGzsqnebQdOJc/bbPWpmsKNP7hxXjUh+198yzUPPBT E+Ig== X-Gm-Message-State: APjAAAVJPXlKp1HS4w9mcTWL/tKN9LUvGjo6iojsdH7AYcTsvqyCMwT/ Kgbrencxonurkydo+uNEFGtOQosUSk5jig== X-Google-Smtp-Source: APXvYqwfyBlKR3jjzBa6cL9DTaV2G3MDanfoffKG38ITzmAbc5pUiILg3E1+q34xtTsoQvu/DWqI/Q== X-Received: by 2002:a9d:3bb4:: with SMTP id k49mr6446753otc.332.1559680469817; Tue, 04 Jun 2019 13:34:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:34 -0500 Message-Id: <20190604203351.27778-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 22/39] target/ppc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace ppc_env_get_cpu with env_archcpu. The combination CPU(ppc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 7 +- target/ppc/helper_regs.h | 4 +- hw/ppc/ppc.c | 18 ++--- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc_booke.c | 4 +- linux-user/ppc/cpu_loop.c | 2 +- target/ppc/excp_helper.c | 14 ++-- target/ppc/fpu_helper.c | 14 ++-- target/ppc/kvm.c | 5 +- target/ppc/misc_helper.c | 22 ++---- target/ppc/mmu-hash64.c | 14 ++-- target/ppc/mmu_helper.c | 115 +++++++++++++------------------- target/ppc/translate_init.inc.c | 85 ++++++++++++----------- 13 files changed, 134 insertions(+), 172 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ec92a8e7af..73ef868a7b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1203,11 +1203,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; =20 -static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) -{ - return container_of(env, PowerPCCPU, env); -} - #define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); @@ -2450,7 +2445,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *= env, ppcmas_tlb_t *tlbm) } } =20 - cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); + cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id); return 0; } =20 diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 922da76c6c..85dfe7687f 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -116,7 +116,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, { int excp; #if !defined(CONFIG_USER_ONLY) - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); #endif =20 excp =3D 0; @@ -175,7 +175,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, #if !defined(CONFIG_USER_ONLY) static inline void check_tlb_flush(CPUPPCState *env, bool global) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Handle global flushes first */ if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index ad20584f26..debcdab993 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -385,7 +385,7 @@ void ppc40x_system_reset(PowerPCCPU *cpu) =20 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 switch ((val >> 28) & 0x3) { case 0x0: @@ -785,7 +785,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env) =20 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); ppc_tb_t *tb_env =3D env->tb_env; uint64_t hdecr; @@ -923,7 +923,7 @@ static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu,= target_ulong decr, =20 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); int nr_bits =3D 32; =20 @@ -955,7 +955,7 @@ static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu= , target_ulong hdecr, =20 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, @@ -980,7 +980,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_= t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { CPUPPCState *env =3D opaque; - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; =20 tb_env->tb_freq =3D freq; @@ -1095,7 +1095,7 @@ const VMStateDescription vmstate_ppc_timebase =3D { /* Set up (once) timebase frequency (in Hz) */ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env; =20 tb_env =3D g_malloc0(sizeof(ppc_tb_t)); @@ -1165,7 +1165,7 @@ static void cpu_4xx_fit_cb (void *opaque) uint64_t now, next; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -1235,7 +1235,7 @@ static void cpu_4xx_pit_cb (void *opaque) ppc40x_timer_t *ppc40x_timer; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; env->spr[SPR_40x_TSR] |=3D 1 << 27; @@ -1261,7 +1261,7 @@ static void cpu_4xx_wdt_cb (void *opaque) uint64_t now, next; =20 env =3D opaque; - cpu =3D ppc_env_get_cpu(env); + cpu =3D env_archcpu(env); tb_env =3D env->tb_env; ppc40x_timer =3D tb_env->opaque; now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3ae7f6d4df..018dcca888 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -49,7 +49,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); ram_addr_t bdloc; int i, n; =20 diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 4f11e00a17..323413e074 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -249,7 +249,7 @@ static void booke_wdt_cb(void *opaque) =20 void store_booke_tsr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; booke_timer_t *booke_timer =3D tb_env->opaque; =20 @@ -277,7 +277,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val) =20 void store_booke_tcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_tb_t *tb_env =3D env->tb_env; booke_timer_t *booke_timer =3D tb_env->opaque; =20 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 801f5ace29..24dfdba854 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -67,7 +67,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t= val) =20 void cpu_loop(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; int trapnr; target_ulong ret; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index ec2c177091..50b004d00d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -49,7 +49,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) =20 static void ppc_hw_interrupt(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D POWERPC_EXCP_NONE; env->error_code =3D 0; @@ -792,7 +792,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) =20 static void ppc_hw_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); bool async_deliver; =20 /* External reset */ @@ -931,7 +931,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) * It generally means a discrepancy between the wakup conditions i= n the * processor has_work implementation and the logic in this functio= n. */ - cpu_abort(CPU(ppc_env_get_cpu(env)), + cpu_abort(env_cpu(env), "Wakeup from PM state but interrupt Undelivered"); } } @@ -974,7 +974,7 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong = msr) void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, uint32_t error_code, uintptr_t raddr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D exception; env->error_code =3D error_code; @@ -1015,7 +1015,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong = val) uint32_t excp =3D hreg_store_msr(env, val, 0); =20 if (excp !=3D 0) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); cpu_interrupt_exittb(cs); raise_exception(env, excp); } @@ -1026,7 +1026,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) { CPUState *cs; =20 - cs =3D CPU(ppc_env_get_cpu(env)); + cs =3D env_cpu(env); cs->halted =3D 1; =20 /* @@ -1043,7 +1043,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) =20 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong= msr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* MSR:POW cannot be set by any form of rfi */ msr &=3D ~(1ULL << MSR_POW); diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 0b7308f539..ffbd19afa1 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -271,7 +271,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, boo= l set_fpcc, env->fpscr |=3D FP_FX; /* We must update the target FPR before raising the exception */ if (fpscr_ve !=3D 0) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D POWERPC_EXCP_PROGRAM; env->error_code =3D POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; @@ -315,7 +315,7 @@ static inline void float_zero_divide_excp(CPUPPCState *= env, uintptr_t raddr) =20 static inline void float_overflow_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_OX; /* Update the floating-point exception summary */ @@ -335,7 +335,7 @@ static inline void float_overflow_excp(CPUPPCState *env) =20 static inline void float_underflow_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_UX; /* Update the floating-point exception summary */ @@ -352,7 +352,7 @@ static inline void float_underflow_excp(CPUPPCState *en= v) =20 static inline void float_inexact_excp(CPUPPCState *env) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->fpscr |=3D 1 << FPSCR_FI; env->fpscr |=3D 1 << FPSCR_XX; @@ -442,7 +442,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) =20 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int prev; =20 prev =3D (env->fpscr >> bit) & 1; @@ -574,7 +574,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) =20 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong prev, new; int i; =20 @@ -612,7 +612,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32= _t mask) =20 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int status =3D get_float_exception_flags(&env->fp_status); bool inexact_happened =3D false; =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 3bf0a46c33..d4107dd70d 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1991,9 +1991,8 @@ static int kvmppc_get_dec_bits(void) } =20 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvin= fo) - { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); +{ + CPUState *cs =3D env_cpu(env); =20 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 0a81e98ee9..49a8a02363 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -81,28 +81,24 @@ void helper_msr_facility_check(CPUPPCState *env, uint32= _t bit, =20 void helper_store_sdr1(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (env->spr[SPR_SDR1] !=3D val) { ppc_store_sdr1(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 #if defined(TARGET_PPC64) void helper_store_ptcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (env->spr[SPR_PTCR] !=3D val) { ppc_store_ptcr(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void helper_store_pcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 env->spr[SPR_PCR] =3D value & pcc->pcr_mask; @@ -111,16 +107,12 @@ void helper_store_pcr(CPUPPCState *env, target_ulong = value) =20 void helper_store_pidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[SPR_BOOKS_PID] =3D val; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_store_lpidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[SPR_LPIDR] =3D val; =20 /* @@ -129,7 +121,7 @@ void helper_store_lpidr(CPUPPCState *env, target_ulong = val) * potentially access and cache entries for the current LPID as * well. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_store_hid0_601(CPUPPCState *env, target_ulong val) @@ -151,12 +143,10 @@ void helper_store_hid0_601(CPUPPCState *env, target_u= long val) =20 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong val= ue) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (likely(env->pb[num] !=3D value)) { env->pb[num] =3D value; /* Should be optimized */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 7899eb2918..da8966ccf5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -96,7 +96,7 @@ void dump_slb(PowerPCCPU *cpu) =20 void helper_slbia(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int n; =20 /* XXX: Warning: slbia never invalidates the first segment */ @@ -118,7 +118,7 @@ void helper_slbia(CPUPPCState *env) static void __helper_slbie(CPUPPCState *env, target_ulong addr, target_ulong global) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc_slb_t *slb; =20 slb =3D slb_lookup(cpu, addr); @@ -251,7 +251,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ul= ong rb, =20 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, @@ -261,7 +261,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb= , target_ulong rs) =20 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { @@ -273,7 +273,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, tar= get_ulong rb) =20 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { @@ -285,7 +285,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, tar= get_ulong rb) =20 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong rt =3D 0; =20 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { @@ -1163,7 +1163,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) =20 void helper_store_lpcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); =20 ppc_store_lpcr(cpu, val); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e3149e4d3f..261a8fe707 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -239,7 +239,6 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, t= arget_ulong eaddr, =20 static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; =20 @@ -253,7 +252,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCStat= e *env) tlb =3D &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -261,7 +260,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCSt= ate *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); ppc6xx_tlb_t *tlb; int way, nr; =20 @@ -474,7 +473,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t = *ctx, static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int type) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; target_ulong vsid; int ds, pr, target_page_bits; @@ -670,7 +669,6 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_u= long address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; =20 @@ -678,7 +676,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCStat= e *env) tlb =3D &env->tlb.tlbe[i]; tlb->prot &=3D ~PAGE_VALID; } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, @@ -749,11 +747,10 @@ static int mmu40x_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, =20 void store_40x_sler(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - /* XXX: TO BE FIXED */ if (val !=3D 0x00000000) { - cpu_abort(CPU(cpu), "Little-endian regions are not supported by no= w\n"); + cpu_abort(env_cpu(env), + "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] =3D val; } @@ -863,7 +860,6 @@ static int mmubooke_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb =3D env->tlb.tlbm; @@ -880,7 +876,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int fl= ags, tlb +=3D booke206_tlb_size(env, i); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1275,7 +1271,7 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int ty= pe) =20 static void mmu6xx_dump_mmu(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; @@ -1347,13 +1343,13 @@ void dump_mmu(CPUPPCState *env) case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: - dump_slb(ppc_env_get_cpu(env)); + dump_slb(env_archcpu(env)); break; case POWERPC_MMU_3_00: - if (ppc64_v3_radix(ppc_env_get_cpu(env))) { + if (ppc64_v3_radix(env_archcpu(env))) { /* TODO - Unsupported */ } else { - dump_slb(ppc_env_get_cpu(env)); + dump_slb(env_archcpu(env)); break; } #endif @@ -1419,7 +1415,6 @@ static int get_physical_address_wtlb( target_ulong eaddr, int rw, int access_type, int mmu_idx) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int ret =3D -1; bool real_mode =3D (access_type =3D=3D ACCESS_CODE && msr_ir =3D=3D 0) || (access_type !=3D ACCESS_CODE && msr_dr =3D=3D 0); @@ -1460,18 +1455,18 @@ static int get_physical_address_wtlb( break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret =3D check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(CPU(cpu), + cpu_abort(env_cpu(env), "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); + cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n"); return -1; } =20 @@ -1583,7 +1578,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState = *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); PowerPCCPU *cpu =3D POWERPC_CPU(cs); mmu_ctx_t ctx; int access_type; @@ -1815,7 +1810,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,= target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong base, end, page; =20 base =3D BATu & ~0x0001FFFF; @@ -1847,7 +1842,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr= , target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); #endif =20 dump_store_bat(env, 'I', 0, nr, value); @@ -1868,7 +1863,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr= , target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->IBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1883,7 +1878,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr= , target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); #endif =20 dump_store_bat(env, 'D', 0, nr, value); @@ -1904,7 +1899,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr= , target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->DBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1919,7 +1914,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t= nr, target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int do_inval; #endif =20 @@ -1953,7 +1948,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t= nr, target_ulong value) } #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -1964,7 +1959,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t= nr, target_ulong value) #if !defined(FLUSH_ALL_TLBS) target_ulong mask; #else - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); int do_inval; #endif =20 @@ -1993,7 +1988,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t= nr, target_ulong value) env->DBAT[1][nr] =3D value; #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -2003,12 +1998,10 @@ void helper_store_601_batl(CPUPPCState *env, uint32= _t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { env->tlb_need_flush =3D 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } else #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { @@ -2021,14 +2014,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -2036,11 +2029,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_32B: case POWERPC_MMU_601: env->tlb_need_flush =3D 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model); + cpu_abort(env_cpu(env), "Unknown MMU model %x\n", env->mmu_model); break; } } @@ -2091,7 +2084,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_= ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!cpu->vhyp); #if defined(TARGET_PPC64) @@ -2118,7 +2111,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong va= lue) #if defined(TARGET_PPC64) void ppc_store_ptcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); target_ulong ptcr_mask =3D PTCR_PATB | PTCR_PATS; target_ulong patbsize =3D value & PTCR_PATS; =20 @@ -2163,7 +2156,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + PowerPCCPU *cpu =3D env_archcpu(env); uint64_t esid, vsid; =20 /* ESID =3D srnum */ @@ -2190,7 +2183,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) page =3D (16 << 20) * srnum; end =3D page + (16 << 20); for (; page !=3D end; page +=3D TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), page); + tlb_flush_page(env_cpu(env), page); } } #else @@ -2212,12 +2205,10 @@ void helper_tlbie(CPUPPCState *env, target_ulong ad= dr) =20 void helper_tlbiva(CPUPPCState *env, target_ulong addr) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - /* tlbiva instruction only exists on BookE */ assert(env->mmu_model =3D=3D POWERPC_MMU_BOOKE); /* XXX: TODO */ - cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "BookE MMU model is not implemented\n"); } =20 /* Software driven TLBs management */ @@ -2433,8 +2424,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, ta= rget_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); ppcemb_tlb_t *tlb; target_ulong page, end; =20 @@ -2529,7 +2519,6 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, targe= t_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2565,13 +2554,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t wo= rd, target_ulong entry, } tlb->PID =3D env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } break; case 1: RPN =3D value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN !=3D RPN) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } tlb->RPN =3D RPN; break; @@ -2665,7 +2654,6 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, targe= t_ulong address) =20 static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg =3D 0; int esel =3D (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_= SHIFT; int ea =3D (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2675,7 +2663,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *en= v) tlbncfg =3D env->spr[SPR_BOOKE_TLB0CFG + tlb]; =20 if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(CPU(cpu), "we don't support HES yet\n"); + cpu_abort(env_cpu(env), "we don't support HES yet\n"); } =20 return booke206_get_tlbm(env, tlb, ea, esel); @@ -2683,40 +2671,33 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *= env) =20 void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - env->spr[pidn] =3D pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke_set_eplc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPLC] =3D val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_LOAD); } void helper_booke_set_epsc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPSC] =3D val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_STORE); } =20 static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - if (booke206_tlb_to_page_size(env, tlb) =3D=3D TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(env_cpu(env), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 void helper_booke206_tlbwe(CPUPPCState *env) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2770,7 +2751,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } =20 if (msr_gs) { - cpu_abort(CPU(cpu), "missing HV implementation\n"); + cpu_abort(env_cpu(env), "missing HV implementation\n"); } =20 if (tlb->mas1 & MAS1_VALID) { @@ -2968,7 +2949,6 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target= _ulong address) =20 void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int i, j; int tid =3D (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb =3D env->tlb.tlbm; @@ -2985,12 +2965,11 @@ void helper_booke206_tlbilx1(CPUPPCState *env, targ= et_ulong address) } tlb +=3D booke206_tlb_size(env, i); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid =3D (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -3026,7 +3005,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target= _ulong address) tlb->mas1 &=3D ~MAS1_VALID; } } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index ad5e14b16f..d161e95fb2 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -3432,7 +3432,7 @@ static void init_proc_401(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3486,7 +3486,7 @@ static void init_proc_401x2(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3538,7 +3538,7 @@ static void init_proc_401x3(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3597,7 +3597,7 @@ static void init_proc_IOP480(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3648,7 +3648,7 @@ static void init_proc_403(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3714,7 +3714,7 @@ static void init_proc_403GCX(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3780,7 +3780,7 @@ static void init_proc_405(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3878,7 +3878,7 @@ static void init_proc_440EP(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4186,7 +4186,7 @@ static void init_proc_440x5(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size =3D 32; env->icache_line_size =3D 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); =20 SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4392,7 +4392,7 @@ static void init_proc_G2(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) @@ -4472,7 +4472,7 @@ static void init_proc_G2LE(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) @@ -4727,7 +4727,7 @@ static void init_proc_e300(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) @@ -4805,7 +4805,6 @@ enum fsl_e500_version { =20 static void init_proc_e500(CPUPPCState *env, int version) { - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask =3D 0xFFFF0000ULL; @@ -4877,7 +4876,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) tlbncfg[1] =3D 0x40028040; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } #endif @@ -4902,7 +4901,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) l1cfg1 |=3D 0x0B83820; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); @@ -5018,7 +5017,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) =20 init_excp_e200(env, ivpr_mask); /* Allocate hardware IRQ controller */ - ppce500_irq_init(ppc_env_get_cpu(env)); + ppce500_irq_init(env_archcpu(env)); } =20 static void init_proc_e500v1(CPUPPCState *env) @@ -5291,7 +5290,7 @@ static void init_proc_601(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 64; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) @@ -5396,7 +5395,7 @@ static void init_proc_602(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) @@ -5466,7 +5465,7 @@ static void init_proc_603(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) @@ -5533,7 +5532,7 @@ static void init_proc_603E(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) @@ -5594,7 +5593,7 @@ static void init_proc_604(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) @@ -5678,7 +5677,7 @@ static void init_proc_604E(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) @@ -5749,7 +5748,7 @@ static void init_proc_740(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) @@ -5829,7 +5828,7 @@ static void init_proc_750(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) @@ -5993,7 +5992,7 @@ static void init_proc_750cl(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) @@ -6115,7 +6114,7 @@ static void init_proc_750cx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) @@ -6203,7 +6202,7 @@ static void init_proc_750fx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) @@ -6291,7 +6290,7 @@ static void init_proc_750gx(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) @@ -6370,7 +6369,7 @@ static void init_proc_745(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) @@ -6457,7 +6456,7 @@ static void init_proc_755(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) @@ -6527,7 +6526,7 @@ static void init_proc_7400(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) @@ -6612,7 +6611,7 @@ static void init_proc_7410(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) @@ -6723,7 +6722,7 @@ static void init_proc_7440(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) @@ -6857,7 +6856,7 @@ static void init_proc_7450(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) @@ -6994,7 +6993,7 @@ static void init_proc_7445(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) @@ -7133,7 +7132,7 @@ static void init_proc_7455(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) @@ -7296,7 +7295,7 @@ static void init_proc_7457(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) @@ -7434,7 +7433,7 @@ static void init_proc_e600(CPUPPCState *env) env->dcache_line_size =3D 32; env->icache_line_size =3D 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) @@ -8298,7 +8297,7 @@ static void init_proc_970(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) @@ -8372,7 +8371,7 @@ static void init_proc_power5plus(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } =20 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) @@ -8487,7 +8486,7 @@ static void init_proc_POWER7(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER7(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8639,7 +8638,7 @@ static void init_proc_POWER8(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER8(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8838,7 +8837,7 @@ static void init_proc_POWER9(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER9(env); - ppcPOWER9_irq_init(ppc_env_get_cpu(env)); + ppcPOWER9_irq_init(env_archcpu(env)); } =20 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH v4 23/39] target/riscv: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 ----- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu_helper.c | 10 ++++------ target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 7 +++---- 5 files changed, 14 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ab038bac3..29a1e08f03 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -221,11 +221,6 @@ typedef struct RISCVCPU { } cfg; } RISCVCPU; =20 -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) !=3D 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ =20 void cpu_loop(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c577a262b8..8b6754b917 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -89,14 +89,12 @@ struct CpuAsyncInfo { static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, run_on_cpu_data data) { - CPURISCVState *env =3D &RISCV_CPU(target_cpu_state)->env; - RISCVCPU *cpu =3D riscv_env_get_cpu(env); struct CpuAsyncInfo *info =3D (struct CpuAsyncInfo *) data.host_ptr; =20 if (info->new_mip) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } =20 g_free(info); @@ -212,7 +210,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } } =20 - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits; target_ulong mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs =3D (addr >> (va_bits - 1)) & mask; @@ -341,7 +339,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int page_fault_exceptions =3D (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9e2910643..c67d29e206 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, ta= rget_ulong val) =20 /* flush translation cache */ if (val !=3D env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } =20 env->misa =3D val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno= , target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); + RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return 0; } if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr =3D val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -724,7 +724,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) return -1; } else { if((val ^ env->satp) & SATP_ASID) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } env->satp =3D val; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb35f..331cc36232 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index =3D exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) =20 void helper_wfi(CPURISCVState *env) { - CPUState *cs =3D CPU(riscv_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && @@ -143,8 +143,7 @@ void helper_wfi(CPURISCVState *env) =20 void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu =3D riscv_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && env->priv_ver >=3D PRIV_VERSION_1_10_0 && --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681450; 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X-Received-From: 2607:f8b0:4864:20::236 Subject: [Qemu-devel] [PATCH v4 24/39] target/s390x: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace s390_env_get_cpu with env_archcpu. The combination CPU(s390_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 5 ---- linux-user/s390x/cpu_loop.c | 2 +- target/s390x/cc_helper.c | 5 ++-- target/s390x/diag.c | 2 +- target/s390x/excp_helper.c | 6 ++--- target/s390x/fpu_helper.c | 4 +-- target/s390x/helper.c | 7 +++--- target/s390x/int_helper.c | 3 +-- target/s390x/interrupt.c | 6 ++--- target/s390x/mem_helper.c | 28 ++++++++------------- target/s390x/misc_helper.c | 50 ++++++++++++++++++------------------- target/s390x/mmu_helper.c | 8 +++--- target/s390x/sigp.c | 4 +-- 13 files changed, 56 insertions(+), 74 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 9cdd831a77..eefed6f509 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,11 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; =20 -static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) -{ - return container_of(env, S390CPU, env); -} - #define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index b8bd1c956c..8211022ceb 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -26,7 +26,7 @@ =20 void cpu_loop(CPUS390XState *env) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, n, sig; target_siginfo_t info; target_ulong addr; diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index a00294f183..cf68792733 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -419,7 +419,6 @@ static uint32_t cc_calc_vc(uint64_t low, uint64_t high) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { - S390CPU *cpu =3D s390_env_get_cpu(env); uint32_t r =3D 0; =20 switch (cc_op) { @@ -543,7 +542,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, break; =20 default: - cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(env_cpu(env), "Unknown CC operation: %s\n", cc_name(cc_o= p)); } =20 HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx =3D %d\n", __func__, @@ -567,7 +566,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t c= c_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(CPU(s390_env_get_cpu(env))); + cpu_loop_exit(env_cpu(env)); } =20 void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target/s390x/diag.c b/target/s390x/diag.c index aafa740f61..65eabf0461 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -55,7 +55,7 @@ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint= 64_t r3) =20 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr= _t ra) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t addr =3D env->regs[r1]; uint64_t subcode =3D env->regs[r3]; IplParameterBlock *iplb; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 3a467b72c5..b718760175 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -36,7 +36,7 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t= code, int ilen, uintptr_t ra) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, ra, true); qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", @@ -51,7 +51,7 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState = *env, uint32_t dxc, g_assert(dxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(CPU(s390_env_get_cpu(env))->as, + stl_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, data_exc_code), dxc); #endif =20 @@ -282,7 +282,7 @@ static void do_svc_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { QEMUS390FLICState *flic =3D QEMU_S390_FLIC(s390_get_flic()); - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); uint64_t mask, addr; uint16_t cpu_addr; LowCore *lowcore; diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 1be68bafea..906fa8ce99 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -114,8 +114,6 @@ static void handle_exceptions(CPUS390XState *env, bool = XxC, uintptr_t retaddr) =20 static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) { - S390CPU *cpu =3D s390_env_get_cpu(env); - switch (float_compare) { case float_relation_equal: return 0; @@ -126,7 +124,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, = int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(CPU(cpu), "unknown return value for float compare\n"); + cpu_abort(env_cpu(env), "unknown return value for float compare\n"= ); } } =20 diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 3c8f0a7615..398c2874e0 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -111,11 +111,11 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint= 64_t addr) env->cc_op =3D (mask >> 44) & 3; =20 if ((old_mask ^ mask) & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env))); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 if (mask & PSW_MASK_WAIT) { - s390_handle_wait(s390_env_get_cpu(env)); + s390_handle_wait(env_archcpu(env)); } } =20 @@ -137,14 +137,13 @@ uint64_t get_psw_mask(CPUS390XState *env) =20 LowCore *cpu_map_lowcore(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); LowCore *lowcore; hwaddr len =3D sizeof(LowCore); =20 lowcore =3D cpu_physical_memory_map(env->psa, &len, 1); =20 if (len < sizeof(LowCore)) { - cpu_abort(CPU(cpu), "Could not map lowcore\n"); + cpu_abort(env_cpu(env), "Could not map lowcore\n"); } =20 return lowcore; diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c index abbbc20d9c..d13cc49be6 100644 --- a/target/s390x/int_helper.c +++ b/target/s390x/int_helper.c @@ -109,10 +109,9 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t a= h, uint64_t al, s390_program_interrupt(env, PGM_FIXPT_DIVIDE, ILEN_AUTO, GETPC= ()); } #else - S390CPU *cpu =3D s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just ab= ort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); + cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index a17eff5ebc..a8f9b38795 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -23,7 +23,7 @@ /* Ensure to exit the TB after this call! */ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ile= n) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_PGM; env->int_pgm_code =3D code; @@ -33,10 +33,8 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t = code, uint32_t ilen) void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, uintptr_t ra) { - S390CPU *cpu =3D s390_env_get_cpu(env); - if (kvm_enabled()) { - kvm_s390_program_interrupt(cpu, code); + kvm_s390_program_interrupt(env_archcpu(env), code); } else if (tcg_enabled()) { tcg_s390_program_interrupt(env, code, ilen, ra); } else { diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 4a0161602f..29d9eaa5b7 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1617,7 +1617,6 @@ uint32_t HELPER(csst_parallel)(CPUS390XState *env, ui= nt32_t r3, uint64_t a1, void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); bool PERchanged =3D false; uint64_t src =3D a2; uint32_t i; @@ -1642,16 +1641,15 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1,= uint64_t a2, uint32_t r3) } =20 if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r= 3) { uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); bool PERchanged =3D false; uint64_t src =3D a2; uint32_t i; @@ -1675,10 +1673,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) } =20 if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } =20 - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) @@ -1737,8 +1735,8 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64= _t real_addr) =20 uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2) { - S390CPU *cpu =3D s390_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + S390CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); =20 /* * TODO: we currently don't handle all access protection types @@ -1906,7 +1904,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l,= uint64_t a1, uint64_t a2) =20 void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m= 4) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); const uintptr_t ra =3D GETPC(); uint64_t table, entry, raddr; uint16_t entries, i, index =3D 0; @@ -1958,7 +1956,7 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, ui= nt64_t r2, uint32_t m4) void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, uint32_t m4) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); const uintptr_t ra =3D GETPC(); uint64_t page =3D vaddr & TARGET_PAGE_MASK; uint64_t pte_addr, pte; @@ -1998,17 +1996,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto,= uint64_t vaddr, /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); - - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } =20 /* flush global tlb */ void HELPER(purge)(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); - - tlb_flush_all_cpus_synced(CPU(cpu)); + tlb_flush_all_cpus_synced(env_cpu(env)); } =20 /* load using real address */ @@ -2052,7 +2046,7 @@ void HELPER(sturg)(CPUS390XState *env, uint64_t addr,= uint64_t v1) /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t cc =3D 0; uint64_t asc =3D env->psw.mask & PSW_MASK_ASC; uint64_t ret; diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index ee67c1fa0c..c806c3ec00 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -55,7 +55,7 @@ /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 HELPER_LOG("%s: exception %d\n", __func__, excp); cs->exception_index =3D excp; @@ -150,7 +150,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint= 32_t r3, uint32_t num) /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t prefix =3D a1 & 0x7fffe000; =20 env->psa =3D prefix; @@ -256,7 +256,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, = uint64_t r0, uint64_t r1) const uint32_t sel2 =3D r1 & STSI_R1_SEL2_MASK; const MachineState *ms =3D MACHINE(qdev_get_machine()); uint16_t total_cpus =3D 0, conf_cpus =3D 0, reserved_cpus =3D 0; - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); SysIB sysib =3D { }; int i, cc =3D 0; =20 @@ -411,7 +411,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t orde= r_code, uint32_t r1, #ifndef CONFIG_USER_ONLY void HELPER(xsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_xsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -419,7 +419,7 @@ void HELPER(xsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(csch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_csch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -427,7 +427,7 @@ void HELPER(csch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(hsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_hsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -435,7 +435,7 @@ void HELPER(hsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_msch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -443,7 +443,7 @@ void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(rchp)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rchp(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -451,7 +451,7 @@ void HELPER(rchp)(CPUS390XState *env, uint64_t r1) =20 void HELPER(rsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -459,7 +459,7 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1) =20 void HELPER(sal)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_sal(cpu, r1, GETPC()); @@ -468,7 +468,7 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1) =20 void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t i= nst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC()); @@ -477,7 +477,7 @@ void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint= 64_t r2, uint64_t inst) =20 void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_ssch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -485,7 +485,7 @@ void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); ioinst_handle_stcrw(cpu, inst >> 16, GETPC()); @@ -494,7 +494,7 @@ void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) =20 void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_stsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -503,7 +503,7 @@ void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uin= t64_t inst) uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) { const uintptr_t ra =3D GETPC(); - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); QEMUS390FLICState *flic =3D s390_get_qemu_flic(s390_get_flic()); QEMUS390FlicIO *io =3D NULL; LowCore *lowcore; @@ -555,7 +555,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) =20 void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_tsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -563,7 +563,7 @@ void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint= 64_t inst) =20 void HELPER(chsc)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_chsc(cpu, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -618,7 +618,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t ad= dr) /* If the instruction has to be nullified, trigger the exception immediately. */ if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 env->per_perc_atmid |=3D PER_CODE_EVENT_NULLIFICATION; env->int_pgm_code =3D PGM_PER; @@ -695,7 +695,7 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t add= r) */ void HELPER(clp)(CPUS390XState *env, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); clp_service_call(cpu, r2, GETPC()); @@ -704,7 +704,7 @@ void HELPER(clp)(CPUS390XState *env, uint32_t r2) =20 void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcilg_service_call(cpu, r1, r2, GETPC()); @@ -713,7 +713,7 @@ void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) =20 void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcistg_service_call(cpu, r1, r2, GETPC()); @@ -723,7 +723,7 @@ void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, ui= nt32_t r2) void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); stpcifc_service_call(cpu, r1, fiba, ar, GETPC()); @@ -745,7 +745,7 @@ void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint6= 4_t r3) =20 void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); rpcit_service_call(cpu, r1, r2, GETPC()); @@ -755,7 +755,7 @@ void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint64_t gaddr, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC()); @@ -765,7 +765,7 @@ void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, ui= nt32_t r3, void HELPER(mpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 qemu_mutex_lock_iothread(); mpcifc_service_call(cpu, r1, fiba, ar, GETPC()); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 145b62a7ef..9669bae393 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -58,12 +58,12 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, uint32_t ilen, uint64_t tec) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 if (kvm_enabled()) { kvm_s390_access_exception(cpu, type, tec); } else { - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); if (type !=3D PGM_ADDRESSING) { stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code),= tec); } @@ -185,7 +185,7 @@ static int mmu_translate_segment(CPUS390XState *env, ta= rget_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t origin, offs, pt_entry; =20 if (st_entry & SEGMENT_ENTRY_RO) { @@ -214,7 +214,7 @@ static int mmu_translate_region(CPUS390XState *env, tar= get_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs =3D CPU(s390_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t origin, offs, new_entry; const int pchks[4] =3D { PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index c1f9245797..ea5f69d5d8 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -454,7 +454,7 @@ int handle_sigp(CPUS390XState *env, uint8_t order, uint= 64_t r1, uint64_t r3) { uint64_t *status_reg =3D &env->regs[r1]; uint64_t param =3D (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1]; - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); S390CPU *dst_cpu =3D NULL; int ret; =20 @@ -492,7 +492,7 @@ int s390_cpu_restart(S390CPU *cpu) =20 void do_stop_interrupt(CPUS390XState *env) { - S390CPU *cpu =3D s390_env_get_cpu(env); + S390CPU *cpu =3D env_archcpu(env); =20 if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) =3D=3D 0) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jHl7gkzT/N8BQj20qWalBWj0TcNnQlOd+W3G9t5Nacs=; b=dZHuwQbEIJt8Qafun4+DETs2m0+QjXaDjbE5XZRnUBykDRTLlfGnEJ7sDtixmSB3vR EoQeNy8OF8pZ49A8kkFOETuvxnDqKK4oOHW3s+xycV3r/ZEam8hlr7Hfpoz0OtMY+6cA fm4UXDjBKNWrUsEtAgmJhdxsMvLdkcU5RuLe59FXdojeLeXlmKJyZe3eJGCxXhuDUDSD 2oNKoE6DKmVZQZlbxvig0pQj+H2RdxpSE9SFyuRJdCxtMORhdZDfFa9XZPAkrLZ9ZAyA 0S1AQu/LgojlB9GneKdJzTxmeJm1LADT5v55yV7u6mtmEJDGdqJWJXob7UWr3WkBG953 QEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jHl7gkzT/N8BQj20qWalBWj0TcNnQlOd+W3G9t5Nacs=; b=r04Bh/QtbBub3xhzefwG1nvwv3imp4bcspsqx3PzDIPpMxUcMJi4KOkgWx6PAg5pKK ekd+hs1RQ5yeU5ByJuThDyZTlXwMkxO7aYXjZUbE7ajMcaOCLm0Lvpxon3XPg3XkTicE DATjhkjPUVNbwyw+xlHHPFUGdYbKOLa8R21TQhanYRAO/QmGS3WjdmcQfaUGTjUqVSeh eeomRfbOqlDEoJgkYFg59jP1BbP16Kwfzr5KXQr3yAPKirG3PMLnt0S4L/wY3ka0rMCq fzRDqUYgjYNmDL9dHy/GBTIrBPfbaJBtnJ4TCUdO1Hy45XlcIM/i9/DGDyf79oLwYRwl 5jkQ== X-Gm-Message-State: APjAAAVG+O49bX5MMghm4EFL296CIJq95h/Ls/hIVjj4bybVHlUDOZIw LuNAujsIvEwY/kJN1jDdHWwdcX3KIBbt2Q== X-Google-Smtp-Source: APXvYqwp4LUz3yFMxLG1d0uQ8d2vumzgXzeHD5BxaYEO+binwIAVThSV2VTjgcSak7dZsSc28NYZxA== X-Received: by 2002:a9d:69d9:: with SMTP id v25mr1735756oto.4.1559680474928; Tue, 04 Jun 2019 13:34:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:37 -0500 Message-Id: <20190604203351.27778-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 25/39] target/sh4: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Cleanup in the boilerplate that each target must define. Replace sh_env_get_cpu with env_archcpu. The combination CPU(sh_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 5 ----- linux-user/sh4/cpu_loop.c | 2 +- target/sh4/helper.c | 26 ++++++++++++-------------- target/sh4/op_helper.c | 9 +++------ 4 files changed, 16 insertions(+), 26 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 8b17e6d63e..089eea261c 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,11 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; =20 -static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) -{ - return container_of(env, SuperHCPU, env); -} - #define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 59cbbeda7e..add8817d86 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -23,7 +23,7 @@ =20 void cpu_loop(CPUSH4State *env) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret; target_siginfo_t info; =20 diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fda195e7cb..2afc1770d8 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -216,8 +216,6 @@ static void update_itlb_use(CPUSH4State * env, int itlb= nb) =20 static int itlb_replacement(CPUSH4State * env) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); - if ((env->mmucr & 0xe0000000) =3D=3D 0xe0000000) { return 0; } @@ -230,7 +228,7 @@ static int itlb_replacement(CPUSH4State * env) if ((env->mmucr & 0x2c000000) =3D=3D 0x00000000) { return 3; } - cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); + cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); } =20 /* Find the corresponding entry in the right TLB @@ -286,7 +284,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int u= tlb) itlb =3D itlb_replacement(env); ientry =3D &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); + tlb_flush_page(env_cpu(env), ientry->vpn << 10); } *ientry =3D env->utlb[utlb]; update_itlb_use(env, itlb); @@ -448,14 +446,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, v= addr addr) =20 void cpu_load_tlb(CPUSH4State * env) { - SuperHCPU *cpu =3D sh_env_get_cpu(env); + CPUState *cs =3D env_cpu(env); int n =3D cpu_mmucr_urc(env->mmucr); tlb_t * entry =3D &env->utlb[n]; =20 if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(cpu), address); + tlb_flush_page(cs, address); } =20 /* Take values into cpu status from registers. */ @@ -478,7 +476,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size =3D 1024 * 1024; /* 1M */ break; default: - cpu_abort(CPU(cpu), "Unhandled load_tlb"); + cpu_abort(cs, "Unhandled load_tlb"); break; } entry->sh =3D (uint8_t)cpu_ptel_sh(env->ptel); @@ -505,7 +503,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v =3D 0; } =20 - tlb_flush(CPU(sh_env_get_cpu(s))); + tlb_flush(env_cpu(s)); } =20 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, @@ -531,7 +529,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->asid =3D asid; entry->vpn =3D vpn; @@ -573,7 +571,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; @@ -626,7 +624,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwa= ddr addr, if (entry->vpn =3D=3D vpn && (!use_asid || entry->asid =3D=3D asid || entry->sh)) { if (utlb_match_entry) { - CPUState *cs =3D CPU(sh_env_get_cpu(s)); + CPUState *cs =3D env_cpu(s); =20 /* Multiple TLB Exception */ cs->exception_index =3D 0x140; @@ -658,13 +656,13 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, h= waddr addr, } =20 if (needs_tlb_flush) { - tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + tlb_flush_page(env_cpu(s), vpn << 10); } } else { int index =3D (addr & 0x00003f00) >> 8; tlb_t * entry =3D &s->utlb[index]; if (entry->v) { - CPUState *cs =3D CPU(sh_env_get_cpu(s)); + CPUState *cs =3D env_cpu(s); =20 /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; @@ -719,7 +717,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwa= ddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address =3D entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn =3D (mem_value & 0x1ffffc00) >> 10; entry->v =3D (mem_value & 0x00000100) >> 8; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 932aa7a7c7..14c3db0f48 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -46,10 +46,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY - SuperHCPU *cpu =3D sh_env_get_cpu(env); - - /* XXXXX */ - cpu_abort(CPU(cpu), "Unhandled ldtlb"); + cpu_abort(env_cpu(env), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif @@ -58,7 +55,7 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int ind= ex, uintptr_t retaddr) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D index; cpu_loop_exit_restore(cs, retaddr); @@ -91,7 +88,7 @@ void helper_debug(CPUSH4State *env) =20 void helper_sleep(CPUSH4State *env) { - CPUState *cs =3D CPU(sh_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; env->in_sleep =3D 1; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Lg8ZYqzoVS5LU/Hk8CNPJL+47kESr7iXuKNlKmQ7dbA=; b=cQfr/jCLUbSIOeHDrEs5DidALVF8R5QxdbcsoEO/4fbpQJP2OvSd9ErV71eNW24/Xh QI4jTcjFMkXtiu2PBykGOSFudGOlCyPGrB6JbvXBe3PILMO7F+vmx+TBoeKvJTJyZwV+ O8Peig4AT58E2z+/yMlMD2xcuXF3gwskJ5EtDpqYTFSXhQgJoUxj4kfRz/5aBdybqgUA LitdKZBuLDrseqy4uzZsYRfLDnfS4XAUEjN8DnXQ5MroXUyYco7NT7PQhbz0lilU4Jtd tJnQFzC3jbvLw9BnV/n8e0A6VUfE6mBze0mbVOsZ6erf1JwE4t/sZ8N3r63XS1JJWYlW 71RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lg8ZYqzoVS5LU/Hk8CNPJL+47kESr7iXuKNlKmQ7dbA=; b=MACUmOdvcReN2zShCHScJsmcBdGas1K779cugvaiwsTLegFd6F2Vkmvf7h/jmBSpaX MjIxAluT9ZvJR74iZMrr40tF36S6XHa/FHL9S7sF+43DigRTA/wpuDSBmYJMpM3wBMjD sfJ8scX3UiO2/mnzDmH9fhJsv8dn+IQO81BdsH9jCcO/44vKRooqYBYQ6ybjVPGHtl5I 6FGkmKH8pH02D4u0+zvSq5IIy8tFg/kJNq60lbAfAoeGme3kmre/Ser/0MKGLqbOUkfC PBwYARbUQd88vab6OtPsWY5dN7nK+6LZnd5g24fDXtUSSHq7WDP+CulQMgQovPnVr62M Hj7g== X-Gm-Message-State: APjAAAX2Yb6rVIuIcPjkvp6uJrvr3VVOx/vKShSnErwcv3oP7Hg/ecMU lUJhSXPI/uI3s4dFSUjMfStht/FsDsnqTQ== X-Google-Smtp-Source: APXvYqzwKkDLGtkrRmHnO2euzse4lxfSENe4b4VxJXY+eCScNQUxT8Ed9MjFSzv5y8+StNBAXXJS6Q== X-Received: by 2002:a9d:3ee:: with SMTP id f101mr5454621otf.311.1559680476651; Tue, 04 Jun 2019 13:34:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:38 -0500 Message-Id: <20190604203351.27778-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v4 26/39] target/sparc: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Cleanup in the boilerplate that each target must define. Replace sparc_env_get_cpu with env_archcpu. The combination CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 ----- bsd-user/main.c | 2 +- hw/sparc/leon3.c | 4 ++-- hw/sparc/sun4m.c | 4 ++-- hw/sparc64/sparc64.c | 2 +- linux-user/sparc/cpu_loop.c | 2 +- target/sparc/fop_helper.c | 2 +- target/sparc/helper.c | 8 ++++---- target/sparc/ldst_helper.c | 33 +++++++++++++++------------------ target/sparc/mmu_helper.c | 10 +++++----- 10 files changed, 32 insertions(+), 40 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e29421349b..adcd9e3000 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,11 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; =20 -static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) -{ - return container_of(env, SPARCCPU, env); -} - #define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY diff --git a/bsd-user/main.c b/bsd-user/main.c index bfdcae4269..f6f76f1a64 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -486,7 +486,7 @@ static void flush_windows(CPUSPARCState *env) =20 void cpu_loop(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr, ret, syscall_nr; //target_siginfo_t info; =20 diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index bdead85a93..19cedebd16 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -159,7 +159,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil= _in) =20 env->interrupt_index =3D TT_EXTINT | i; if (old_interrupt !=3D env->interrupt_index) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_leon3_set_irq(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -167,7 +167,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil= _in) } } } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_leon3_reset_irq(env->interrupt_index & 15); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 5151a7202b..7e4f61fc3e 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -166,7 +166,7 @@ void cpu_check_irqs(CPUSPARCState *env) =20 env->interrupt_index =3D TT_EXTINT | i; if (old_interrupt !=3D env->interrupt_index) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_sun4m_cpu_interrupt(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -174,7 +174,7 @@ void cpu_check_irqs(CPUSPARCState *env) } } } else if (!env->pil_in && (env->interrupt_index & ~15) =3D=3D TT_EXTI= NT) { - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 408388945e..689801f37d 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -46,7 +46,7 @@ void cpu_check_irqs(CPUSPARCState *env) if (env->ivec_status & 0x20) { return; } - cs =3D CPU(sparc_env_get_cpu(env)); + cs =3D env_cpu(env); /* check if TM or SM in SOFTINT are set setting these also causes interrupt 14 */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 9e357229c0..d85359037c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -145,7 +145,7 @@ static void flush_windows(CPUSPARCState *env) =20 void cpu_loop (CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index b6642fd1d7..9eb9b75718 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCStat= e *env, uintptr_t ra) } =20 if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* Unmasked exception, generate a trap. Note that while the helper is marked as NO_WG, we can get away with diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 46232788c8..1a52061fbf 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -26,7 +26,7 @@ =20 void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit_restore(cs, ra); @@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, u= intptr_t ra) =20 void helper_raise_exception(CPUSPARCState *env, int tt) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D tt; cpu_loop_exit(cs); @@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) =20 void helper_debug(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cs); @@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target= _ulong src1, #ifndef TARGET_SPARC64 void helper_power_down(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index b4bf6faf41..7f56c100c6 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_ac= cess_register) =20 static void replace_tlb_entry(SparcTLBEntry *tlb, uint64_t tlb_tag, uint64_t tlb_tte, - CPUSPARCState *env1) + CPUSPARCState *env) { target_ulong mask, size, va, offset; =20 /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env1)); + CPUState *cs =3D env_cpu(env); =20 size =3D 8192ULL << 3 * TTE_PGSIZE(tlb->tte); mask =3D 1ULL + ~size; @@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong= addr, { int size =3D 1 << (memop & MO_SIZE); int sign =3D memop & MO_SIGN; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t ret =3D 0; #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr =3D addr; @@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, int asi, uint32_t memop) { int size =3D 1 << (memop & MO_SIZE); - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 do_check_align(env, addr, size - 1, GETPC()); switch (asi) { @@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, uint64_t val, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(CPU(cpu), addr & 0xfffff000); + tlb_flush_page(cs, addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; default: break; @@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) & (MMU_NF | env->def.mmu_bm)) { - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 1: /* Context Table Pointer Register */ @@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong add= r, uint64_t val, if (oldreg !=3D env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, uint64_t val, case ASI_USERTXT: /* User code access, XXX */ case ASI_KERNELTXT: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, true, false, asi, size); + cpu_unassigned_access(cs, addr, true, false, asi, size); break; =20 case ASI_USERDATA: /* User data access */ @@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, { int size =3D 1 << (memop & MO_SIZE); int sign =3D memop & MO_SIGN; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint64_t ret =3D 0; #if defined(DEBUG_ASI) target_ulong last_addr =3D addr; @@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong a= ddr, target_ulong val, int asi, uint32_t memop) { int size =3D 1 << (memop & MO_SIZE); - SPARCCPU *cpu =3D sparc_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); @@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, target_ulong val, env->dmmu.mmu_primary_context =3D val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context =3D val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong= addr, target_ulong val, case 1: env->dmmu.mmu_primary_context =3D val; env->immu.mmu_primary_context =3D val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_I= DX)); break; case 2: env->dmmu.mmu_secondary_context =3D val; env->immu.mmu_secondary_context =3D val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_SECONDARY_IDX) | (1 << MMU_KERNEL_SECONDARY_IDX)); break; diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index facc0c60e9..cbd1e91179 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -97,7 +97,7 @@ static int get_physical_address(CPUSPARCState *env, hwadd= r *physical, uint32_t pde; int error_code =3D 0, is_dirty, is_user; unsigned long page_offset; - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 is_user =3D mmu_idx =3D=3D MMU_USER_IDX; =20 @@ -268,7 +268,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, =20 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); hwaddr pde_ptr; uint32_t pde; =20 @@ -335,7 +335,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong= address, int mmulev) =20 void dump_mmu(CPUSPARCState *env) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_ulong va, va1, va2; unsigned int n, m, o; hwaddr pde_ptr, pa; @@ -494,7 +494,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu= _idx) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int i; uint64_t context; uint64_t sfsr =3D 0; @@ -612,7 +612,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { - CPUState *cs =3D CPU(sparc_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); unsigned int i; uint64_t context; bool is_user =3D false; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=ZuP9P/y2awmw4izu8Ta8VFFIgoiKI0vJso4eBOFOhZo=; b=FP/D1Y1iqgpLQtySYV9nBgT4e6P62H7u/gFtlA4N3isoDkmlvj52z2xgYOwPw8/RPX IrZPcjYubpbF1F7myI6q36APDhfqehV+liNy56LewCL9CBk7i7Ku74KwCUljFHN7Ym1D LxvrSgZS8Ura8njbR1Oz5lafu4wfxoXFDynpvu5sgjqYBDhjwWLbxie/Kj3HpfmaVtxY 8RZlYkVNHlFDnAiiVOmAyq+mRIiZH4uq3W+Rznm/HdKxpYe/v/C3Bpb1N+Lq44XyTerY rbxhgEO/uKYicL3ZHrE4ng/e4DkOiYUL02X7ikejrsTlxM4PELe9DVwthZntXz7XSPIX adhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=ZuP9P/y2awmw4izu8Ta8VFFIgoiKI0vJso4eBOFOhZo=; b=Ukc+1UlBJkq0pUt3Svvtvmn7NjCeGjbeL0AnZKzn+21clFXcaMuHgAMs8DKexUJ1JY ggFzqfMEXZ6t4FZlo4OCy+ZI5vweX88qaKNvUvcgEse5CuPyFi2MbbhC668TH2a8KNpl XSnTV0uDV6q49U1DRPO+xv9v2zsWTKHGIvAeen9TIVd7Dt6z+UVycM2XOmwRB669yOpc sNd8Yohijt/p6bvi9I48+F3BQslbMpNG06xL81oP2zXdBFc1D6Inf8pP54CmL/uLzyp3 rtVo7t49ZJEGewSvcaoqGiGp/XLhGbnF16GSZGp+O45Mb8LTkaHBjZvN//bjkgSPVG3b UDdQ== X-Gm-Message-State: APjAAAWusvlmZrXIVC45acVIsEVU8QWgxbz25Q9o/APJxlHpWFzQjRYA 7OWIvNn6tLesaNvSgpabpdr4falzdRXz4A== X-Google-Smtp-Source: APXvYqzeprpiStjU6Tcb2WXnZ5vwAX+F5SacMa7H1nyiykhsqrCfw4UTLTQ5hRHpj9okg/aVKHYDZw== X-Received: by 2002:aca:c786:: with SMTP id x128mr5295534oif.146.1559680477950; Tue, 04 Jun 2019 13:34:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:39 -0500 Message-Id: <20190604203351.27778-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v4 27/39] target/tilegx: Use env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace tilegx_env_get_cpu with env_archcpu. The combination CPU(tilegx_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tilegx/cpu.h | 5 ----- linux-user/tilegx/cpu_loop.c | 2 +- target/tilegx/helper.c | 2 +- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 135df63523..7f8fe7c513 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,11 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; =20 -static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) -{ - return container_of(env, TileGXCPU, env); -} - #define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c index 4f39eb9ad3..d4abe29dcd 100644 --- a/linux-user/tilegx/cpu_loop.c +++ b/linux-user/tilegx/cpu_loop.c @@ -206,7 +206,7 @@ static void do_fetch(CPUTLGState *env, int trapnr, bool= quad) =20 void cpu_loop(CPUTLGState *env) { - CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; =20 while (1) { diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index 4964bb9111..a57a679825 100644 --- a/target/tilegx/helper.c +++ b/target/tilegx/helper.c @@ -28,7 +28,7 @@ =20 void helper_exception(CPUTLGState *env, uint32_t excp) { - CPUState *cs =3D CPU(tilegx_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559682058; cv=none; d=zoho.com; s=zohoarc; b=mQRI9UUrJqjALiATp9aZ/UcCKbBGKL9vKab1ZHILudtq899s7hNzX5CL0ZPqGJO2gKkA6TTLdy8DMJWuItyuzcNUjKOEvyaEdDp3/5e6p/gVof55p72RscTe4gmxHKsafnbi6ttOrCzYObcr3T7cIRKqPODc92o1aLkIQBYLaB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559682058; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YQXS0805f11aCOQVinsy2uv+bSnryD5T76PFwhCiklU=; b=arBLSP8EtnF0VxQmrq8L2xqpFS/o41plwJABDQrflEeMPI4bdVRCjttxS98axWr1Adlfy9+8UGkaT+PBJSOLqqg/GiDJ372eudMzdaECqxzOUqgf2s7pSouUOLoKPTMrICvCTqAoItXjIWXsa2KYQTzats0sHNsDRFqx/Pl5jqw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559682058481338.22386684129333; Tue, 4 Jun 2019 14:00:58 -0700 (PDT) Received: from localhost ([127.0.0.1]:58011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGY7-0006W0-GN for importer@patchew.org; Tue, 04 Jun 2019 17:00:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8n-0001T7-Ed for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8m-0004eE-IT for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:41 -0400 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:34608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8m-0004dZ-DT for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:40 -0400 Received: by mail-oi1-x241.google.com with SMTP id u64so16636042oib.1 for ; Tue, 04 Jun 2019 13:34:40 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=YQXS0805f11aCOQVinsy2uv+bSnryD5T76PFwhCiklU=; b=JArYRBxPghL/cDE81vV0ce+oU6C7ziwidFxFgG/YURtzBE3XRmsUOh7qO3GcAFHt9D pVNoJgzrlyHR+PrEfMkLZSf3XrZhIH4EAAbsCmaZcAqKXgrhhYUInYMuit8MfxaXFEh4 UPd+Nckq07zMAK4ic8lkNiSGvPJUpS3Vx+vqO8MIM+GMKiKHhVeeClJdgpMTs8ta0wbs gzChzFOmLCtwqiA78Os9zKuh5QWaz3wsWjIC+BWVB09DuJktboHpbG9HDEUMyeTYUFuX nja/ADes7qPZjBP0o6HF7Mm1KuVTjA5CiKJ9XS70FI6Dcy++9+Q14PgtvOpD7ojuWhK/ HF8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=YQXS0805f11aCOQVinsy2uv+bSnryD5T76PFwhCiklU=; b=mFLoKnMW6qn4J4sZTI1bmHxrDB3Ce1TsZ5W84D+3HD8e6UySTfTqJajIqLlGeJ1y/V SAJivEXRm4l9ls2BvxD6cyXrzugu7ut9lQP1n6KeHuLM1JTPKkExs72k3fQBp677Xmli TYelKui9ykfJZzO+ciidyLlojbLunoI2dZX4eDJ0tBsGKUzEabMLKpY8If1JGHLTVJR5 PFYF3e5pdgjAvHQTo4XrA+KUaphHEnbTHCVcrW+R+JiEeGVA0sKs61oX6xgtrSamPu1m O7CTbSCe0CfwwE5wl6FGyIrBCdCc8ULfSThuhaisc9Z8yFNSvFML4moI7Sizz1m6J9qs ec3A== X-Gm-Message-State: APjAAAWVmXt+Cd6FhPrgeAgMGXP3trAeH1IURL47bPOGHrLPqD/oIup1 qLzfzY/iKqKlmP6EwtFcdooNAtjBoSrcsg== X-Google-Smtp-Source: APXvYqx/dIbehgKOYZKcpGO86DAYvgUSsUNPMXpZLPhBuv7o0hXIE3xCTpyUxCqkxJc5cwCM2+uk4g== X-Received: by 2002:aca:ac4d:: with SMTP id v74mr3417597oie.66.1559680479344; Tue, 04 Jun 2019 13:34:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:40 -0500 Message-Id: <20190604203351.27778-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v4 28/39] target/tricore: Use env_cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace tricore_env_get_cpu with env_archcpu. The combination CPU(tricore_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tricore/cpu.h | 5 ----- target/tricore/op_helper.c | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4a2a955cc5..6a40d37362 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -208,11 +208,6 @@ struct TriCoreCPU { CPUTriCoreState env; }; =20 -static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env) -{ - return TRICORE_CPU(container_of(env, TriCoreCPU, env)); -} - #define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 601e92f92a..9476d10d00 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -29,7 +29,7 @@ static void QEMU_NORETURN raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int ti= n, uintptr_t pc, uint32_t fcd_pc) { - CPUState *cs =3D CPU(tricore_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); /* in case we come from a helper-call we need to restore the PC */ cpu_restore_state(cs, pc, true); =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559682186; cv=none; d=zoho.com; s=zohoarc; b=dDhX713mGxS5bOlc7ApwhrmX1gWklH3l6sJCcd44oFzWp/tYAt5oKNnoq1ugxqk7Shu9AXdldJPF3aMQZ/ZbCAjBT5LXr9yljwJbGxC8qwlWrw4J+mhCAxbDZel/o6NEC3i9MbQ8iyiDio+9FEmNou3lmVmwZXyIuqK1rvQiAJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559682186; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8TtqTmBnQgsNdelS4/2zOiTH2Ne6fCH7LBgKkWFYMCA=; b=JGKX7K9n1yAQFp2PAoeBjz5eouyOzqg+ID0vpw3u94kF+/YHV0+RMH5PCajKMFV+q6S4XFpkzpLRCJx2O4yuBleq/QHwYBoYHcgNxoVGJU/JYyOAC1tTjURRxTx1NoEGklJeeEdI++AGB3ugUnVBTsLCCnzNiPRGbFwUgiqhRu8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559682186438849.2478063570742; Tue, 4 Jun 2019 14:03:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:58046 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGaB-0008K3-E1 for importer@patchew.org; Tue, 04 Jun 2019 17:02:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG8q-0001W6-9G for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8o-0004hB-23 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:43 -0400 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:35317) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8n-0004fl-SO for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:42 -0400 Received: by mail-ot1-x342.google.com with SMTP id n14so20873989otk.2 for ; Tue, 04 Jun 2019 13:34:41 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=8TtqTmBnQgsNdelS4/2zOiTH2Ne6fCH7LBgKkWFYMCA=; b=q1zjSdonzryn6WEg7j5mevPE6PHAIHR44lKoyJ+Oh4VTMhHtomHR6VGVP0JsLM2pCu wM0k8DZmqHRT+XsFQr143sV1Yjtj8REYkKPQtOBZSehDXhPVo6om/Wz4Q0n7kV/gPit+ /nWDsoerQ2iAzpC2zIMSB1t85prmWnOLxi90BuP2521nAV3GzhbIGA/ze+mAq3qLoFRp 8Q5AhNQDAr1Ml7Igz7amLMpqb9WwdXyNRXyr9rMccgh3rNYgN/TURJVHzy8sh9HxZ6JE r6u4EWEQodnwEEpcbzNsG7EM9AZj2KKf4fr2xwksVZ1bKN4r4EG00RpnvifmtOTL+9Zh PGKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8TtqTmBnQgsNdelS4/2zOiTH2Ne6fCH7LBgKkWFYMCA=; b=osfcGsFXGE/GvuFJ7+MZnylh4dxxsDMfyzhFz51KaUx0CuS6uFDKACW2hbJkHvT20A qY2MNecOgn80vqx8AIBdLPifvCleYrrqKYmr2QNjqzvK2ooju93rzxqtphcEw2b+m5DA pU9vSddg3WPBBRq3SJ7skQxUk2+OkqW+SAto1yXjCPyxdZfxWhMoYdlLJ1pGU0zTBY+C YTBCCpNSNQjKYXomdyI0qUSIOqqO0cbHNfmF4nlZK/RIyf4SALHLBVJcD20p9xvBAKgi SsY2GTyNx8pKFNU3gClyLiZ4Az3s6XlMy66IHoL9MtxBUDmGKRpewDQLa/ULjcVVCihI cB0Q== X-Gm-Message-State: APjAAAVTD6aPLuyEFo5mZ1jyZKf1nTFexAmfuuQq+u/jI9mMogJia/XT WjSD9ME7/J1iu+WVa3GBKvkAc6y2B1Qh9A== X-Google-Smtp-Source: APXvYqyFf6QYeUPzI4AFwkTcjeRgYUZHiaVtJL6fjO+srT0FWbXxSLRsEdcn/JUKT1Y9UPXD2ieXBA== X-Received: by 2002:a9d:72da:: with SMTP id d26mr7104441otk.327.1559680480806; Tue, 04 Jun 2019 13:34:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:41 -0500 Message-Id: <20190604203351.27778-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 29/39] target/unicore32: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace uc32_env_get_cpu with env_archcpu. The combination CPU(uc32_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 ----- hw/unicore32/puv3.c | 2 +- target/unicore32/helper.c | 4 +--- target/unicore32/op_helper.c | 2 +- target/unicore32/softmmu.c | 11 ++++------- target/unicore32/translate.c | 26 ++------------------------ target/unicore32/ucf64_helper.c | 2 +- 7 files changed, 10 insertions(+), 42 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index e91cec4d2e..595dc43c99 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,11 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; =20 -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) -{ - return container_of(env, UniCore32CPU, env); -} - #define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index b42e600f74..132e6086ee 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env) =20 /* Initialize interrupt controller */ cpu_intc =3D qemu_allocate_irq(puv3_intc_cpu_handler, - uc32_env_get_cpu(env), 0); + env_archcpu(env), 0); dev =3D sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc); for (i =3D 0; i < PUV3_IRQS_NR; i++) { irqs[i] =3D qdev_get_gpio_in(dev, i); diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index 0d4914b48d..7d538e2144 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -31,8 +31,6 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val= , uint32_t creg, case 6: if ((cop <=3D 6) && (cop >=3D 2)) { /* invalid all tlb */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); return; } break; diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 797ba60dc9..eeaa78601a 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -19,7 +19,7 @@ =20 void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - CPUState *cs =3D CPU(uc32_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; cpu_loop_exit(cs); diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 27f218abf0..cbdaa500b7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -36,8 +36,6 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int= mode) case ASR_MODE_INTR: return 4; } - cpu_abort(CPU(cpu), "Bad mode %x\n", mode); + cpu_abort(env_cpu(env), "Bad mode %x\n", mode); return -1; } =20 @@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, u= int32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); int code; uint32_t table; uint32_t desc; @@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,= uint32_t address, *page_size =3D TARGET_PAGE_SIZE; break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } =20 *phys_ptr =3D phys_addr; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 89b02d1c3c..d27451eed3 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -180,7 +180,7 @@ static void store_reg(DisasContext *s, int reg, TCGv va= r) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) =20 -#define ILLEGAL cpu_abort(CPU(cpu), \ +#define ILLEGAL cpu_abort(env_cpu(env), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) =20 @@ -188,7 +188,6 @@ static void store_reg(DisasContext *s, int reg, TCGv va= r) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) =3D=3D 0xe0000000) { tmp2 =3D new_tmp(); @@ -214,7 +213,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, Disa= sContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; =20 if ((insn & 0xff003fff) =3D=3D 0xe1000400) { @@ -682,7 +680,6 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint3= 2_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -729,7 +726,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, Dis= asContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint3= 2_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -815,7 +811,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, Dis= asContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32= _t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; =20 if ((insn & 0xfe0003ff) =3D=3D 0xe2000000) { @@ -880,8 +875,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, Disa= sContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_= t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT =3D=3D 3) { ILLEGAL; } @@ -948,8 +941,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, Disas= Context *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_= t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_SET(25)) { ILLEGAL; } @@ -1028,8 +1019,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, Dis= asContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32= _t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT =3D=3D 3) { ILLEGAL; } @@ -1063,8 +1052,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, Di= sasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint= 32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1162,8 +1149,6 @@ static void gen_exception_return(DisasContext *s, TCG= v pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1178,14 +1163,13 @@ static void disas_coproc_insn(CPUUniCore32State *en= v, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(CPU(cpu), "Unknown coprocessor!"); + cpu_abort(env_cpu(env), "Unknown coprocessor!"); } } =20 /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins= n) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1419,7 +1403,6 @@ static void do_mult(CPUUniCore32State *env, DisasCont= ext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val; TCGv tmp; =20 @@ -1545,7 +1528,6 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasC= ontext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1573,7 +1555,6 @@ static void do_swap(CPUUniCore32State *env, DisasCont= ext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t= insn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); TCGv addr; TCGv tmp; =20 @@ -1626,7 +1607,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, Disa= sContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in= sn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1768,7 +1748,6 @@ static void do_ldst_m(CPUUniCore32State *env, DisasCo= ntext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t in= sn) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1798,7 +1777,6 @@ static void do_branch(CPUUniCore32State *env, DisasCo= ntext *s, uint32_t insn) =20 static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); unsigned int insn; =20 insn =3D cpu_ldl_code(env, s->pc); diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helpe= r.c index fad3fa6618..e078e84437 100644 --- a/target/unicore32/ucf64_helper.c +++ b/target/unicore32/ucf64_helper.c @@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bit= s) =20 void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); + UniCore32CPU *cpu =3D env_archcpu(env); int i; uint32_t changed; =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559682341; cv=none; d=zoho.com; s=zohoarc; b=LuyYkhrDL6Qdn8hSdh5q3yHFAOjvFUyU5rUi/iN+HAKKbi4KF9p9G3UOsnDYrwA7yFBoIFDtVVqKiXS0fSyuuNYqMHLOUdWtzo0KvrDa4l2Dr77WPOysXz2WDKDggk/F04aHjsBzd9XY5BMVjmSi7gDX/OeUeGun5D8pC9Q5POU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559682341; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v4 30/39] target/xtensa: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 17 ++++++----------- hw/xtensa/pic_cpu.c | 2 +- linux-user/xtensa/cpu_loop.c | 2 +- target/xtensa/dbg_helper.c | 4 ++-- target/xtensa/exc_helper.c | 9 ++++----- target/xtensa/helper.c | 2 +- target/xtensa/mmu_helper.c | 17 ++++++----------- target/xtensa/xtensa-semi.c | 2 +- 8 files changed, 22 insertions(+), 33 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3de53cb5d0..97b7bae0fe 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -559,11 +559,6 @@ struct XtensaCPU { CPUXtensaState env; }; =20 -static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) -{ - return container_of(env, XtensaCPU, env); -} - #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 @@ -724,10 +719,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, = bool ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 +typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; + +#include "exec/cpu-all.h" + static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong = *pc, target_ulong *cs_base, uint32_t *flags) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 *pc =3D env->pc; *cs_base =3D 0; @@ -797,9 +797,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } } =20 -typedef CPUXtensaState CPUArchState; -typedef XtensaCPU ArchCPU; - -#include "exec/cpu-all.h" - #endif diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index a8939f5e58..df3acbb541 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -33,7 +33,7 @@ =20 void check_interrupts(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int minlevel =3D xtensa_get_cintlevel(env); uint32_t int_set_enabled =3D env->sregs[INTSET] & env->sregs[INTENABLE= ]; int level; diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index bee78edb8a..64831c9199 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env) =20 void cpu_loop(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index cd8fbd653a..be1f81107b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,= uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask =3D dbreakc | ~DBREAKC_MASK; =20 @@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t = i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] =3D NULL; diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 4a1f7aef5d..601341d13a 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -34,7 +34,7 @@ =20 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cs->exception_index =3D excp; if (excp =3D=3D EXCP_YIELD) { @@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint3= 2_t pc, uint32_t cause) =20 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) { - CPUState *cpu; + CPUState *cpu =3D env_cpu(env); =20 env->pc =3D pc; env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | @@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, = uint32_t intlevel) qemu_mutex_unlock_iothread(); =20 if (env->pending_irq_level) { - cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); + cpu_loop_exit(cpu); return; } =20 - cpu =3D CPU(xtensa_env_get_cpu(env)); cpu->halted =3D 1; HELPER(exception)(env, EXCP_HLT); } @@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (level > 1) { env->sregs[EPC1 + level - 1] =3D env->pc; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f2d07e4a2f..376a61f339 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -324,7 +324,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, =20 void xtensa_runstall(CPUXtensaState *env, bool runstall) { - CPUState *cpu =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cpu =3D env_cpu(env); =20 env->runstall =3D runstall; cpu->halted =3D runstall; diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index cab39f687a..f15bff306f 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -71,12 +71,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_= t vaddr) =20 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - v =3D (v & 0xffffff00) | 0x1; if (v !=3D env->sregs[RASID]) { env->sregs[RASID] =3D v; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 @@ -276,8 +274,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, b= ool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); xtensa_tlb_entry *entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); =20 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { @@ -503,7 +500,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint= 32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); + tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid =3D 0; } } @@ -844,7 +841,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, b= ool update_tlb, =20 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t paddr; uint32_t page_size; unsigned access; @@ -924,13 +921,11 @@ static int xtensa_mpu_lookup(const xtensa_mpu_entry *= entry, unsigned n, =20 void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) { - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - v &=3D (2u << (env->config->n_mpu_fg_segments - 1)) - 1; =20 if (v !=3D env->sregs[MPUENB]) { env->sregs[MPUENB] =3D v; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } =20 @@ -942,7 +937,7 @@ void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uin= t32_t v) env->mpu_fg[segment].vaddr =3D v & -env->config->mpu_align; env->mpu_fg[segment].attr =3D p & XTENSA_MPU_ATTR_MASK; env->sregs[MPUENB] =3D deposit32(env->sregs[MPUENB], segment, 1, v= ); - tlb_flush(CPU(xtensa_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } =20 diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 38efa3485a..8862985e56 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr) =20 void HELPER(simcall)(CPUXtensaState *env) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); uint32_t *regs =3D env->regs; =20 switch (regs[2]) { --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=uSSyoHXJH7D31EiI6ZgERCNl/xa+/DM8TM4+rAUEItM=; b=DS0qjvuIG3Cx8h/cpRwZFaNHanJn4+FEzMXu9vnBQNL8zut8j3HkjPfssYPvzOIJlu rQ2J3RuJeDQRoopLHLz7JyiX/2jY4NDgfD5v4sPQ4BGYtZBMDnl1KnTD3KrdnpAGBZXj 9spWJqKQbKArZ4HXUdfGCRJK8UZVCHEGGDD4W7yPOE89sgeZe9pwiBMN4315BKBOpjpD 8mKsBEM747nK1AiR50e6NmyahTus43yXYjOKFjCYbF0igKEskcSXFl5zNmFc0SrNGmLE ORH+wx+RPhk6ckaaz+7SGzycnHSy4DIh8rlGq8lLvqClKEuqWaiY4aABDnteyXbyw4bD bgbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=uSSyoHXJH7D31EiI6ZgERCNl/xa+/DM8TM4+rAUEItM=; b=ckjImARfrMfusXylDorJpE6gw1mynKp8a4FaLiCpQ4Fsx2LIWLjFfMzKzQJlKUz8XN L6ctstySSZJUQEoKRfSNBqOhxWq/4eC+gWv9q2e0enV54H/u4om71DiRBNrFg1yIKNnO TkRxBJ6Q69XpHIPtrIAGozxKOCRd7AhB8JaUa+BzdVYG/px8YWlNE35HdSt9Lyp80TBD 3wpNTjk7qpoQn9Wt+DkDUIELBuLUVOIwFLbZQJud/vT3fSPsFuRETW7YCi/gTbOthIzs hPQmpevivJOj7psNKBjQZrULzZcL6BIyMKOnTup2LvRwHwlUvvQC5/BGqBpf2HCQcJEb 3iAQ== X-Gm-Message-State: APjAAAU0LlozGTkWLybNdU1+r0es2/wuEt9NDf7zxm5LJ+0BuwQ/fb88 XW8MiyRFLJaLgsjanrvgeNq5g9uxoY1RFg== X-Google-Smtp-Source: APXvYqxbkzZPKIGYIZDMni3CcKSc0yvK73DCJnSA1oCzKDKvdZ3jB4cOUL+Ujhf7A1GbIxmxUn/3tw== X-Received: by 2002:a9d:6494:: with SMTP id g20mr6668678otl.195.1559680483387; Tue, 04 Jun 2019 13:34:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:43 -0500 Message-Id: <20190604203351.27778-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v4 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 2 ++ target/alpha/cpu.h | 1 - target/arm/cpu.h | 2 -- target/cris/cpu.h | 1 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 1 - target/lm32/cpu.h | 1 - target/m68k/cpu.h | 1 - target/microblaze/cpu.h | 1 - target/mips/cpu.h | 1 - target/moxie/cpu.h | 1 - target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/ppc/cpu.h | 1 - target/riscv/cpu.h | 2 -- target/s390x/cpu.h | 1 - target/sh4/cpu.h | 1 - target/sparc/cpu.h | 1 - target/tilegx/cpu.h | 1 - target/tricore/cpu.h | 1 - target/unicore32/cpu.h | 1 - target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 24 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 24f7991781..9cfa6ccce5 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,6 +5,8 @@ =20 /* Helpers for instruction counting code generation. */ =20 +#define ENV_OFFSET offsetof(ArchCPU, env) + static TCGOp *icount_start_insn; =20 static inline void gen_tb_start(TranslationBlock *tb) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 86d3e953b9..361f85c976 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -278,7 +278,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; =20 -#define ENV_OFFSET offsetof(AlphaCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_alpha_cpu; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7df3816b5..abe6fce7ab 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -917,8 +917,6 @@ void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); =20 -#define ENV_OFFSET offsetof(ARMCPU, env) - #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_arm_cpu; #endif diff --git a/target/cris/cpu.h b/target/cris/cpu.h index e9e4e39a40..83c350377a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,7 +183,6 @@ struct CRISCPU { CPUCRISState env; }; =20 -#define ENV_OFFSET offsetof(CRISCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_cris_cpu; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 75e6a91a5e..7f9f54731b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,7 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 -#define ENV_OFFSET offsetof(HPPACPU, env) =20 typedef CPUHPPAState CPUArchState; typedef HPPACPU ArchCPU; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 709d88cfcf..3a155c12d3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1480,7 +1480,6 @@ struct X86CPU { int32_t hv_max_vps; }; =20 -#define ENV_OFFSET offsetof(X86CPU, env) =20 #ifndef CONFIG_USER_ONLY extern struct VMStateDescription vmstate_x86_cpu; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 7fb65fb4b6..2c934472d6 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -195,7 +195,6 @@ struct LM32CPU { uint32_t features; }; =20 -#define ENV_OFFSET offsetof(LM32CPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_lm32_cpu; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7f3fa8d141..4006663494 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,7 +163,6 @@ struct M68kCPU { CPUM68KState env; }; =20 -#define ENV_OFFSET offsetof(M68kCPU, env) =20 void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 8402cc81f6..a17c12ca2f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,7 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; =20 -#define ENV_OFFSET offsetof(MicroBlazeCPU, env) =20 void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index cb09425476..24fe25f61c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1071,7 +1071,6 @@ struct MIPSCPU { CPUMIPSState env; }; =20 -#define ENV_OFFSET offsetof(MIPSCPU, env) =20 void mips_cpu_list(void); =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b9f5635e50..3d418c8f1d 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -90,7 +90,6 @@ typedef struct MoxieCPU { CPUMoxieState env; } MoxieCPU; =20 -#define ENV_OFFSET offsetof(MoxieCPU, env) =20 void moxie_cpu_do_interrupt(CPUState *cs); void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9490ba83e4..c96d797dda 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -194,7 +194,6 @@ typedef struct Nios2CPU { uint32_t fast_tlb_miss_addr; } Nios2CPU; =20 -#define ENV_OFFSET offsetof(Nios2CPU, env) =20 void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9e46ac5266..39e2765aa2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,7 +317,6 @@ typedef struct OpenRISCCPU { =20 } OpenRISCCPU; =20 -#define ENV_OFFSET offsetof(OpenRISCCPU, env) =20 void cpu_openrisc_list(void); void openrisc_cpu_do_interrupt(CPUState *cpu); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 73ef868a7b..73b92c189c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1203,7 +1203,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; =20 -#define ENV_OFFSET offsetof(PowerPCCPU, env) =20 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 29a1e08f03..d9611eaced 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -239,8 +239,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; =20 -#define ENV_OFFSET offsetof(RISCVCPU, env) - void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index eefed6f509..971dc0ccbd 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,7 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; =20 -#define ENV_OFFSET offsetof(S390CPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_s390_cpu; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 089eea261c..610a8db6de 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,7 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; =20 -#define ENV_OFFSET offsetof(SuperHCPU, env) =20 void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index adcd9e3000..0cc36873ce 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,7 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; =20 -#define ENV_OFFSET offsetof(SPARCCPU, env) =20 #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_sparc_cpu; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 7f8fe7c513..643b7dbd17 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,7 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; =20 -#define ENV_OFFSET offsetof(TileGXCPU, env) =20 /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 6a40d37362..9f45bb5c24 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -208,7 +208,6 @@ struct TriCoreCPU { CPUTriCoreState env; }; =20 -#define ENV_OFFSET offsetof(TriCoreCPU, env) =20 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 595dc43c99..c1130e9548 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,7 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; =20 -#define ENV_OFFSET offsetof(UniCore32CPU, env) =20 void uc32_cpu_do_interrupt(CPUState *cpu); bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 97b7bae0fe..e89605747a 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -559,8 +559,6 @@ struct XtensaCPU { CPUXtensaState env; }; =20 -#define ENV_OFFSET offsetof(XtensaCPU, env) - =20 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=aRRPed9GGahppyN9nV5kay8UuYoPwEZwq6VS5FHWIs8=; b=uq5uNHNck/rn3lN07DCyeVrS4S3cd9dVqT2VJwL0kGtQb6HFq57mz6aeyedHtVLV+N p9S6bPKiL5FRXG9AeANgDJkKFr0YH+gwPtZveCEmvW8rekquD4hBcSIgxysYkf4KRe6T 9U+l1nfNgS927oBvZKsn93BtheVjkjZsWRcvUb+YTqNTum6IPV0M3tiUUj8ikwIHodHI CDYO62pirFMBWSFjfKbmi8jAzAzrAoJFQVzUZ2/f+EREsAp0AKXRhhECtGm3xm4/W76k VF2PbwfG0BQUnAQQJqQaKb2wur2+O/1UL/e3kac2tYmVbBdbf2zrcJHEsOdeUrtssEeb w58Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=aRRPed9GGahppyN9nV5kay8UuYoPwEZwq6VS5FHWIs8=; b=AzMUgZR5OAVibPCDoHrfL+snX326lL3co2s54PjsuuSQo4EIIQPgIEbOiEWNwOqU6z tb4JreDgo9J3FDG3QhPUTfXCBnBKorfSYTzkcUpCZvcCLasTqZ8u4C9xQp6K1hQse5T1 CSm5cCnGWMyKSERtT4Q7xd7C9e9oy78brL93mCVblcz70mqCMIPBcAM3611txQ3zHcmY KEE8eyQL4MsGhCtq+Y7nIUAqmCnJCddeUxIdFjkWsdqFFRv1LuT6k7Yf1KalJe0/rl9R cnByot9ecjLnmOz7V6dnWvg/+Y/sWuNyZJB+8MlZpxh88gNKfRiOkbQ1U3OQxYOgpQXs nL9g== X-Gm-Message-State: APjAAAWyg9+rvvY52HZA2HGvHYR+yW90YY5ucIqj6HVvILkhVc0gaaaB qog39Dz7QHJb4gKFBbcK5ODYJHCu3bCV9Q== X-Google-Smtp-Source: APXvYqwDQl18IQOIxN+PmKh6NJ2bnS4vnkB8EXUiQXwPxAbV31eZwm2r0TxIfMBcbK3m2x7wzpuQNg== X-Received: by 2002:a9d:5cc2:: with SMTP id r2mr6500527oti.122.1559680484677; Tue, 04 Jun 2019 13:34:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:44 -0500 Message-Id: <20190604203351.27778-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 32/39] cpu: Introduce cpu_set_cpustate_pointers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Consolidate some boilerplate from foo_cpu_initfn. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 11 +++++++++++ target/alpha/cpu.c | 3 +-- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 4 +--- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 6 ++---- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 9 +++++---- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 4 +--- target/tricore/cpu.c | 4 +--- target/unicore32/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 22 files changed, 37 insertions(+), 48 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c62f07b354..71154070a7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong ad= dr, =20 int cpu_exec(CPUState *cpu); =20 +/** + * cpu_set_cpustate_pointers(cpu) + * @cpu: The cpu object + * + * Set the generic pointers in CPUState into the outer object. + */ +static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) +{ + cpu->parent_obj.env_ptr =3D &cpu->env; +} + /** * env_archcpu(env) * @env: The architecture environment diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7c81be4111..952582567f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -191,11 +191,10 @@ static void ev67_cpu_initfn(Object *obj) =20 static void alpha_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); AlphaCPU *cpu =3D ALPHA_CPU(obj); CPUAlphaState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b23ac2c93..f70e07fd11 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -697,10 +697,9 @@ static void cpreg_hashtable_data_destroy(gpointer data) =20 static void arm_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); ARMCPU *cpu =3D ARM_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, g_free, cpreg_hashtable_data_dest= roy); =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4e5288ae80..1dce6d10c3 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -172,12 +172,11 @@ static void cris_disas_set_info(CPUState *cpu, disass= emble_info *info) =20 static void cris_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); CRISCPU *cpu =3D CRIS_CPU(obj); CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->pregs[PR_VR] =3D ccc->vr; =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9717ea1798..ae494abad1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_cpu_initfn(Object *obj) HPPACPU *cpu =3D HPPA_CPU(obj); CPUHPPAState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a461d8d92c..b21ecaac17 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5592,13 +5592,12 @@ static void x86_cpu_get_crash_info_qom(Object *obj,= Visitor *v, =20 static void x86_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; FeatureWord w; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "family", "int", x86_cpuid_version_get_family, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 57c50c1578..a14191236f 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -142,11 +142,10 @@ static void lm32_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void lm32_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); LM32CPU *cpu =3D LM32_CPU(obj); CPULM32State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->flags =3D 0; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b16957934a..ea38cb46e9 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -238,11 +238,9 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error= **errp) =20 static void m68k_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); M68kCPU *cpu =3D M68K_CPU(obj); - CPUM68KState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static const VMStateDescription vmstate_m68k_cpu =3D { diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 0ea549910b..5c537526c0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -221,11 +221,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error = **errp) =20 static void mb_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); CPUMBState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a33058609a..73232b80ad 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -152,12 +152,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void mips_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(obj); CPUMIPSState *env =3D &cpu->env; MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); env->cpu_model =3D mcc->cpu_def; } =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 02b2b47574..4688cee8c1 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -74,10 +74,9 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error = **errp) =20 static void moxie_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); MoxieCPU *cpu =3D MOXIE_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 186af4913d..b00223e0c7 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -66,14 +66,12 @@ static void nios2_cpu_reset(CPUState *cs) =20 static void nios2_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); Nios2CPU *cpu =3D NIOS2_CPU(obj); - CPUNios2State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 #if !defined(CONFIG_USER_ONLY) - mmu_init(env); + mmu_init(&cpu->env); #endif } =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 3816baee70..d5b0134371 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,9 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 static void openrisc_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 /* CPU models */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index d161e95fb2..b71b7bac20 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10473,12 +10473,11 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) =20 static void ppc_cpu_instance_init(Object *obj) { - CPUState *cs =3D CPU(obj); PowerPCCPU *cpu =3D POWERPC_CPU(obj); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cpu->vcpu_id =3D UNASSIGNED_CPU_INDEX; =20 env->msr_mask =3D pcc->msr_mask; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e29879915f..86fd8693a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -367,10 +367,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 static void riscv_cpu_init(Object *obj) { - CPUState *cs =3D CPU(obj); RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - cs->env_ptr =3D &cpu->env; + cpu_set_cpustate_pointers(cpu); } =20 static const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b1df63d82c..9ee166d873 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -282,17 +282,18 @@ static void s390_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); S390CPU *cpu =3D S390_CPU(obj); - CPUS390XState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; object_property_add(obj, "crash-information", "GuestPanicInformation", s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NUL= L); s390_cpu_model_register_props(obj); #if !defined(CONFIG_USER_ONLY) - env->tod_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, c= pu); - env->cpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, c= pu); + cpu->env.tod_timer =3D + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); + cpu->env.cpu_timer =3D + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); #endif } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index c4736a0a73..dfca03f266 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -194,11 +194,10 @@ static void superh_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void superh_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); SuperHCPU *cpu =3D SUPERH_CPU(obj); CPUSH4State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 env->movcal_backup_tail =3D &(env->movcal_backup); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f93ce72eb9..ad2c362c6a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -774,12 +774,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 static void sparc_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); SPARCCPU *cpu =3D SPARC_CPU(obj); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 if (scc->cpu_def) { env->def =3D *scc->cpu_def; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index b209c55387..3567a2b664 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -100,11 +100,9 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 static void tilegx_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); TileGXCPU *cpu =3D TILEGX_CPU(obj); - CPUTLGState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static void tilegx_cpu_do_interrupt(CPUState *cs) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index ea1199d27e..8624103674 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -104,11 +104,9 @@ static void tricore_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void tricore_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); TriCoreCPU *cpu =3D TRICORE_CPU(obj); - CPUTriCoreState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); } =20 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 3f57c508a0..451082bbe6 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -103,11 +103,10 @@ static void uc32_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 static void uc32_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); UniCore32CPU *cpu =3D UNICORE32_CPU(obj); CPUUniCore32State *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); =20 #ifdef CONFIG_USER_ONLY env->uncached_asr =3D ASR_MODE_USER; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c79dc75bfe..f3ec66e242 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -138,12 +138,11 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Er= ror **errp) =20 static void xtensa_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); XtensaCPU *cpu =3D XTENSA_CPU(obj); XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; =20 - cs->env_ptr =3D env; + cpu_set_cpustate_pointers(cpu); env->config =3D xcc->config; =20 #ifndef CONFIG_USER_ONLY --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=RFNas4A/KzQEOFTRNZEH7vXo29C+TS62qwiVCmcIbQg=; b=gL8TjBqB+oXwMIeGSXtyXVPthGVN7N6OOO0sOzUP9wF/gkioM7a5qpUlFx7kpA34zx Yebs+7B6Pr5gpLwnPqvrWZlUWaK9Exl1XRfk7er3e7uGHrwOs9LC5j4KTIH2cFtlKHzE HIGkHY7xdGEXZG+Q3SrBR5HQXHAiAAzIdX5Vpcvarj1wEcG6uiEiC68zX4FLN8fjAEx4 JtlllH+k8Ywhhlwa3pPeUqpVSUZyB2cPPtMedr/uPqQe0svLjhQUZbAP+sFckkQGVDuM AzLoVMIQ3sI9wipn7LmMY1lm3GCX3stpDO7iYKc9gQtCd7lhA6K/E7qlhF4opX04mlWS Ulfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=RFNas4A/KzQEOFTRNZEH7vXo29C+TS62qwiVCmcIbQg=; b=jaFCEWOCcAWFJ7xyJRh0kn5ZrTlvpZKpZCaSmVMsdVn01MG8munCocgd7EsWcMM7sD sQAM/xTcHBah3VLLN6PS7KmBnageGa3St/l6RB7NfD0dtoLYYtkPNRHD4X//jGAjxPo0 CZRmev7gdYNrkcbgBAO0PZw5nw2JmmB2oy/7Hy9ZbMRpsleBKvbtBDh5/6hbcLhfVwi8 XHoUCU2cCAQ9BoIDrnLTiRxdfyM9kPGSxK7Jl5YJ7zLDNbRPscTSlEpbr9BvKBfrWg44 wnlUWIHS3WQ+EAurLpDNDufrpg9ol9YCVQue0B22z08K2/9abVebziutJ8ktFcju2CPe 3rkQ== X-Gm-Message-State: APjAAAVhcG9/KEL4hPgBV0PoOWbpDEI/RL6JEPUU+Wm+yOAKrVRw8aoi EUXxZZ/5fmgeqolTVGxVVtPPeQKM1jQkFQ== X-Google-Smtp-Source: APXvYqxT6pMkjjQ/sq7tYjjJ9gVXZG+QnjwRtzoVN2XDhv1Kpu+BGogQDFcbru/9OxBYUVHHeML9jA== X-Received: by 2002:a9d:57c6:: with SMTP id q6mr28432oti.17.1559680485964; Tue, 04 Jun 2019 13:34:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:45 -0500 Message-Id: <20190604203351.27778-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v4 33/39] cpu: Introduce CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 24 ++++++++++++++++++++++++ include/exec/cpu-defs.h | 8 ++++++++ target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/cris/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/lm32/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 5 +++-- target/mips/cpu.h | 1 + target/moxie/cpu.h | 1 + target/nios2/cpu.h | 2 ++ target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 2 ++ target/riscv/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tilegx/cpu.h | 1 + target/tricore/cpu.h | 1 + target/unicore32/cpu.h | 1 + target/xtensa/cpu.h | 1 + 23 files changed, 57 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 71154070a7..5ae83405c8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -404,4 +404,28 @@ static inline CPUState *env_cpu(CPUArchState *env) return &env_archcpu(env)->parent_obj; } =20 +/** + * env_neg(env) + * @env: The architecture environment + * + * Return the CPUNegativeOffsetState associated with the environment. + */ +static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) +{ + ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); + return &arch_cpu->neg; +} + +/** + * cpu_neg(cpu) + * @cpu: The generic CPUState + * + * Return the CPUNegativeOffsetState associated with the cpu. + */ +static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) +{ + ArchCPU *arch_cpu =3D container_of(cpu, ArchCPU, parent_obj); + return &arch_cpu->neg; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index b9ec261b01..921fbb4c36 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -227,4 +227,12 @@ typedef struct CPUTLB { =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 +/* + * This structure must be placed in ArchCPU immedately + * before CPUArchState, as a field named "neg". + */ +typedef struct CPUNegativeOffsetState { + /* Empty */ +} CPUNegativeOffsetState; + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 361f85c976..94fbc00a3b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -272,6 +272,7 @@ struct AlphaCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUAlphaState env; =20 /* This alarm doesn't exist in real hardware; we wish it did. */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index abe6fce7ab..5965c52f0c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,6 +721,7 @@ struct ARMCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUARMState env; =20 /* Coprocessor information */ diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 83c350377a..ad93d1a9ee 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -180,6 +180,7 @@ struct CRISCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUCRISState env; }; =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7f9f54731b..f7c6205218 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -218,6 +218,7 @@ struct HPPACPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUHPPAState env; QEMUTimer *alarm_timer; }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3a155c12d3..e7580a86e5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1369,6 +1369,7 @@ struct X86CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUX86State env; =20 bool hyperv_vapic; diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 2c934472d6..324bc90f81 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -186,6 +186,7 @@ struct LM32CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPULM32State env; =20 uint32_t revision; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4006663494..d92263b750 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -160,6 +160,7 @@ struct M68kCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUM68KState env; }; =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a17c12ca2f..d90c4fbcb5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -287,6 +287,9 @@ struct MicroBlazeCPU { =20 /*< public >*/ =20 + CPUNegativeOffsetState neg; + CPUMBState env; + /* Microblaze Configuration Settings */ struct { bool stackprot; @@ -306,8 +309,6 @@ struct MicroBlazeCPU { char *version; uint8_t pvr; } cfg; - - CPUMBState env; }; =20 =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 24fe25f61c..62af24937d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1068,6 +1068,7 @@ struct MIPSCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUMIPSState env; }; =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 3d418c8f1d..c6b681531d 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -87,6 +87,7 @@ typedef struct MoxieCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUMoxieState env; } MoxieCPU; =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c96d797dda..8cc3d4971e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -182,7 +182,9 @@ typedef struct Nios2CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUNios2State env; + bool mmu_present; uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 39e2765aa2..51723e9312 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -313,8 +313,8 @@ typedef struct OpenRISCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUOpenRISCState env; - } OpenRISCCPU; =20 =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 73b92c189c..e8962e4655 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1184,7 +1184,9 @@ struct PowerPCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUPPCState env; + int vcpu_id; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d9611eaced..0ed7031915 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -210,6 +210,7 @@ typedef struct RISCVCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPURISCVState env; =20 /* Configuration Settings */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 971dc0ccbd..ebcf7863e4 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -156,6 +156,7 @@ struct S390CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUS390XState env; S390CPUModel *model; /* needed for live migration */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 610a8db6de..e266db411f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,6 +204,7 @@ struct SuperHCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUSH4State env; }; =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 0cc36873ce..a3c4f47d40 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -529,6 +529,7 @@ struct SPARCCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUSPARCState env; }; =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 643b7dbd17..deb3e836ea 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -135,6 +135,7 @@ typedef struct TileGXCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUTLGState env; } TileGXCPU; =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 9f45bb5c24..03b293c1f6 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -205,6 +205,7 @@ struct TriCoreCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUTriCoreState env; }; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index c1130e9548..39beb32366 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -73,6 +73,7 @@ struct UniCore32CPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUUniCore32State env; }; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e89605747a..e2d7e8371d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -556,6 +556,7 @@ struct XtensaCPU { CPUState parent_obj; /*< public >*/ =20 + CPUNegativeOffsetState neg; CPUXtensaState env; }; =20 --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=PYpVsDECn50S2iyRZN0fZ1fEzaZW8+7DmxjFRcVQ65o=; b=SNgfQUeHb6yhrsOM1h+GkXlqqOeqNSivVzYqCTW5ewigzePOuzkVVjdvjODC9RAB50 UcQdCe5CunAL4AuQa2DPFHXqbi8qAyvM2QWxcaH/j2pbMegxyKJPd51s+WWWl0riwuXN 39I9/VpK8fw8m6dfP0we9ArVuDsUcG1mrTNLOHr9T/cXc0naffcB003e70J035SPh8AR k6xMqoVzHSqe4Rff9xTHa5iTaPlr4lqmu9+cT98vRKLed5Ur+/QfWLVys9RotpOvh/bI 3O750k5IJn/LE+u1cUr4UL15AIp8FURl2ccqp9zj7Y5HOMG98L1thM2u2J0tBUCGEoks L9Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PYpVsDECn50S2iyRZN0fZ1fEzaZW8+7DmxjFRcVQ65o=; b=J9sJypf2eCh5Ju1+xc5uNJ1sauqGFU7OZ38VxnVqNU7JALu8KGiL+1onaN8kFr+e69 7QOGMd1YFSlguerM3+jktDrHfdCZggjm9D4xLlFZeGlXaYGl8mCC9lIXkQfAPvJWUzfG 0S+mB7cL9sZLXY5pv2hePEt7Szqvr82EELc4Pgvba5+8kA+8hErMMBku9IJpYSu2h3o1 6Hwo2AD8HK1y4Ofi9W28Xx7OUklY4+FWxuoWIBHNG2HsalwCtEbDqpQ7JDGn3hZOrWyd SOF/LEsRU34NVYiNsTaHDyLCsFbmb14cpYljsNSXCXts4wrlApv03DyzLoyFF3a4uhj4 2jDg== X-Gm-Message-State: APjAAAX3vU27TYmDf5e533q7zG6XM8MCynaVUDSUErFT7iudhAZnKmL+ mKVMVvT2s3GvyR+KyEhiYd6XSjIaw96wyQ== X-Google-Smtp-Source: APXvYqznvEFzA5gQZa/9Q11QrqcT2qA6jImT/ejQQ4ReafIQfXdFy5DqknPms/EFbsf40PA2IKOowQ== X-Received: by 2002:a9d:4c17:: with SMTP id l23mr6516898otf.367.1559680487251; Tue, 04 Jun 2019 13:34:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:46 -0500 Message-Id: <20190604203351.27778-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 34/39] cpu: Move icount_decr to CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Amusingly, we had already ignored the comment to keep this value at the end of CPUState. This restores the minimum negative offset from TCG_AREG0 for code generation. For the couple of uses within qom/cpu.c, without NEED_CPU_H, add a pointer from the CPUState object to the IcountDecr object within CPUNegativeOffsetState. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 + include/exec/cpu-defs.h | 3 ++- include/exec/gen-icount.h | 16 ++++++++++------ include/qom/cpu.h | 40 ++++++++++++++++++--------------------- accel/tcg/cpu-exec.c | 23 +++++++++++----------- accel/tcg/tcg-all.c | 6 ++---- accel/tcg/translate-all.c | 8 ++++---- cpus.c | 9 +++++---- qom/cpu.c | 4 ++-- 9 files changed, 56 insertions(+), 54 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5ae83405c8..253dd1d9a5 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -380,6 +380,7 @@ int cpu_exec(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr =3D &cpu->env; + cpu->parent_obj.icount_decr_ptr =3D &cpu->neg.icount_decr; } =20 /** diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 921fbb4c36..c067994e5c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -33,6 +33,7 @@ #include "exec/hwaddr.h" #endif #include "exec/memattrs.h" +#include "qom/cpu.h" =20 #include "cpu-param.h" =20 @@ -232,7 +233,7 @@ typedef struct CPUTLB { * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { - /* Empty */ + IcountDecr icount_decr; } CPUNegativeOffsetState; =20 #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9cfa6ccce5..f7669b6841 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,8 +5,6 @@ =20 /* Helpers for instruction counting code generation. */ =20 -#define ENV_OFFSET offsetof(ArchCPU, env) - static TCGOp *icount_start_insn; =20 static inline void gen_tb_start(TranslationBlock *tb) @@ -21,7 +19,8 @@ static inline void gen_tb_start(TranslationBlock *tb) } =20 tcg_gen_ld_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); + offsetof(ArchCPU, neg.icount_decr.u32) - + offsetof(ArchCPU, env)); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { imm =3D tcg_temp_new_i32(); @@ -39,7 +38,8 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, - -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); + offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, env)); } =20 tcg_temp_free_i32(count); @@ -60,14 +60,18 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } =20 static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_i= o)); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); tcg_temp_free_i32(tmp); } =20 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 98e12d914c..5ee0046b62 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -232,17 +232,25 @@ typedef struct CPUClass { bool gdb_stop_before_watchpoint; } CPUClass; =20 +/* + * Low 16 bits: number of cycles left, used only in icount mode. + * High 16 bits: Set to -1 to force TCG to stop executing linked TBs + * for this CPU and return to its top level loop (even in non-icount mode). + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. + */ +typedef union IcountDecr { + uint32_t u32; + struct { #ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; + uint16_t high; + uint16_t low; #else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; + uint16_t low; + uint16_t high; #endif + } u16; +} IcountDecr; =20 typedef struct CPUBreakpoint { vaddr pc; @@ -314,11 +322,6 @@ struct qemu_work_item; * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. - * @icount_decr: Low 16 bits: number of cycles left, only used in icount m= ode. - * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for t= his - * CPU and return to its top level loop (even in non-icount mode). - * This allows a single read-compare-cbranch-write sequence to test - * for both decrementer underflow and exceptions. * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution * requires that IO only be performed on the last instruction of a TB * so that interrupts take effect immediately. @@ -328,6 +331,7 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets = which * only have a single AddressSpace * @env_ptr: Pointer to subclass-specific CPUArchState field. + * @icount_decr_ptr: Pointer to IcountDecr field within subclass. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -387,6 +391,7 @@ struct CPUState { MemoryRegion *memory; =20 void *env_ptr; /* CPUArchState */ + IcountDecr *icount_decr_ptr; =20 /* Accessed in parallel; all accesses must be atomic */ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; @@ -441,15 +446,6 @@ struct CPUState { =20 bool ignore_memory_transaction_failures; =20 - /* Note that this is accessed at the start of every TB via a negative - offset from AREG0. Leave this field at the end so as to make the - (absolute value) offset as small as possible. This reduces code - size, especially for hosts without large memory offsets. */ - union { - uint32_t u32; - icount_decr_u16 u16; - } icount_decr; - struct hax_vcpu_state *hax_vcpu; =20 int hvf_fd; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 45ef41ebb2..032a62672e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -54,7 +54,7 @@ typedef struct SyncClocks { #define MAX_DELAY_PRINT_RATE 2000000000LL #define MAX_NB_PRINTS 100 =20 -static void align_clocks(SyncClocks *sc, const CPUState *cpu) +static void align_clocks(SyncClocks *sc, CPUState *cpu) { int64_t cpu_icount; =20 @@ -62,7 +62,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *= cpu) return; } =20 - cpu_icount =3D cpu->icount_extra + cpu->icount_decr.u16.low; + cpu_icount =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; sc->diff_clk +=3D cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount =3D cpu_icount; =20 @@ -105,15 +105,15 @@ static void print_delay(const SyncClocks *sc) } } =20 -static void init_delay_params(SyncClocks *sc, - const CPUState *cpu) +static void init_delay_params(SyncClocks *sc, CPUState *cpu) { if (!icount_align_option) { return; } sc->realtime_clock =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_= clock; - sc->last_cpu_icount =3D cpu->icount_extra + cpu->icount_decr.u16.low; + sc->last_cpu_icount + =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay =3D sc->diff_clk; } @@ -467,7 +467,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu->icount_decr.u16.low + cpu->icount_extra =3D=3D 0) { + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0) { /* try to cause an exception pending in the log */ cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()),= true); } @@ -525,7 +525,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ - atomic_mb_set(&cpu->icount_decr.u16.high, 0); + atomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0); =20 if (unlikely(atomic_read(&cpu->interrupt_request))) { int interrupt_request; @@ -596,8 +596,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 /* Finally, check if we need to exit to the main loop. */ - if (unlikely(atomic_read(&cpu->exit_request) - || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0))) { + if (unlikely(atomic_read(&cpu->exit_request)) + || (use_icount + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0)) { atomic_set(&cpu->exit_request, 0); if (cpu->exception_index =3D=3D -1) { cpu->exception_index =3D EXCP_INTERRUPT; @@ -624,7 +625,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, } =20 *last_tb =3D NULL; - insns_left =3D atomic_read(&cpu->icount_decr.u32); + insns_left =3D atomic_read(&cpu_neg(cpu)->icount_decr.u32); if (insns_left < 0) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit @@ -643,7 +644,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, cpu_update_icount(cpu); /* Refill decrementer and continue execution. */ insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low =3D insns_left; + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; if (!cpu->icount_extra) { /* Execute any remaining instructions, then let the main loop diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 3d25bdcc17..9b215dcc5a 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,13 +28,12 @@ #include "sysemu/sysemu.h" #include "qom/object.h" #include "qemu-common.h" -#include "qom/cpu.h" +#include "cpu.h" #include "sysemu/cpus.h" #include "qemu/main-loop.h" =20 unsigned long tcg_tb_size; =20 -#ifndef CONFIG_USER_ONLY /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -51,7 +50,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); if (use_icount && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { @@ -59,7 +58,6 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } } } -#endif =20 static int tcg_init(MachineState *ms) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 52d94facf0..e24ee3a172 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -364,7 +364,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, assert(use_icount); /* Reset the cycle counter to the start of the block and shift if to the number of actually executed instructions */ - cpu->icount_decr.u16.low +=3D num_insns - i; + cpu_neg(cpu)->icount_decr.u16.low +=3D num_insns - i; } restore_state_to_opc(env, tb, data); =20 @@ -2200,7 +2200,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 && env->active_tc.PC !=3D tb->pc) { env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->hflags &=3D ~MIPS_HFLAG_BMASK; n =3D 2; } @@ -2208,7 +2208,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 && env->pc !=3D tb->pc) { env->pc -=3D 2; - cpu->icount_decr.u16.low++; + cpu_neg(cpu)->icount_decr.u16.low++; env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); n =3D 2; } @@ -2382,7 +2382,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |=3D mask; - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } =20 /* diff --git a/cpus.c b/cpus.c index ffc57119ca..111ca4ed1c 100644 --- a/cpus.c +++ b/cpus.c @@ -239,7 +239,8 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp) */ static int64_t cpu_get_icount_executed(CPUState *cpu) { - return cpu->icount_budget - (cpu->icount_decr.u16.low + cpu->icount_ex= tra); + return (cpu->icount_budget - + (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra)); } =20 /* @@ -1389,12 +1390,12 @@ static void prepare_icount_for_run(CPUState *cpu) * each vCPU execution. However u16.high can be raised * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ - g_assert(cpu->icount_decr.u16.low =3D=3D 0); + g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 cpu->icount_budget =3D tcg_get_icount_limit(); insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu->icount_decr.u16.low =3D insns_left; + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; =20 replay_mutex_lock(); @@ -1408,7 +1409,7 @@ static void process_icount_data(CPUState *cpu) cpu_update_icount(cpu); =20 /* Reset the counters */ - cpu->icount_decr.u16.low =3D 0; + cpu_neg(cpu)->icount_decr.u16.low =3D 0; cpu->icount_extra =3D 0; cpu->icount_budget =3D 0; =20 diff --git a/qom/cpu.c b/qom/cpu.c index 3c5493c96c..6b4632abda 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -115,7 +115,7 @@ void cpu_exit(CPUState *cpu) atomic_set(&cpu->exit_request, 1); /* Ensure cpu_exec will see the exit request after TCG has exited. */ smp_wmb(); - atomic_set(&cpu->icount_decr.u16.high, -1); + atomic_set(&cpu->icount_decr_ptr->u16.high, -1); } =20 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -264,7 +264,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc =3D 0; cpu->mem_io_vaddr =3D 0; cpu->icount_extra =3D 0; - atomic_set(&cpu->icount_decr.u32, 0); + atomic_set(&cpu->icount_decr_ptr->u32, 0); cpu->can_do_io =3D 1; cpu->exception_index =3D -1; cpu->crash_occurred =3D false; --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681961; cv=none; d=zoho.com; s=zohoarc; b=keKWjwq569Kq6V9PtRRl4Tiw1zKYV7WRkIquGPDAbpRR/fFbhL68yKeOvb62lNK3yRZTtOPQUca4RD+ZW1YvwSqf1yr4fo3KVnJ2mMHWuycoUzdXMuIGv3bQCoLxQ318LCaYrqyWOcZoizZQfVC1JQGSpGLGbonYr9H95c4g4tc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559681961; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jdrDk/bUIVKCAYFx0I8wpHfDUmzdUpIyWvwMFMVbpV8=; b=eipw4zWp4v9OWe6UVkboy9h36qM2XbTcMMPzJFrU5/yjlRGYWjvQN99T0XL6pOrDMLkL7zj5XTzqyHiAxeoHtBaCiuCxHFVifLzvmh0XAjcdkQiuuDus8e2yZ0Cs7Wc3YVmR01/yQ3Ozppk2YIRIksvBqPPn4euvF0oymaCmBhs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559681960982214.264838461585; Tue, 4 Jun 2019 13:59:20 -0700 (PDT) Received: from localhost ([127.0.0.1]:57946 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGWR-0005DH-Og for importer@patchew.org; Tue, 04 Jun 2019 16:59:07 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG93-0001gQ-EZ for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:35:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG8z-0004ta-JQ for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:57 -0400 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:39554) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG8y-0004pP-AR for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:53 -0400 Received: by mail-ot1-x344.google.com with SMTP id r21so8385466otq.6 for ; Tue, 04 Jun 2019 13:34:50 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=jdrDk/bUIVKCAYFx0I8wpHfDUmzdUpIyWvwMFMVbpV8=; b=ympVh5ooS1M1MpVb8Mpm7hdsLg7HgN6ma5cS2xuxgoaHgX7J4GisS7SZC0RhQCIntq giBn9XAD8ypR3IMFdVbDYjvxasCNNqPQSTbuqcCHkfJ7bICyX1mUSLNp+N04yXRiy8ss EWOYjQs0xHVQDqlITMcfOwUfGyXx5fSDN7embRB+9rZYAi1NZgpsRFXEU1bhiut9i4Ur hL2XHauigvLVNRoRBw0P1aCtFT5Cn0r4FlShSPUM2AEBCsJOvtzS3TMtJ/NVa2Y42Kp9 /e1lDEbSJnmUEd5IeAYwRHE4GC7TcpwIlV63vc/M23WVkPmja0j5R5oWdMDuKEOBjtv0 kwOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=jdrDk/bUIVKCAYFx0I8wpHfDUmzdUpIyWvwMFMVbpV8=; b=qG7EobtUVA1CLpTgpCncaAyC7XFFSdjnKHP3RTR1sTyDX21xo4oCwhGrxaxZr5D/Do hbXULQ3pmY8bJb1A6wEVaA5dSmAwDLtwBSbyfsYEAcphb+rb9O3eFLbvM7TXLhRGp0Xz v9gQMyT/H95rUGddJDD5lqOVFOAFi2z+erNdsie5kajhrP2WacVaXDybGuwaArSgi7fS GlIOE81nXsqcm18LMEYCQset2CEMBhT0JQ9aKR5siMtgCHptCxwV4sFe+saPElA4ofVI MPCk1ZDHpmvFS1gUWuSEbgjo3J4JYn0NpnDgnC6a02061E3HgJQPRKcy/lMdwmN5veMT HSNA== X-Gm-Message-State: APjAAAUXEVc4wKxead9cpdwY+bSt37kbATJkjbGyG7jP+1bYPzt78YT/ fe6zWK0K5rkde3fKGX5Y2oGFwroxxTgAmg== X-Google-Smtp-Source: APXvYqyoi0VbDyZBx+kNG+sgfRzZ5ge5bAgChG/FFbmbltDyUJROY1g2J9hdEpk02rdcPkRhroMaDQ== X-Received: by 2002:a9d:4008:: with SMTP id m8mr373771ote.200.1559680488931; Tue, 04 Jun 2019 13:34:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:47 -0500 Message-Id: <20190604203351.27778-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 35/39] cpu: Move the softmmu tlb to CPUNegativeOffsetState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have for some time had code within the tcg backends to handle large positive offsets from env. This move makes sure that need not happen. Indeed, we are able to assert at build time that simple offsets suffice for all hosts. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 +++++++++++++------- tcg/aarch64/tcg-target.inc.c | 29 ++++++-------------------- tcg/arm/tcg-target.inc.c | 40 ++++++++---------------------------- tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 39 ++++++++--------------------------- tcg/ppc/tcg-target.inc.c | 30 ++++++++------------------- tcg/riscv/tcg-target.inc.c | 31 +++++++--------------------- tcg/s390/tcg-target.inc.c | 11 +++++----- tcg/sparc/tcg-target.inc.c | 32 +++++++++-------------------- 9 files changed, 74 insertions(+), 166 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c067994e5c..ac1aa9a1b6 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -178,13 +178,14 @@ typedef struct CPUTLBDesc { =20 /* * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. */ typedef struct CPUTLBDescFast { /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ uintptr_t mask; /* The array of tlb entries itself. */ CPUTLBEntry *table; -} CPUTLBDescFast; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); =20 /* * Data elements that are shared between all MMU modes. @@ -211,28 +212,35 @@ typedef struct CPUTLBCommon { /* * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. */ typedef struct CPUTLB { - CPUTLBDescFast f[NB_MMU_MODES]; - CPUTLBDesc d[NB_MMU_MODES]; CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; =20 -/* There are target-specific members named "tlb". This is temporary. */ -#define CPU_COMMON CPUTLB tlb_; -#define env_tlb(ENV) (&(ENV)->tlb_) +#define env_tlb(ENV) (&env_neg(ENV)->tlb) + +/* This will be used by TCG backends to compute offsets. */ +#define TLB_MASK_TABLE_OFS(IDX) \ + ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) =20 #else =20 -#define CPU_COMMON /* Nothing */ +typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 +#define CPU_COMMON /* Nothing */ + /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { + CPUTLB tlb; IcountDecr icount_decr; } CPUNegativeOffsetState; =20 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 90957593a3..57c297f9d7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1637,9 +1637,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -/* We expect to use a 24-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xffffff); +/* We expect to use a 7-bit scaled negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); =20 /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finali= zing @@ -1649,8 +1649,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg ad= dr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int mask_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_ofs =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; @@ -1659,24 +1660,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg a= ddr_reg, TCGMemOp opc, TCGType mask_type; uint64_t compare_mask; =20 - if (table_ofs > 0xfff) { - int table_hi =3D table_ofs & ~0xfff; - int mask_hi =3D mask_ofs & ~0xfff; - - table_base =3D TCG_REG_X1; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_X0; - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - mask_base, TCG_AREG0, mask_hi); - } - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, - table_base, TCG_AREG0, table_hi); - mask_ofs -=3D mask_hi; - table_ofs -=3D table_hi; - } - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 38de6d59c7..b066e30f0e 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1220,9 +1220,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg= argreg, =20 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 -/* We expect to use a 20-bit unsigned offset from ENV. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0xfffff); +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); =20 /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ @@ -1232,39 +1232,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0xfff) { - int mask_hi =3D mask_off & ~0xfff; - int table_hi =3D table_off & ~0xfff; - int rot; - - table_base =3D TCG_REG_R2; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_TMP; - rot =3D encode_imm(mask_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0, - rotl(mask_hi, rot) | (rot << 7)); - } - rot =3D encode_imm(table_hi); - assert(rot >=3D 0); - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0, - rotl(table_hi, rot) | (rot << 7)); - - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); =20 /* Extract the tlb index from the address into TMP. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5f5b886c04..6ddeebf4bc 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,10 +1730,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].mask)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - offsetof(CPUArchState, tlb_.f[mem_index].table)); + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); =20 /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ef6633587e..41bff32fb4 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1202,6 +1202,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int= i, TCGReg al, TCGReg ah) return i; } =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* * Perform the tlb comparison operation. * The complete host address is placed in BASE. @@ -1215,42 +1219,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; target_ulong mask; =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_TMP1; - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base; - tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >= > 16); - tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0= ); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - if (mask_hi !=3D 0) { - mask_base =3D TCG_TMP0; - tcg_out_opc_imm(s, OPC_LUI, - mask_base, TCG_REG_ZERO, mask_hi >> 16); - tcg_out_opc_reg(s, ALIAS_PADD, - mask_base, mask_base, TCG_AREG0); - } - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_of= f); - } - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 /* Extract the TLB index from the address into TMP3. */ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d69c18ac1e..852b8940fb 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1498,6 +1498,10 @@ static void * const qemu_st_helpers[16] =3D { [MO_BEQ] =3D helper_be_stq_mmu, }; =20 +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ @@ -1510,31 +1514,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =3D (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - if (table_off > 0x7fff) { - int mask_hi =3D mask_off - (int16_t)mask_off; - int table_hi =3D table_off - (int16_t)table_off; - - table_base =3D TCG_REG_R4; - if (mask_hi =3D=3D table_hi) { - mask_base =3D table_base; - } else if (mask_hi) { - mask_base =3D TCG_REG_R3; - tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16)); - } - tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16)); - mask_off -=3D mask_hi; - table_off -=3D table_hi; - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 96c33bf621..1f0ae64aae 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -962,6 +962,10 @@ static void * const qemu_st_helpers[16] =3D { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); =20 +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -971,32 +975,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; int mem_index =3D get_mmuidx(oi); - int mask_off, table_off; + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; =20 - mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - if (table_off > 0x7ff) { - int mask_hi =3D mask_off - sextreg(mask_off, 0, 12); - int table_hi =3D table_off - sextreg(table_off, 0, 12); - - if (likely(mask_hi =3D=3D table_hi)) { - mask_base =3D table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - mask_off -=3D mask_hi; - table_off -=3D mask_hi; - } else { - mask_base =3D TCG_REG_TMP0; - table_base =3D TCG_REG_TMP1; - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi); - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0); - table_off -=3D mask_off; - mask_off -=3D mask_hi; - tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off); - } - } - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 4d896d0b58..fe42939d98 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1538,9 +1538,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" =20 -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table) - > 0x7ffff); +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. = */ @@ -1551,8 +1551,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg = addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; uint64_t tlb_mask; =20 diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 066cb0e892..10b1cea63b 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1062,6 +1062,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) } =20 #if defined(CONFIG_SOFTMMU) + +/* We expect to use a 13-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + /* Perform the TLB load and compare. =20 Inputs: @@ -1078,9 +1083,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, TCGMemOp opc, int which) { - int mask_off =3D offsetof(CPUArchState, tlb_.f[mem_index].mask); - int table_off =3D offsetof(CPUArchState, tlb_.f[mem_index].table); - TCGReg base =3D TCG_AREG0; + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); const TCGReg r0 =3D TCG_REG_O0; const TCGReg r1 =3D TCG_REG_O1; const TCGReg r2 =3D TCG_REG_O2; @@ -1088,26 +1093,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addr, int mem_index, unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; =20 - if (!check_fit_i32(table_off, 13)) { - int table_hi; - - base =3D r1; - if (table_off <=3D 2 * 0xfff) { - table_hi =3D 0xfff; - tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD); - } else { - table_hi =3D table_off & ~0x3ff; - tcg_out_sethi(s, base, table_hi); - tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD); - } - mask_off -=3D table_hi; - table_off -=3D table_hi; - tcg_debug_assert(check_fit_i32(mask_off, 13)); - } - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=h67pDbY19Cg4UtoQKX9gtRcpiPsg13J7hEg0ny3fNUo=; b=wsfe2ZDcMtOBg9wNOkf4IxyOAm5CNy8D+xcEBcaNKWt5Cs43ThJi5+hJaFKgPpLbLy GKAWlYyPXCNSQNyWtMJsdRj7RX8g2uUihv3yend6wPV66d7BOSWMQh+UiiL+2kqDrHFm JHFgCu3pdKXhlXQ3AQuX6lCHOajw9e/RDDWTmjivKOS5Mp000JprDDZIneB3TKG8Q29P XZ/Q5GExLzD3jfu9bOgEqdweHwKBO7KPP2elJ6KCdog7KzDh0R5KJ1b5+jYIiPLhn3jx ME/HEDWK7AwkI3lTpMYdpBZTMrnhALgNbR1/MUajkZza5eWU/v6B2KJD5DC8EhF5aN80 TWAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=h67pDbY19Cg4UtoQKX9gtRcpiPsg13J7hEg0ny3fNUo=; b=cUcnVUjQ3EUPk/0JRC4AeqxnSrh5vxDGQduXprR65h95m94MWu/aBm9UNvqMG+pZBg dk3hJ+Bzxle9PtroJqti1XV5gJFo95+8aytBpfuNx9xFqbdwZ4LhX49tq30sUDec5H09 f5JshY8ttZJorv/1CVWeNGfciU0gFRrmNiVYDjg7lb/CeyVzX1Gfu6BbiZ54W9c2sqy2 TIIG9nOlU5Txw+g30gxqODqs5TnOqvb66tj3VGJ0pgDpzLGJO2+CslCrPBPY2GMf0mW+ IX3tTc0NQwCcigeNiMzA/J70ba0OjIvi6LVWamFVLpN/nPYqXEu0bzU5A9PAMww/Yua6 XNmA== X-Gm-Message-State: APjAAAWmdt5EGZ4ocBKgewqMpV9KS9zmmFu1kXsp1UhP2PhQltNm6xGy LP9O2nlTJhgyRa098RXENYstorrKMcGghQ== X-Google-Smtp-Source: APXvYqzH+NCJxzZ8cUr+7DMUSH+ch61vFbFUOxy4DogVMs0UFwJpeACApFW317/r+C7EI5zmTK2fkg== X-Received: by 2002:a9d:17e1:: with SMTP id j88mr5649551otj.369.1559680490336; Tue, 04 Jun 2019 13:34:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:48 -0500 Message-Id: <20190604203351.27778-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 36/39] cpu: Remove CPU_COMMON X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 2 -- target/alpha/cpu.h | 3 --- target/arm/cpu.h | 4 +--- target/cris/cpu.h | 2 -- target/hppa/cpu.h | 3 --- target/i386/cpu.h | 4 +--- target/lm32/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/moxie/cpu.h | 3 --- target/nios2/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 3 --- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/tilegx/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/unicore32/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- 22 files changed, 2 insertions(+), 50 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ac1aa9a1b6..03914abd10 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB; =20 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 -#define CPU_COMMON /* Nothing */ - /* * This structure must be placed in ArchCPU immedately * before CPUArchState, as a field named "neg". diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 94fbc00a3b..5d6fb222b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -251,9 +251,6 @@ struct CPUAlphaState { /* This alarm doesn't exist in real hardware; we wish it did. */ uint64_t alarm_expire; =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - int error_code; =20 uint32_t features; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5965c52f0c..8fa9772c9d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -645,9 +645,7 @@ typedef struct CPUARMState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* Internal CPU feature flags. */ uint64_t features; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index ad93d1a9ee..9d2a80d995 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -163,8 +163,6 @@ typedef struct CPUCRISState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Members from load_info on are preserved across resets. */ void *load_info; } CPUCRISState; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f7c6205218..c7db2eca9a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -197,9 +197,6 @@ struct CPUHPPAState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ =20 - /* Those resources are used only in QEMU core */ - CPU_COMMON - /* ??? The number of entries isn't specified by the architecture. */ /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7580a86e5..edad6e1efb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1289,9 +1289,7 @@ typedef struct CPUX86State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - - /* Fields after CPU_COMMON are preserved across CPU reset. */ + /* Fields after this point are preserved across CPU reset. */ =20 /* processor features (e.g. for CPUID insn) */ /* Minimum level/xlevel/xlevel2, based on CPU model + features */ diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 324bc90f81..3e10a693a3 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -159,8 +159,6 @@ struct CPULM32State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d92263b750..1ebd360afb 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -143,8 +143,6 @@ typedef struct CPUM68KState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d90c4fbcb5..98b4d915d7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -266,8 +266,6 @@ struct CPUMBState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* These fields are preserved on reset. */ =20 struct { diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 62af24937d..bbf1aa8b0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1041,8 +1041,6 @@ struct CPUMIPSState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index c6b681531d..2b596d5d45 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -45,9 +45,6 @@ typedef struct CPUMoxieState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON - } CPUMoxieState; =20 #include "qom/cpu.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 8cc3d4971e..e40ee27e53 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -167,8 +167,6 @@ struct CPUNios2State { =20 uint32_t irq_pending; #endif - - CPU_COMMON }; =20 /** diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 51723e9312..9b80834d68 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ uint32_t cpucfgr; /* CPU configure register */ =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e8962e4655..c93ebc4c10 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -999,8 +999,6 @@ struct CPUPPCState { /* when a memory exception occurs, the access type is stored here */ int access_type; =20 - CPU_COMMON - /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ed7031915..a935b17dbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -171,9 +171,6 @@ struct CPURISCVState { =20 float_status fp_status; =20 - /* QEMU */ - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ }; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index ebcf7863e4..17d54f9587 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -114,8 +114,6 @@ struct CPUS390XState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - #if !defined(CONFIG_USER_ONLY) uint32_t core_id; /* PoP "CPU address", same as cpu_index */ uint64_t cpuid; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index e266db411f..08cf275f79 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -179,8 +179,6 @@ typedef struct CPUSH4State { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a3c4f47d40..49e0349a81 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -446,8 +446,6 @@ struct CPUSPARCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index deb3e836ea..c2acb43c2b 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -93,8 +93,6 @@ typedef struct CPUTLGState { =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - - CPU_COMMON } CPUTLGState; =20 #include "qom/cpu.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 03b293c1f6..52b07c73bf 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -184,8 +184,6 @@ struct CPUTriCoreState { int error_code; uint32_t hflags; /* CPU State */ =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint64_t features; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 39beb32366..6b459dacde 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State { float_status fp_status; } ucf64; =20 - CPU_COMMON - /* Internal CPU feature flags. */ uint32_t features; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index e2d7e8371d..bfc6604b76 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -541,8 +541,6 @@ typedef struct CPUXtensaState { =20 /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; - - CPU_COMMON } CPUXtensaState; =20 /** --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559681669; 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=Iz2EvZFIABjNbnkyC3UNjG2s6yNlDWo5TqN7+5GSNOs=; b=dfatdokm9TB3x/9etBxCYS6//ddPBSOkTFuV2/9BVeEkCwIt96RYqU7eeFPpRKewOu h6JP1Vko+6UiBUDHtwlFesVK9X2zknjqagphNdZZugDkxkk+39TNs3sJ2VPRT4hvBoFP 7Z2YvCeFj6ACEqeI588CI5UkfN0ZGnB0wmUl3mG5wOvde/CMSneDhA50kHq/BKFWwNWK vLB+4TqjRYDpuC+xR2xdudiuzDwqnbaDVlIhKNllUKhw785FJcHQa+MZLOtrV8HGcZLF 42wYOth1CIv0QBxPU4FHMeo2PMIvk7wWYE5qwLG80BTPj9XgUk63cZK1lTsEs/B8E40M WbyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Iz2EvZFIABjNbnkyC3UNjG2s6yNlDWo5TqN7+5GSNOs=; b=KLs3t4GbDiA6+OxFe9z4HwFF/2QgnR89+w9Jf5Aup4p77DpOQOPDJuUhua624zXsI4 BrFVJck2XZF0Ahsq2pPq5WS/ephkEMre7fVHdlbMl8RLVJvzlK8twB807HdOry8q6HF/ Dtm/+9D3TEe8TKEDdrWcUFX4uvWk7EI1jDHJnfrfeS80T53z2uwgmp70WIOoYOljR2AP fZhfSmytz1Z0L0f5JY8rwkU7a+Zdm3xZmgOZhXu03HW+ovgwWmW69GCy2UglvfNDXtuK Yp/cZvnvcw+nQq16mgwbFdax8YrN9lVXYsvvukdiQvDouCzES3yn46q7rI8EEiphMeb7 UJMw== X-Gm-Message-State: APjAAAWNheJD2zh8DTmWqby0cRwYIm6oaEFjWXz/+7j6jkTlD2lsb47J HH7uAg6+przlDorrxATmmudJzr03a3kDsQ== X-Google-Smtp-Source: APXvYqyB0YpJ2C8PZ8V0sNKEt5ZT9nlp4MoAIN3spUVYvevF8tvFHEUv5Zq4cGo2w4nlud6nD2NgAg== X-Received: by 2002:a05:6830:1050:: with SMTP id b16mr1746988otp.228.1559680491501; Tue, 04 Jun 2019 13:34:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:49 -0500 Message-Id: <20190604203351.27778-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v4 37/39] tcg/aarch64: Use LDP to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This changes the code generation for the tlb from e.g. ldur x0, [x19, #0xffffffffffffffe0] ldur x1, [x19, #0xffffffffffffffe8] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] to ldp x0, x1, [x19, #-0x20] and x0, x0, x20, lsr #8 add x1, x1, x0 ldr x0, [x1] ldr x1, [x1, #0x18] Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes. --- tcg/aarch64/tcg-target.inc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 57c297f9d7..b0f8106642 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1641,6 +1641,10 @@ static void add_qemu_ldst_label(TCGContext *s, bool = is_ld, TCGMemOpIdx oi, QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); =20 +/* These offsets are built into the LDP below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + /* Load and compare a TLB entry, emitting the conditional jump to the slow path for the failure case, which will be patched later when finali= zing the slow path. Generated code returns the host addend in X1, @@ -1649,23 +1653,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits =3D get_alignment_bits(opc); unsigned s_bits =3D opc & MO_SIZE; unsigned a_mask =3D (1u << a_bits) - 1; unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0, x3; + TCGReg x3; TCGType mask_type; uint64_t compare_mask; =20 mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); =20 /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559682525; cv=none; d=zoho.com; s=zohoarc; b=RKmaHMgweCm928pjVWWJRf7n323nLczDw6TZ4SnzezubHOa4XnEf6mOsFFH2bDx5l77Ak6n9GYJCuhsSm1NI0fs/Ykzgnk4DkP9PquqNdJnwJJkISXoASZAj9VnW3iNd0ZpKws/A/73BOkmLFhmLnFiIQ8H+sWAOSeRgCaCvuP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559682525; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=553hxqrDAaVUQC3lJivdSjvTJknfLBkowACUKjkFIKU=; b=mQmeZgbuEzpL7Xtle1Uk7X1SgxeBEVa1iGq0bQNcazjiqS7gbnNSgq48b9aMJXqUFOmKDHOJYZpalfOdSE6rGOnUhu/8X4Uy/Vil7NZGlHAU65NjN1WATpisxSVXf45rZa/pPG2z6/KX1Nsq8HgwDb51uszwgKQpfucQf1bdguY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559682525076761.7466373404174; Tue, 4 Jun 2019 14:08:45 -0700 (PDT) Received: from localhost ([127.0.0.1]:58152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGfe-0003r5-1q for importer@patchew.org; Tue, 04 Jun 2019 17:08:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG95-0001iH-9c for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:35:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG93-00051E-Q2 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:59 -0400 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:39555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG93-0004tW-Hg for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:57 -0400 Received: by mail-ot1-x343.google.com with SMTP id r21so8385618otq.6 for ; Tue, 04 Jun 2019 13:34:53 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=553hxqrDAaVUQC3lJivdSjvTJknfLBkowACUKjkFIKU=; b=wjeWu0IJC5u7+vcq3j0z0KP4aryrXTRGdY8nNyfuZqKfy2D/7kVgHZbuU7gcivqK2n czElBpzY8iwiVD5LZfsHBtcClPqme90IJEKbhj/fsSVlhJeAuCEaWFT8eE9uXcg8Pmz0 2W9WeCu+843JxGIxDraFqUsVacLwouaMZyO9RCTvVWVo3mlwPgYxjPYATDL1GGU524Lo znDkc2PJvErHpapnI0WyKdr1PHJa1agkCnxEbUf5WXHYyUc+U6QIJJI1qkoOiesOxjto 4iF5rNgAnq3rC/kv+5AaP7o0fEr2krTznwe5sgPJ9ik2xO7RARgEjc0qG0KiwraThFTX uWtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=553hxqrDAaVUQC3lJivdSjvTJknfLBkowACUKjkFIKU=; b=Nk/yFdujEN+sNiZNQSg/7krgtQBT9V3uFSavOn81A09gCk8xLswUa0Qp1B5Aq0wwZp kg/nJyoGM3xtQ5KVVz3+0KoiNLa6v4ScWkZptiyQtPNGqPrDO/t5cb/4t7YP/A+0181V DfcngexQQkWPD6X7Cnl75bOQKAMU7sy8uarvVa169nRqBvaZyOYMJM37Nqu/vYfum5aP B2gBdvBYycaLjXtbx//1yv9RP0nAkZbFHyk0BZcB2qDgqYglD7R0Mn7yYC1LFVZPHGiN SzvwFfd6lVbR3TdeQRRW7OsbIY68tY4zaiVnd4FghYebWH0ckylptx6lAQ4qFeEWDOSf oNHg== X-Gm-Message-State: APjAAAVrF05sCYiBVRlizxpWsAh0KhR5nDYs6kdTa/YL8UgSCdWif1Ee PEi12wo4nvYahnF0r6Qxj3dStETMT3eYxw== X-Google-Smtp-Source: APXvYqwqjgMy1EP0ZmcfaHcdA0RoRcSCmpIsvWsESoVRE7c/fa+vRKiXcefdEm4Y7C0sHJHSTzptlA== X-Received: by 2002:a9d:27a4:: with SMTP id c33mr6481649otb.113.1559680492813; Tue, 04 Jun 2019 13:34:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:50 -0500 Message-Id: <20190604203351.27778-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v4 38/39] tcg/arm: Use LDRD to load tlb mask+table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This changes the code generation for the tlb from e.g. ldr ip, [r6, #-0x10] ldr r2, [r6, #-0xc] and ip, ip, r4, lsr #8 ldrd r0, r1, [r2, ip]! ldr r2, [r2, #0x18] to ldrd r0, r1, [r6, #-0x10] and r0, r0, r4, lsr #8 ldrd r2, r3, [r1, r0]! ldr r1, [r1, #0x18] for armv7 hosts. Rearranging the register allocation in order to avoid overlap between the two ldrd pairs causes the patch to be larger than it ordinarily would be. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes. --- tcg/arm/tcg-target.inc.c | 92 +++++++++++++++++++++++----------------- 1 file changed, 53 insertions(+), 39 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index b066e30f0e..276e843627 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -267,6 +267,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); #endif break; @@ -1224,6 +1225,10 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGRe= g argreg, QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); =20 +/* These offsets are built into the LDRD below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); + /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ =20 @@ -1238,47 +1243,54 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off); - - /* Extract the tlb index from the address into TMP. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrl= o, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R2. - * Load the tlb comparator into R0/R1 and the fast path addend into R2. + * We don't support inline unaligned acceses, but we can easily + * support overalignment checks. */ - if (cmp_off =3D=3D 0) { - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_T= MP); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0); - if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off); - } - } - if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4); - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, - offsetof(CPUTLBEntry, addend)); - - /* Check alignment. We don't support inline unaligned acceses, - but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits =3D s_bits; } =20 + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + if (use_armv6_instructions) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + } else { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); + } + + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + if (!use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); + } + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* Check alignment, check comparators. */ if (use_armv7_instructions) { tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); int rot =3D encode_imm(mask); @@ -1291,22 +1303,24 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, TCG_REG_TMP, 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); } else { if (a_bits) { tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R0, TCG_REG_TMP, + 0, TCG_REG_R2, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } =20 if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); } =20 - return TCG_REG_R2; + return TCG_REG_R1; } =20 /* Record the context of a call to the out of line helper code for the slow --=20 2.17.1 From nobody Mon May 20 01:26:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559682347; cv=none; d=zoho.com; s=zohoarc; b=MDXXlYz/xOLKru81E942/kdLe12AzdDCCOLwsqwdZI6X15MyqK3TTvF/t+I7flXkjm3e2f89dwvENY/O8/EFXN6ybcSdJz4CMLkH2RkJTyjk4Q8g4qq+AAVDXtCmtGyt+l85xfiMRAHS7uM562fIX0PN0OSLAhJZCtNBU17njs0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559682347; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8wDpuqt2tvKadOymhMpkkiKWS+EHs0ZcemyyrplJ7bs=; b=KPmOXoRBF1SzQPeE25rGvXLC8SjybKWbBmmsYukWKh0cdn5aqG542uIhXBH5E8XmkSJq25cfj6DCiZ/R9WObuCGqekeDizka2c68s76iJk3b43/gtlYzkLHHKYipjTFaGqLwrTa3nS9rN3PFeS3Z7AKJA5/XeFnq7cZGYB1xSW8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559682347713523.4808156935884; Tue, 4 Jun 2019 14:05:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:58102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYGcg-0001aO-Nt for importer@patchew.org; Tue, 04 Jun 2019 17:05:34 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYG95-0001j2-SS for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:35:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYG94-00051U-5b for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:59 -0400 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:37825) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYG93-0004wI-W2 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 16:34:58 -0400 Received: by mail-oi1-x244.google.com with SMTP id t76so1581677oih.4 for ; Tue, 04 Jun 2019 13:34:54 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id h1sm5979901otj.78.2019.06.04.13.34.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 13:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=8wDpuqt2tvKadOymhMpkkiKWS+EHs0ZcemyyrplJ7bs=; b=b4G3l++DM5lY5nFvXhNgyNVJdSJiP2fPobYejXCrWikvLRamBtiHVfz6uOm74JSxhv R7IaeprCyybU+WzZ1cExVhgKfoTmYqlUU9EjDtd8IEbnhSRtGnswnhtcE/qehpbKeD0R eqTn7Qj8oAg2zw9xK9+bcCmJOtHhrINCnQ+nkayj+d/r+LBs4GyosIrmFdKK+eVmi6YJ MGlx/HeNaMIfmJBmi9SNNGR7c0vrMeEmLeLgIH5Vuvddm2RfrmzH3Gmg1pAhnOyT7yY1 PlnYymO9H6Wtcb9igKbU1a7PiIWbt/7MCnIbkI3IJxqFWOXHIDJ7vDCqN911InkEJXaq qK5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=8wDpuqt2tvKadOymhMpkkiKWS+EHs0ZcemyyrplJ7bs=; b=sNO2vfsgHVqyQjZ0hMQQSJa6OPecS/J9MQjbUidunuuy2LrKfxk53HRy9mE+YzmSLm itYHZClmoh63n12dsYTwXAdCRg7f0g2mrHj4gGl1ThgZx9N2n6dZCTg9FnsiRTShGthn s05P3EawJEco73y2E5RZpCERvAo2Gm/YVtmys23Iz0FSzrNaBBJSXHSpf582z1ll6F9z iNVPcaFyzFmLjbXQ7pG1yG6sUE54uaIatFIp8uYHpG7C5wPGRNwYUiGQBT1LRncvavCM nkPkTb80nuUhsBqlojgVHIM5C+KwTUt3YY+sDMH32tFHx2WK0YuM8Y0NRNC1Th2sVwK5 PMFw== X-Gm-Message-State: APjAAAW4kJ50DIeviy0bcbPq1qJRWGgEXzt2Fs64ePdfDl/a4su9oLZW aQ8VCc7VsxMqxgHyvcMFF8ryAm15b1nIjw== X-Google-Smtp-Source: APXvYqx0obfITlNBpwOqhgqWqUkaiiaI0Dm4MVBeqeu/pvXuDFg8Dr2AmPThwZf8y9ulAqkepg0rbg== X-Received: by 2002:aca:5d45:: with SMTP id r66mr1036453oib.143.1559680493992; Tue, 04 Jun 2019 13:34:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 15:33:51 -0500 Message-Id: <20190604203351.27778-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604203351.27778-1-richard.henderson@linaro.org> References: <20190604203351.27778-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH v4 39/39] tcg/arm: Remove mostly unreachable tlb special case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There was nothing armv7 specific about the bic+cmp sequence, however looking at the set of guests more closely shows that the 8-bit immediate operand for the bic can only be satisfied with one guest in tree: baseline m-profile -- 10-bit pages with aligned 4-byte memory ops. Therefore it does not seem useful to keep this path. Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 276e843627..ece88dc2eb 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1290,19 +1290,20 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, offsetof(CPUTLBEntry, addend)); =20 - /* Check alignment, check comparators. */ - if (use_armv7_instructions) { + /* + * Check alignment, check comparators. + * Do this in no more than 3 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we need + * to clear at least 9 bits even for an 8-byte memory, which means it + * isn't worth checking for an immediate operand for BIC. + */ + if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); - int rot =3D encode_imm(mask); =20 - if (rot >=3D 0) {=20 - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, - rotl(mask, rot) | (rot << 7)); - } else { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); - } + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + addrlo, TCG_REG_TMP, 0); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); } else { if (a_bits) { --=20 2.17.1