From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155966610879424.767575180682798; Tue, 4 Jun 2019 09:35:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:55172 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCOp-0007lh-5U for importer@patchew.org; Tue, 04 Jun 2019 12:34:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCFx-0000Zz-Gz for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYCFv-0003Zm-3b for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:49 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40476) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYCFq-0003RV-9U; Tue, 04 Jun 2019 12:25:42 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 02C8896F56; Tue, 4 Jun 2019 16:25:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=15SURQuq7gIBgpjRlvviKrmBck+uSlAG1Ct83XX3t6U=; b=DJSd9HDaQZdleZxohktQ3aJiu+JSMnPlvqWZrH76JhuGKCtx7pkhbbg1c/1rFDk20vJslv +7dCe1jU6nylZDkGEYqcexgU6eoqOBYpLK8baub0bLAi1ChHmT1V7/hshFeA79EeuovkMz uZ42hhig10/vAxzcaMinGNOT7RgDHcw= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:15 +0200 Message-Id: <20190604162526.10655-2-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=15SURQuq7gIBgpjRlvviKrmBck+uSlAG1Ct83XX3t6U=; b=jBd8pNsZ+Q0+P5zh6otcqJQiDD1SqHBcDpF/8Lrv3I5kAAnaahSZX8mAfyHlJsZaAkDj8x Uxt0GBNOCV/viAZrqgpE0caYMjegRQGLwXQC7bx0pLlpCMhc7ipw0QCh3H9fvw3eNZ2JOj UautRcjzfwqxo0ytDEExLOGfLCFfNDc= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1559665540; a=rsa-sha256; cv=none; b=R+emzzn2Pr7a3SREGj2J/27bc3wVBeuJ1JKQqkH3O+ussmbliFMu9cPz4n0uv/a5O9YXTE nzKzkvOzxmnGYm89WTLrWQltKl0arCQ7ESgatZNBZQPhr1lwEVXEe8xDFQ+bsT6sQis5NN hSwGvEmvYdPdL20ZBDdsXaUhz5PFUcI= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [RFC PATCH v2 01/12] Create Resettable QOM interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, marc.burton@greensocs.com, alistair@alistair23.me, qemu-arm@nongnu.org, Damien Hedde , marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This commit defines an interface allowing multi-phase reset. The phases are INIT, HOLD and EXIT. Each phase has an associated method in the class. The reset of a Resettable is controlled with 2 functions: - resettable_assert_reset which starts the reset operation. - resettable_deassert_reset which ends the reset operation. There is also a `resettable_reset` helper function which does assert then deassert allowing to do a proper reset in one call. The Resettable interface is "reentrant", _assert_ can be called several times and _deasert_ must be called the same number of times so that the Resettable leave reset state. It is supported by keeping a counter of the current number of _assert_ calls. The counter maintainance is done though 3 methods get/increment/decrement_count. Reset hierarchy is also supported. Each Resettable may have sub-Resettable objects. When resetting a Resettable, it is propagated to its children using the foreach_child method. The reset is first propagated to the children before being applied to the Resettable. This will allow to replace current qdev_reset mechanism by this interface without side-effects on reset order. Note: I used an uint32 for the count. This match the type already used in the existing resetting counter in hw/scsi/vmw_pvscsi.c for the PVSCSIState. Signed-off-by: Damien Hedde --- hw/core/Makefile.objs | 1 + hw/core/resettable.c | 121 ++++++++++++++++++++++++++++++++++++++++ include/hw/resettable.h | 104 ++++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 hw/core/resettable.c create mode 100644 include/hw/resettable.h diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index a799c83815..97007454a8 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -1,6 +1,7 @@ # core qdev-related obj files, also used by *-user: common-obj-y +=3D qdev.o qdev-properties.o common-obj-y +=3D bus.o reset.o +common-obj-y +=3D resettable.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o common-obj-$(CONFIG_SOFTMMU) +=3D fw-path-provider.o # irq.o needed for qdev GPIO handling: diff --git a/hw/core/resettable.c b/hw/core/resettable.c new file mode 100644 index 0000000000..59954dac05 --- /dev/null +++ b/hw/core/resettable.c @@ -0,0 +1,121 @@ +/* + * Resettable interface. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "hw/resettable.h" + +#define RESETTABLE_MAX_COUNT 50 + +#define RESETTABLE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE) + +static void resettable_init_phase(Object *obj, bool cold); + +static void resettable_cold_init_phase(Object *obj) +{ + resettable_init_phase(obj, true); +} + +static void resettable_warm_init_phase(Object *obj) +{ + resettable_init_phase(obj, false); +} + +static void resettable_init_phase(Object *obj, bool cold) +{ + void (*func)(Object *); + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + uint32_t count; + + count =3D rc->increment_count(obj); + /* this assert is triggered by an eventual reset loop */ + assert(count <=3D RESETTABLE_MAX_COUNT); + + func =3D cold ? resettable_cold_init_phase : resettable_warm_init_phas= e; + rc->foreach_child(obj, func); + + if (rc->phases.init) { + rc->phases.init(obj, cold); + } +} + +static void resettable_hold_phase(Object *obj) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + + rc->foreach_child(obj, resettable_hold_phase); + + if (rc->phases.hold) { + rc->phases.hold(obj); + } +} + +static void resettable_exit_phase(Object *obj) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + + rc->foreach_child(obj, resettable_exit_phase); + + assert(rc->get_count(obj) > 0); + if (rc->decrement_count(obj) =3D=3D 0 && rc->phases.exit) { + rc->phases.exit(obj); + } +} + +void resettable_assert_reset(Object *obj, bool cold) +{ + resettable_init_phase(obj, cold); + resettable_hold_phase(obj); +} + +void resettable_deassert_reset(Object *obj) +{ + resettable_exit_phase(obj); +} + +void resettable_reset(Object *obj, bool cold) +{ + resettable_assert_reset(obj, cold); + resettable_deassert_reset(obj); +} + +void resettable_class_set_parent_reset_phases(ResettableClass *rc, + ResettableInitPhase init, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_pha= ses) +{ + *parent_phases =3D rc->phases; + if (init) { + rc->phases.init =3D init; + } + if (hold) { + rc->phases.hold =3D hold; + } + if (exit) { + rc->phases.exit =3D exit; + } +} + +static const TypeInfo resettable_interface_info =3D { + .name =3D TYPE_RESETTABLE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(ResettableClass), +}; + +static void reset_register_types(void) +{ + type_register_static(&resettable_interface_info); +} + +type_init(reset_register_types) diff --git a/include/hw/resettable.h b/include/hw/resettable.h new file mode 100644 index 0000000000..39522b9b51 --- /dev/null +++ b/include/hw/resettable.h @@ -0,0 +1,104 @@ +#ifndef HW_RESETTABLE_H +#define HW_RESETTABLE_H + +#include "qom/object.h" + +#define TYPE_RESETTABLE "resettable" + +#define RESETTABLE_CLASS(class) \ + OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE) + +/* + * ResettableClass: + * Interface for resettable objects. + * + * The reset operation is divided in several phases each represented by a + * method. + * + * Each Ressetable must maintain a reset counter in its state, 3 methods a= llows + * to interact with it. + * + * @phases.init: should reset local state only. Takes a bool @cold argument + * specifying whether the reset is cold or warm. It must not do side-effect + * on others objects. + * + * @phases.hold: side-effects action on others objects due to staying in a + * resetting state. + * + * @phases.exit: leave the reset state, may do side-effects action on othe= rs + * objects. + * + * @get_count: Get the current reset count + * @increment_count: Increment the reset count, returns the new count + * @decrement_count: decrement the reset count, returns the new count + * + * @foreach_child: Executes a given function on every Resettable child. + * A child is not a QOM child, but a child a reset meaning. + */ +typedef void (*ResettableInitPhase)(Object *obj, bool cold); +typedef void (*ResettableHoldPhase)(Object *obj); +typedef void (*ResettableExitPhase)(Object *obj); +typedef uint32_t (*ResettableGetCount)(Object *obj); +typedef uint32_t (*ResettableIncrementCount)(Object *obj); +typedef uint32_t (*ResettableDecrementCount)(Object *obj); +typedef void (*ResettableForeachChild)(Object *obj, void (*visitor)(Object= *)); +typedef struct ResettableClass { + InterfaceClass parent_class; + + struct ResettablePhases { + ResettableInitPhase init; + ResettableHoldPhase hold; + ResettableExitPhase exit; + } phases; + + ResettableGetCount get_count; + ResettableIncrementCount increment_count; + ResettableDecrementCount decrement_count; + ResettableForeachChild foreach_child; +} ResettableClass; +typedef struct ResettablePhases ResettablePhases; + +/** + * resettable_assert_reset: + * Increments the reset count and executes the init and hold phases. + * Each time resettable_assert_reset is called, resettable_deassert_reset + * must eventually be called once. + * It will also impact reset children. + * + * @obj object to reset, must implement Resettable interface. + * @cold boolean indicating the type of reset (cold or warm) + */ +void resettable_assert_reset(Object *obj, bool cold); + +/** + * resettable_deassert_reset: + * Decrements the reset count by one and executes the exit phase if it hits + * zero. + * It will also impact reset children. + * + * @obj object to reset, must implement Resettable interface. + */ +void resettable_deassert_reset(Object *obj); + +/** + * resettable_reset: + * Calling this function is equivalent to call @assert_reset then + * @deassert_reset. + */ +void resettable_reset(Object *obj, bool cold); + +/** + * resettable_class_set_parent_reset_phases: + * + * Save @rc current reset phases into @parent_phases and override @rc phas= es + * by the given new methods (@init, @hold and @exit). + * Each phase is overriden only if the new one is not NULL allowing to + * override a subset of phases. + */ +void resettable_class_set_parent_reset_phases(ResettableClass *rc, + ResettableInitPhase init, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_pha= ses); + +#endif --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Tue, 04 Jun 2019 12:25:42 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id C358896F59; Tue, 4 Jun 2019 16:25:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ids2q0cvMSkPKHjRd29FbMXZAla1JGKMnzTb1AHd7kk=; b=wDvIKIbtw7KbHs24sz2MFMX/4p3m2tz1fdFstnYxsUllAhCp3Za3QJywjFUgf9YLKqQczh d3lsL5jY/W4P50DnkVhtbjyaGsdCqMqcuNzB1cTf61XXDwf5611p/yQYs8jjeXWOaUdqnF HPFnyZEzZ+zOsztlTfnvnE4FpFbfpvE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:16 +0200 Message-Id: <20190604162526.10655-3-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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charset="utf-8" This function has device_reset behavior and will allow to change device_reset prototype while keeping the functionality. Signed-off-by: Damien Hedde --- hw/core/qdev.c | 2 +- include/hw/qdev-core.h | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index f9b6efe509..90037ba70c 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -1086,7 +1086,7 @@ void device_class_set_parent_unrealize(DeviceClass *d= c, dc->unrealize =3D dev_unrealize; } =20 -void device_reset(DeviceState *dev) +void device_legacy_reset(DeviceState *dev) { DeviceClass *klass =3D DEVICE_GET_CLASS(dev); =20 diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index fa55dc10ae..537dd0054d 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -406,11 +406,16 @@ char *qdev_get_own_fw_dev_path_from_handler(BusState = *bus, DeviceState *dev); void qdev_machine_init(void); =20 /** - * @device_reset + * device_legacy_reset: * * Reset a single device (by calling the reset method). */ -void device_reset(DeviceState *dev); +void device_legacy_reset(DeviceState *dev); + +static inline void device_reset(DeviceState *dev) +{ + device_legacy_reset(dev); +} =20 void device_class_set_parent_reset(DeviceClass *dc, DeviceReset dev_reset, --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559665932614285.93549897063485; Tue, 4 Jun 2019 09:32:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:55144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCM2-0005ll-I2 for importer@patchew.org; Tue, 04 Jun 2019 12:32:06 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCFx-0000Zq-Df for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYCFv-0003a4-7o for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:49 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40524) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYCFr-0003TS-59; Tue, 04 Jun 2019 12:25:43 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 9831296F5B; Tue, 4 Jun 2019 16:25:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665542; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YYxCAcFY2f8T7dY7vwkEpubeXgbDt8PO/wb4DbcDzk8=; b=EHffHrquEFGV8MLehGdJ56kI3+VIXA79OJVSDruYKa/2PKN+LbOKDqavaWQ5TW44/8EWze TF7C81ZmWXWJuBmX+Q5TQsYH+2K+EJ6T8e+bK/01tHvaLTL0vXeVXKRsyCRhfpljtqjRCy ILKkerL1QqWNIEefJ/hWT3YwlFzwevw= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:17 +0200 Message-Id: <20190604162526.10655-4-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Damien Hedde --- hw/audio/intel-hda.c | 2 +- hw/hyperv/hyperv.c | 2 +- hw/i386/pc.c | 2 +- hw/ide/microdrive.c | 8 ++++---- hw/intc/spapr_xive.c | 2 +- hw/ppc/pnv_psi.c | 2 +- hw/ppc/spapr_pci.c | 2 +- hw/ppc/spapr_vio.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- hw/scsi/vmw_pvscsi.c | 2 +- hw/sd/omap_mmc.c | 2 +- hw/sd/pl181.c | 2 +- 12 files changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index 33e333cc26..c674b9c0bb 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -1085,7 +1085,7 @@ static void intel_hda_reset(DeviceState *dev) QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { DeviceState *qdev =3D kid->child; cdev =3D HDA_CODEC_DEVICE(qdev); - device_reset(DEVICE(cdev)); + device_legacy_reset(DEVICE(cdev)); d->state_sts |=3D (1 << cdev->cad); } intel_hda_update_irq(d); diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index 8758635227..ec57417a3d 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -139,7 +139,7 @@ void hyperv_synic_reset(CPUState *cs) SynICState *synic =3D get_synic(cs); =20 if (synic) { - device_reset(DEVICE(synic)); + device_legacy_reset(DEVICE(synic)); } } =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index edc240bcbf..c6d72c9a5d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2634,7 +2634,7 @@ static void pc_machine_reset(void) cpu =3D X86_CPU(cs); =20 if (cpu->apic_state) { - device_reset(cpu->apic_state); + device_legacy_reset(cpu->apic_state); } } } diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c index 34bb98dce8..b1350eb54f 100644 --- a/hw/ide/microdrive.c +++ b/hw/ide/microdrive.c @@ -171,7 +171,7 @@ static void md_attr_write(PCMCIACardState *card, uint32= _t at, uint8_t value) case 0x00: /* Configuration Option Register */ s->opt =3D value & 0xcf; if (value & OPT_SRESET) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -314,7 +314,7 @@ static void md_common_write(PCMCIACardState *card, uint= 32_t at, uint16_t value) case 0xe: /* Device Control */ s->ctrl =3D value; if (value & CTRL_SRST) { - device_reset(DEVICE(s)); + device_legacy_reset(DEVICE(s)); } md_interrupt_update(s); break; @@ -539,7 +539,7 @@ static int dscm1xxxx_attach(PCMCIACardState *card) md->attr_base =3D pcc->cis[0x74] | (pcc->cis[0x76] << 8); md->io_base =3D 0x0; =20 - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); md_interrupt_update(md); =20 return 0; @@ -549,7 +549,7 @@ static int dscm1xxxx_detach(PCMCIACardState *card) { MicroDriveState *md =3D MICRODRIVE(card); =20 - device_reset(DEVICE(md)); + device_legacy_reset(DEVICE(md)); return 0; } =20 diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 62e0ef8fa5..bea4582f33 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -1528,7 +1528,7 @@ static target_ulong h_int_reset(PowerPCCPU *cpu, return H_PARAMETER; } =20 - device_reset(DEVICE(xive)); + device_legacy_reset(DEVICE(xive)); =20 if (kvm_irqchip_in_kernel()) { Error *local_err =3D NULL; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 5345c8389e..d79c8c62be 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -702,7 +702,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr = addr, break; case PSIHB9_INTERRUPT_CONTROL: if (val & PSIHB9_IRQ_RESET) { - device_reset(DEVICE(&psi9->source)); + device_legacy_reset(DEVICE(&psi9->source)); } psi->regs[reg] =3D val; break; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 97961b0128..d89290ac28 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1858,7 +1858,7 @@ static int spapr_phb_children_reset(Object *child, vo= id *opaque) DeviceState *dev =3D (DeviceState *) object_dynamic_cast(child, TYPE_D= EVICE); =20 if (dev) { - device_reset(dev); + device_legacy_reset(dev); } =20 return 0; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 583c13deda..5a0b5cc35c 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -306,7 +306,7 @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *cr= q) static void spapr_vio_quiesce_one(SpaprVioDevice *dev) { if (dev->tcet) { - device_reset(DEVICE(dev->tcet)); + device_legacy_reset(DEVICE(dev->tcet)); } free_crq(dev); } diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index be2896232d..d532597566 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -243,7 +243,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_= t ra) stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); goto out; } - device_reset(DEVICE(pbdev)); + device_legacy_reset(DEVICE(pbdev)); pbdev->fh &=3D ~FH_MASK_ENABLE; pbdev->state =3D ZPCI_FS_DISABLED; stl_p(&ressetpci->fh, pbdev->fh); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 584b4be07e..7ad3d05b9b 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -834,7 +834,7 @@ pvscsi_on_cmd_reset_device(PVSCSIState *s) =20 if (sdev !=3D NULL) { s->resetting++; - device_reset(&sdev->qdev); + device_legacy_reset(&sdev->qdev); s->resetting--; return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; } diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index d0c98ca021..24a1edc149 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -317,7 +317,7 @@ void omap_mmc_reset(struct omap_mmc_s *host) * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. */ - device_reset(DEVICE(host->card)); + device_legacy_reset(DEVICE(host->card)); } =20 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index 3ad7e925c5..03f859ec33 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -479,7 +479,7 @@ static void pl181_reset(DeviceState *d) /* Since we're still using the legacy SD API the card is not plugged * into any bus, and we must reset it manually. */ - device_reset(DEVICE(s->card)); + device_legacy_reset(DEVICE(s->card)); } =20 static void pl181_init(Object *obj) --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155966624766666.20032720549898; Tue, 4 Jun 2019 09:37:27 -0700 (PDT) Received: from localhost ([127.0.0.1]:55227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCR7-0001IN-KX for importer@patchew.org; Tue, 04 Jun 2019 12:37:21 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39344) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCFz-0000c9-D9 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYCFx-0003dl-4u for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:51 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40534) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYCFr-0003UO-Rz; Tue, 04 Jun 2019 12:25:44 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 5E54F96F58; Tue, 4 Jun 2019 16:25:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9FKgRGbSAx2vsIcSB6v4+/dH/c3qOu+6weH6IoadarA=; b=o9gGV7tHdf9G97XJEQXQfV+rBt4GOaWA2gCjQphv+xSVJtVgiQK7MDUNxehzcq6bt93o50 1ONsmhiFbTMMDoBDVNKJPNIe1EMGdH6WaSIe7hkLIvHkawChopUyV6/vZtYkzBiDDSVRP7 vVcUzZoE90mUfVHdJE9neV8R3zBUtoY= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:18 +0200 Message-Id: <20190604162526.10655-5-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9FKgRGbSAx2vsIcSB6v4+/dH/c3qOu+6weH6IoadarA=; b=fPRa3FcahC35XR7I4Mpf9D5RXe6fXqDjORzJYQaDhVbMfslAt/TFYpaBx7coIeRFNBF6lK efOj6KM1ZFp1hFbLd7cwBGHRAYNSuYmdtlu11Wfk4ABjDcay9zyhOL2Hz7kdwE2VpemPgU OeANmN3sfLmSPp8fHJepZjdkx56PnZs= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1559665543; a=rsa-sha256; cv=none; b=pnX1f5uo8vEI2LD5uDsujiHlFFWPV+MlxEkaLBlDWEqGr05gF6Gpdn58u9eNO0rC8Xn2FR g1WyIjankYev4qFMWPtuB2lspsaaD61l/ZnnnXy/555urfir79zvtwsLCihjYAKi8ACW0T 0beYOA8b0sUCVgoz9x4r8Ey0WEZj5Fo= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [RFC PATCH v2 04/12] make Device and Bus Resettable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, marc.burton@greensocs.com, alistair@alistair23.me, qemu-arm@nongnu.org, Damien Hedde , marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This add Resettable interface implementation for both Bus and Device. The init phase default implementation is to call the legacy reset handler. qdev/bus_reset_all implementations are modified to use the new device_reset / bus_reset function. Signed-off-by: Damien Hedde --- hw/core/bus.c | 60 ++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 65 +++++++++++++++++++++++++++++++++++------- include/hw/qdev-core.h | 63 ++++++++++++++++++++++++++++++++++------ tests/Makefile.include | 1 + 4 files changed, 170 insertions(+), 19 deletions(-) diff --git a/hw/core/bus.c b/hw/core/bus.c index e09843f6ab..c731e5cac7 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -21,6 +21,7 @@ #include "qemu-common.h" #include "hw/qdev.h" #include "qapi/error.h" +#include "hw/resettable.h" =20 void qbus_set_hotplug_handler(BusState *bus, Object *handler, Error **errp) { @@ -67,6 +68,54 @@ int qbus_walk_children(BusState *bus, return 0; } =20 +void bus_reset(BusState *bus, bool cold) +{ + resettable_reset(OBJECT(bus), cold); +} + +bool bus_is_resetting(BusState *bus) +{ + return (bus->resetting !=3D 0); +} + +static uint32_t bus_get_reset_count(Object *obj) +{ + BusState *bus =3D BUS(obj); + return bus->resetting; +} + +static uint32_t bus_increment_reset_count(Object *obj) +{ + BusState *bus =3D BUS(obj); + return ++bus->resetting; +} + +static uint32_t bus_decrement_reset_count(Object *obj) +{ + BusState *bus =3D BUS(obj); + return --bus->resetting; +} + +static void bus_foreach_reset_child(Object *obj, void (*func)(Object *)) +{ + BusState *bus =3D BUS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + func(OBJECT(kid->child)); + } +} + +static void bus_reset_init_phase(Object *obj, bool cold) +{ + BusState *bus =3D BUS(obj); + BusClass *bc =3D BUS_GET_CLASS(obj); + + if (bc->reset) { + bc->reset(bus); + } +} + static void qbus_realize(BusState *bus, DeviceState *parent, const char *n= ame) { const char *typename =3D object_get_typename(OBJECT(bus)); @@ -204,9 +253,16 @@ static char *default_bus_get_fw_dev_path(DeviceState *= dev) static void bus_class_init(ObjectClass *class, void *data) { BusClass *bc =3D BUS_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); =20 class->unparent =3D bus_unparent; bc->get_fw_dev_path =3D default_bus_get_fw_dev_path; + + rc->phases.init =3D bus_reset_init_phase; + rc->get_count =3D bus_get_reset_count; + rc->increment_count =3D bus_increment_reset_count; + rc->decrement_count =3D bus_decrement_reset_count; + rc->foreach_child =3D bus_foreach_reset_child; } =20 static void qbus_finalize(Object *obj) @@ -225,6 +281,10 @@ static const TypeInfo bus_info =3D { .instance_init =3D qbus_initfn, .instance_finalize =3D qbus_finalize, .class_init =3D bus_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_RESETTABLE }, + { } + }, }; =20 static void bus_register_types(void) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 90037ba70c..8c3911c2bd 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -254,25 +254,56 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState = *dev) return hotplug_ctrl; } =20 -static int qdev_reset_one(DeviceState *dev, void *opaque) +void device_reset(DeviceState *dev, bool cold) { - device_reset(dev); + resettable_reset(OBJECT(dev), cold); +} =20 - return 0; +bool device_is_resetting(DeviceState *dev) +{ + return (dev->resetting !=3D 0); +} + +static uint32_t device_get_reset_count(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + return dev->resetting; } =20 -static int qbus_reset_one(BusState *bus, void *opaque) +static uint32_t device_increment_reset_count(Object *obj) { - BusClass *bc =3D BUS_GET_CLASS(bus); - if (bc->reset) { - bc->reset(bus); + DeviceState *dev =3D DEVICE(obj); + return ++dev->resetting; +} + +static uint32_t device_decrement_reset_count(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + return --dev->resetting; +} + +static void device_foreach_reset_child(Object *obj, void (*func)(Object *)) +{ + DeviceState *dev =3D DEVICE(obj); + BusState *bus; + QLIST_FOREACH(bus, &dev->child_bus, sibling) { + func(OBJECT(bus)); + } +} + +static void device_reset_init_phase(Object *obj, bool cold) +{ + DeviceState *dev =3D DEVICE(obj); + DeviceClass *dc =3D DEVICE_GET_CLASS(dev); + + if (dc->reset) { + dc->reset(dev); } - return 0; } =20 void qdev_reset_all(DeviceState *dev) { - qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NU= LL); + device_reset(dev, false); } =20 void qdev_reset_all_fn(void *opaque) @@ -282,7 +313,7 @@ void qdev_reset_all_fn(void *opaque) =20 void qbus_reset_all(BusState *bus) { - qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NU= LL); + bus_reset(bus, false); } =20 void qbus_reset_all_fn(void *opaque) @@ -864,7 +895,7 @@ static void device_set_realized(Object *obj, bool value= , Error **errp) } } if (dev->hotplugged) { - device_reset(dev); + device_reset(dev, true); } dev->pending_deleted_event =3D false; =20 @@ -954,6 +985,7 @@ static void device_initfn(Object *obj) =20 dev->instance_id_alias =3D -1; dev->realized =3D false; + dev->resetting =3D 0; =20 object_property_add_bool(obj, "realized", device_get_realized, device_set_realized, NUL= L); @@ -1049,6 +1081,7 @@ static void device_unparent(Object *obj) static void device_class_init(ObjectClass *class, void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); =20 class->unparent =3D device_unparent; =20 @@ -1060,6 +1093,12 @@ static void device_class_init(ObjectClass *class, vo= id *data) */ dc->hotpluggable =3D true; dc->user_creatable =3D true; + + rc->phases.init =3D device_reset_init_phase; + rc->get_count =3D device_get_reset_count; + rc->increment_count =3D device_increment_reset_count; + rc->decrement_count =3D device_decrement_reset_count; + rc->foreach_child =3D device_foreach_reset_child; } =20 void device_class_set_parent_reset(DeviceClass *dc, @@ -1117,6 +1156,10 @@ static const TypeInfo device_type_info =3D { .class_init =3D device_class_init, .abstract =3D true, .class_size =3D sizeof(DeviceClass), + .interfaces =3D (InterfaceInfo[]) { + { TYPE_RESETTABLE }, + { } + }, }; =20 static void qdev_register_types(void) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 537dd0054d..658a419350 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -6,6 +6,7 @@ #include "qom/object.h" #include "hw/irq.h" #include "hw/hotplug.h" +#include "hw/resettable.h" =20 enum { DEV_NVECTORS_UNSPECIFIED =3D -1, @@ -107,6 +108,11 @@ typedef struct DeviceClass { bool hotpluggable; =20 /* callbacks */ + /* + * Reset method here is deprecated and replaced by methods in the + * resettable class interface to implement a multi-phase reset. + * TODO: remove once every reset callback is unused + */ DeviceReset reset; DeviceRealize realize; DeviceUnrealize unrealize; @@ -131,6 +137,8 @@ struct NamedGPIOList { /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. + * @resetting: Indicates whether the device is under reset. Also + * used to count how many times reset has been initiated on the device. * * This structure should not be accessed directly. We declare it here * so that it can be embedded in individual device state structures. @@ -152,6 +160,7 @@ struct DeviceState { int num_child_bus; int instance_id_alias; int alias_required_for_version; + uint32_t resetting; }; =20 struct DeviceListener { @@ -198,6 +207,8 @@ typedef struct BusChild { /** * BusState: * @hotplug_handler: link to a hotplug handler associated with bus. + * @resetting: Indicates whether the device is under reset. Also + * used to count how many times reset has been initiated on the device. */ struct BusState { Object obj; @@ -209,6 +220,7 @@ struct BusState { int num_children; QTAILQ_HEAD(, BusChild) children; QLIST_ENTRY(BusState) sibling; + uint32_t resetting; }; =20 /** @@ -375,11 +387,36 @@ int qdev_walk_children(DeviceState *dev, qdev_walkerfn *post_devfn, qbus_walkerfn *post_busf= n, void *opaque); =20 -void qdev_reset_all(DeviceState *dev); -void qdev_reset_all_fn(void *opaque); +/** + * device_reset: + * Resets the device @dev, @cold tell whether to do a cold or warm reset. + * Uses the ressetable interface. + * Base behavior is to reset the device and its qdev/qbus subtree. + */ +void device_reset(DeviceState *dev, bool cold); =20 /** - * @qbus_reset_all: + * bus_reset: + * Resets the bus @bus, @cold tell whether to do a cold or warm reset. + * Uses the ressetable interface. + * Base behavior is to reset the bus and its qdev/qbus subtree. + */ +void bus_reset(BusState *bus, bool cold); + +/** + * device_is_resetting: + * Tell whether the device @dev is currently under reset. + */ +bool device_is_resetting(DeviceState *dev); + +/** + * bus_is_resetting: + * Tell whether the bus @bus is currently under reset. + */ +bool bus_is_resetting(BusState *bus); + +/** + * qbus/qdev_reset_all: * @bus: Bus to be reset. * * Reset @bus and perform a bus-level ("hard") reset of all devices connec= ted @@ -387,7 +424,13 @@ void qdev_reset_all_fn(void *opaque); * hard reset means that qbus_reset_all will reset all state of the device. * For PCI devices, for example, this will include the base address regist= ers * or configuration space. + * + * Theses functions are deprecated, please use device/bus_reset or + * resettable_reset_* instead + * TODO: remove them when all occurence are removed */ +void qdev_reset_all(DeviceState *dev); +void qdev_reset_all_fn(void *opaque); void qbus_reset_all(BusState *bus); void qbus_reset_all_fn(void *opaque); =20 @@ -409,17 +452,21 @@ void qdev_machine_init(void); * device_legacy_reset: * * Reset a single device (by calling the reset method). + * + * This function is deprecated, please use device_reset() instead. + * TODO: remove the function when all occurences are removed. */ void device_legacy_reset(DeviceState *dev); =20 -static inline void device_reset(DeviceState *dev) -{ - device_legacy_reset(dev); -} - +/** + * device_class_set_parent_reset: + * TODO: remove the function when DeviceClass's reset method + * is not used anymore. + */ void device_class_set_parent_reset(DeviceClass *dc, DeviceReset dev_reset, DeviceReset *parent_reset); + void device_class_set_parent_realize(DeviceClass *dc, DeviceRealize dev_realize, DeviceRealize *parent_realize); diff --git a/tests/Makefile.include b/tests/Makefile.include index 46a36c2c95..5b25905907 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -547,6 +547,7 @@ tests/fp/%: =20 tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ + hw/core/resettable.o \ hw/core/bus.o \ hw/core/irq.o \ hw/core/fw-path-provider.o \ --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 04 Jun 2019 12:25:44 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 2347496F5E; Tue, 4 Jun 2019 16:25:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BV0HcRaSIU6Sfthp4FZeZ/8eIR2NE6/Pg/vTMJGpqZY=; b=CN8qRnadXOPvK5WPEJ90QixXUOL/2WmYapH/CXsyaMZN0SWMS5Smitz7phifTBbNtiCmbw KKkwXd7jcUsrflZzb6tG/OkIoR+TwHvWIGMVdPsWKa1meqP0QMwc1aXJuCWuVsEeb98xgy GwJWsqZoGAksJQS4DXr6q/YSN6yYAP0= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:19 +0200 Message-Id: <20190604162526.10655-6-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BV0HcRaSIU6Sfthp4FZeZ/8eIR2NE6/Pg/vTMJGpqZY=; b=To0LJPRV0yTupyaEtrgPvojdbEkCbpEkDxfMvmiGgENOcIGLkf7nBfXoVaarFJjHitiwoC WjdkMAbukxkf74p+EzRKOLIj2wPH9DBm1g2pg5G6Mpb66MsD8J0cYB5froBfBK4yMTap3Y /gT6buEPxmtO0vigNNpPOcBNEGJIotc= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1559665543; a=rsa-sha256; cv=none; b=jBjUSTf86wY0KAec2FMpSLAU3aZf3ArCa/zJ00cB6Jh4rcXT6LPTgQbR3bNq9BqpYZuJ8P NAEs4hJI6PH3lWddY/ODlBdGr00dLzkCbjNLEDw4lggnqbAV25wtf8JY+Aue0QsfM1FMpM x38n6IQlARdWzeZlJnYaAtdmGhQfy4Y= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [RFC PATCH v2 05/12] Add function to control reset with gpio inputs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, marc.burton@greensocs.com, alistair@alistair23.me, qemu-arm@nongnu.org, Damien Hedde , marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" It adds the possibility to add 2 gpios to control the warm and cold reset. With theses ios, the reset can be maintained during some time. Each io is associated with a state to detect level changes. The cold reset io function is named power_gate as it is really the meaning of this io. Signed-off-by: Damien Hedde --- hw/core/qdev.c | 57 ++++++++++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 44 ++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 8c3911c2bd..89405398ae 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -429,6 +429,61 @@ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_hand= ler handler, int n) qdev_init_gpio_in_named(dev, handler, NULL, n); } =20 +static void device_reset_handler(DeviceState *dev, bool cold, bool level) +{ + DeviceResetInputState *dris; + + dris =3D cold ? &dev->cold_reset_input : &dev->warm_reset_input; + + if (level =3D=3D dris->state) { + /* io state has not changed */ + return; + } + + dris->state =3D level; + switch (dris->type) { + case DEVICE_ACTIVE_LOW: + level =3D !level; + case DEVICE_ACTIVE_HIGH: + if (level) { + resettable_assert_reset(OBJECT(dev), cold); + } else { + resettable_deassert_reset(OBJECT(dev)); + } + break; + } +} + +static void device_cold_reset_handler(void *opaque, int n, int level) +{ + device_reset_handler((DeviceState *) opaque, true, level); +} + +static void device_warm_reset_handler(void *opaque, int n, int level) +{ + device_reset_handler((DeviceState *) opaque, false, level); +} + +void qdev_init_reset_gpio_in_named(DeviceState *dev, const char *name, + bool cold, DeviceActiveType type) +{ + qemu_irq_handler handler; + + if (cold) { + assert(!dev->cold_reset_input.exists); + dev->cold_reset_input.exists =3D true; + dev->cold_reset_input.type =3D type; + handler =3D device_cold_reset_handler; + } else { + assert(!dev->warm_reset_input.exists); + dev->warm_reset_input.exists =3D true; + dev->warm_reset_input.type =3D type; + handler =3D device_warm_reset_handler; + } + + qdev_init_gpio_in_named(dev, handler, name, 1); +} + void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, const char *name, int n) { @@ -986,6 +1041,8 @@ static void device_initfn(Object *obj) dev->instance_id_alias =3D -1; dev->realized =3D false; dev->resetting =3D 0; + dev->cold_reset_input.exists =3D false; + dev->warm_reset_input.exists =3D false; =20 object_property_add_bool(obj, "realized", device_get_realized, device_set_realized, NUL= L); diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 658a419350..693f79b385 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -134,6 +134,17 @@ struct NamedGPIOList { QLIST_ENTRY(NamedGPIOList) node; }; =20 +typedef enum DeviceActiveType { + DEVICE_ACTIVE_LOW, + DEVICE_ACTIVE_HIGH, +} DeviceActiveType; + +typedef struct DeviceResetInputState { + bool exists; + DeviceActiveType type; + bool state; +} DeviceResetInputState; + /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. @@ -161,6 +172,8 @@ struct DeviceState { int instance_id_alias; int alias_required_for_version; uint32_t resetting; + DeviceResetInputState cold_reset_input; + DeviceResetInputState warm_reset_input; }; =20 struct DeviceListener { @@ -362,6 +375,37 @@ static inline void qdev_init_gpio_in_named(DeviceState= *dev, void qdev_pass_gpios(DeviceState *dev, DeviceState *container, const char *name); =20 +/** + * qdev_init_reset_gpio_in_named: + * Create a gpio controlling the warm or cold reset of the device. + * @cold specify whether it triggers cold or warm reset + * @type what kind of reset io it is + */ +void qdev_init_reset_gpio_in_named(DeviceState *dev, const char *name, + bool cold, DeviceActiveType type); + +/** + * qdev_init_warm_reset_gpio: + * Create a reset input to control the device warm reset. + */ +static inline void qdev_init_warm_reset_gpio(DeviceState *dev, + const char *name, + DeviceActiveType type) +{ + qdev_init_reset_gpio_in_named(dev, name, false, type); +} + +/** + * qdev_init_power_gate_gpio: + * Create a power gate input to control the device cold reset. + */ +static inline void qdev_init_power_gate_gpio(DeviceState *dev, + const char *name, + DeviceActiveType type) +{ + qdev_init_reset_gpio_in_named(dev, name, true, type); +} + BusState *qdev_get_parent_bus(DeviceState *dev); =20 /*** BUS API. ***/ --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 04 Jun 2019 12:25:45 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id E0A7096F60; Tue, 4 Jun 2019 16:25:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665544; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6EFLWJiXnIDh4G42bZanNNuCQdKUk7RN59mJdttTr24=; b=ZiD70jtDlPpOxgyZSBUycnFNnLMtTxgs7BEla/ZZg+FZbMa3Rrir3DjEuDpd9CCSv0a/41 MgMP5wtDyWXyBwcQIWpLTdzNBc5aDDZm6bXowFnyj4KlCkd+gOpafn3FgU5GrwyVsFdnvl GEStZHTm+6xx76hTHPXZsOnW3u3gJaA= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:20 +0200 Message-Id: <20190604162526.10655-7-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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charset="utf-8" The `device_vmstate_reset` can be added by device specialization, as vmsd subsection, to migrate the reset related device state part. It contains the resetting counter and the reset inputs current status. Signed-off-by: Damien Hedde --- hw/core/Makefile.objs | 1 + hw/core/qdev-vmstate.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 6 ++++++ 3 files changed, 41 insertions(+) create mode 100644 hw/core/qdev-vmstate.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 97007454a8..b3b4990005 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -4,6 +4,7 @@ common-obj-y +=3D bus.o reset.o common-obj-y +=3D resettable.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o common-obj-$(CONFIG_SOFTMMU) +=3D fw-path-provider.o +common-obj-$(CONFIG_SOFTMMU) +=3D qdev-vmstate.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o common-obj-y +=3D hotplug.o diff --git a/hw/core/qdev-vmstate.c b/hw/core/qdev-vmstate.c new file mode 100644 index 0000000000..5322b70b0e --- /dev/null +++ b/hw/core/qdev-vmstate.c @@ -0,0 +1,34 @@ +/* + * Device vmstate + * + * Copyright (c) 2019 GreenSocs + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/qdev.h" +#include "migration/vmstate.h" + +static bool device_vmstate_reset_needed(void *opaque) +{ + DeviceState *dev =3D (DeviceState *) opaque; + return dev->resetting; +} + +const struct VMStateDescription device_vmstate_reset =3D { + .name =3D "device_reset", + .version_id =3D 0, + .minimum_version_id =3D 0, + .needed =3D device_vmstate_reset_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(resetting, DeviceState), + VMSTATE_BOOL(cold_reset_input.state, DeviceState), + VMSTATE_BOOL(warm_reset_input.state, DeviceState), + VMSTATE_END_OF_LIST() + } +}; diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 693f79b385..596a5bbead 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -546,4 +546,10 @@ static inline bool qbus_is_hotpluggable(BusState *bus) void device_listener_register(DeviceListener *listener); void device_listener_unregister(DeviceListener *listener); =20 +/** + * device_vmstate_reset: + * vmstate entry for reset related state + */ +extern const struct VMStateDescription device_vmstate_reset; + #endif --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 04 Jun 2019 12:25:46 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id A3A9C96F62; Tue, 4 Jun 2019 16:25:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665545; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uEF2McHRjJAqSo5QcKbdG0zwjTeD+AMnzAukkEqETLw=; b=43MGdX14BxD16FUKTvZJ7yI+l/WUtXXPHuHI6naj/Ujy6TqVc+MUt1jyt5aPTiHQxXmVZJ KzPJ6FWTR8kHxG9gVhxff4fenUTy5cStzcyZ1DRozsSfi//KTnJo5tpd5jouro3koxnOdk WScFg/Z/y7Pf1nzlEW/yjpk8CMl4KJo= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:21 +0200 Message-Id: <20190604162526.10655-8-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Damien Hedde --- docs/devel/reset.txt | 151 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 docs/devel/reset.txt diff --git a/docs/devel/reset.txt b/docs/devel/reset.txt new file mode 100644 index 0000000000..32c211d8ca --- /dev/null +++ b/docs/devel/reset.txt @@ -0,0 +1,151 @@ + +=3D=3D=3D=3D=3D +Reset +=3D=3D=3D=3D=3D + +The reset of qemu objects is handled using the Resettable interface declar= ed +in *include/hw/resettable.h*. +As of now DeviceClass and BusClass implement this interface. + + +Triggering reset +---------------- + +The function *resettable_reset* must be used to trigger a reset on a given +object. +void resettable_reset(Object *obj, bool cold) + +The parameter *obj* must implement the Resettable interface. +The parameter *cold* is a boolean specifying whether to do a cold or warm +reset + +For Devices and Buses there is also the corresponding helpers: +void device_reset(Device *dev, bool cold) +void bus_reset(Device *dev, bool cold) + +If one wants to put an object into a reset state. There is the +*resettable_assert_reset* function. +void resettable_assert_reset(Object *obj, bool cold) + +One must eventually call the function *resettable_deassert_reset* to end t= he +reset state: +void resettable_deassert_reset(Object *obj, bool cold) + +Calling *resettable_assert_reset* then *resettable_deassert_reset* is the +same as calling *resettable_reset*. + +It is possible to interleave multiple calls to + - resettable_reset, + - resettable_assert_reset, and + - resettable_deassert_reset. +The only constraint is that *resettable_deassert_reset* must be called once +per *resettable_assert_reset* call so that the object leaves the reset sta= te. + +Therefore there may be several reset sources/controllers of a given object. +The interface handle everything and the controllers do not need to know +anything about each others. The object will leave reset state only when all +controllers released their reset. + +All theses functions must called while holding the iothread lock. + + +Implementing reset for a Resettable object : Multi-phase reset +-------------------------------------------------------------- + +The Resettable uses a multi-phase mechanism to handle some ordering constr= aints +when resetting multiple object at the same time. For a given object the re= set +procedure is split into three different phases executed in order: + 1 INIT: This phase should set/reset the state of the Resettable it has wh= en is + in reset state. Side-effects to others object is forbidden (such = as + setting IO level). + 2 HOLD: This phase corresponds to the external side-effects due to stayin= g into + the reset state. + 3 EXIT: This phase corresponds to leaving the reset state. It have both + local and external effects. + +*resettable_assert_reset* does the INIT and HOLD phases. While +*resettable_deassert_reset* does the EXIT phase. + +When resetting multiple object at the same time. The interface executes the +given phase of the objects before going to the next phase. This guarantee = that +all INIT phases are done before any HOLD phase and so on. + +There is three methods in the interface so must be implemented in an objec= t. +The methods corresponds to the three phases: +``` +typedef void (*ResettableInitPhase)(Object *obj, bool cold); +typedef void (*ResettableHoldPhase)(Object *obj); +typedef void (*ResettableExitPhase)(Object *obj); +typedef struct ResettableClass { + InterfaceClass parent_class; + + struct ResettablePhases { + ResettableInitPhase init; + ResettableHoldPhase hold; + ResettableExitPhase exit; + } phases; + [...] +} ResettableClass; +``` + +Note that only the init method takes the bool parameter, if the warm/cold +information is needed by other methods it should be stored somewhere in the +object state. + +Theses methods should be updated when specializing an object. For this the +helper function *resettable_class_set_parent_reset_phases* can be used to +backup parent methods while changing the specialized ones. +void resettable_class_set_parent_reset_phases(ResettableClass *rc, + ResettableInitPhase init, + ResettableHoldPhase hold, + ResettableExitPhase exit, + ResettablePhases *parent_pha= ses); + + +Implementing the base Resettable behavior : Re-entrance and Hierarchy +--------------------------------------------------------------------- + +There is four others methods in the interface to handle the base mechanics +of the Resettable interface. The methods should be implemented in object +base class. DeviceClass and BusClass implement them. + +``` +typedef uint32_t (*ResettableGetCount)(Object *obj); +typedef uint32_t (*ResettableIncrementCount)(Object *obj); +typedef uint32_t (*ResettableDecrementCount)(Object *obj); +typedef void (*ResettableForeachChild)(Object *obj, void (*visitor)(Object= *)); +typedef struct ResettableClass { + InterfaceClass parent_class; + + [...] + + ResettableGetCount get_count; + ResettableIncrementCount increment_count; + ResettableDecrementCount decrement_count; + ResettableForeachChild foreach_child; +} ResettableClass; +``` + +As stated above, several reset procedures can be concurrent on an object. +This is handled with the three methods *get_count*, *increment_count* and +*decrement_count*. An object is in reset state if the count is non-zero. + +The reset hierarchy is handled using the *foreach_child* method. This meth= od +executes a given function on every reset "child". + +In DeviceClass and BusClass the base behavior is to mimic the legacy qdev +reset. Reset hierarchy follows the qdev/qbus tree. + +Reset control through GPIO +-------------------------- + +For devices, two reset inputs can be added: one for the cold, one the warm +reset. This is done using the following function. +``` +typedef enum DeviceActiveType { + DEVICE_ACTIVE_LOW, + DEVICE_ACTIVE_HIGH, +} DeviceActiveType; +void qdev_init_reset_gpio_in_named(DeviceState *dev, const char *name, + bool cold, DeviceActiveType type); +``` --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559666279115696.8247692306817; Tue, 4 Jun 2019 09:37:59 -0700 (PDT) Received: from localhost ([127.0.0.1]:55231 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCRf-0001gX-0Q for importer@patchew.org; Tue, 04 Jun 2019 12:37:55 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39417) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCG4-0000gS-C5 for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYCG2-0003lV-5H for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:56 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40598) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYCFv-0003Z8-75; Tue, 04 Jun 2019 12:25:47 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 690D896F64; Tue, 4 Jun 2019 16:25:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665546; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0bJ2hum2zlr7bPGpjXAx9UrpHQAtmrB+tmkWJ+2Db6o=; b=cupCbfY/c38/4Fa549e83aLPcyslcYG+vadchgf/DCCpdhnj0cCqwbLWSeoMFhgpsqvBXK pvrsSfutA316A6avuUa2jlG87QlyJSdb+5tNbxeyoHSWlk1X9mBrxxh631zf4C9pYDbB5r oe295ypi/itX1UmcqSUT961pTQ0tkBc= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:22 +0200 Message-Id: <20190604162526.10655-9-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665546; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0bJ2hum2zlr7bPGpjXAx9UrpHQAtmrB+tmkWJ+2Db6o=; b=VM7NhyT0bGcC5JNLhKibEIcn3pv+8hoemtD97LF0v9B//IS9f4pej+H+Q99M49s2vdE6T+ R+IbsMYAqrSF6lGbbEGLJFofTbad/1WjSoJvA0PtMhrBbsSs7zjZRAB8dXQazTMNtpUXrm Nd3ZCzKCAjRVPO1X5DbZT99iOhsPfww= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1559665546; a=rsa-sha256; cv=none; b=y1u/f/Z5lK8c6oZDXZterOSFQtvTP2NbrewoeJxjZLMUSigfjyHgND/+BnrMh36r/NXsu3 DMxeXi9jEAxFxDMmq1ht3yCdroRIEM16ckFG0tdY2/bEx0Q++K9+5FW2Nju9aTiN74ubbU tVOXdITBCiOeIQIH3p/hlvPdPJii1Eo= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [RFC PATCH v2 08/12] hw/misc/zynq_slcr: use standard register definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, Alistair Francis , marc.burton@greensocs.com, alistair@alistair23.me, qemu-arm@nongnu.org, Damien Hedde , marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Replace the zynq_slcr registers enum and macros using the hw/registerfields.h macros. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/misc/zynq_slcr.c | 472 ++++++++++++++++++++++---------------------- 1 file changed, 236 insertions(+), 236 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d6bdd027ef..baa13d1316 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "qemu/log.h" +#include "hw/registerfields.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -35,138 +36,135 @@ #define XILINX_LOCK_KEY 0x767b #define XILINX_UNLOCK_KEY 0xdf0d =20 -#define R_PSS_RST_CTRL_SOFT_RST 0x1 - -enum { - SCL =3D 0x000 / 4, - LOCK, - UNLOCK, - LOCKSTA, - - ARM_PLL_CTRL =3D 0x100 / 4, - DDR_PLL_CTRL, - IO_PLL_CTRL, - PLL_STATUS, - ARM_PLL_CFG, - DDR_PLL_CFG, - IO_PLL_CFG, - - ARM_CLK_CTRL =3D 0x120 / 4, - DDR_CLK_CTRL, - DCI_CLK_CTRL, - APER_CLK_CTRL, - USB0_CLK_CTRL, - USB1_CLK_CTRL, - GEM0_RCLK_CTRL, - GEM1_RCLK_CTRL, - GEM0_CLK_CTRL, - GEM1_CLK_CTRL, - SMC_CLK_CTRL, - LQSPI_CLK_CTRL, - SDIO_CLK_CTRL, - UART_CLK_CTRL, - SPI_CLK_CTRL, - CAN_CLK_CTRL, - CAN_MIOCLK_CTRL, - DBG_CLK_CTRL, - PCAP_CLK_CTRL, - TOPSW_CLK_CTRL, +REG32(SCL, 0x000) +REG32(LOCK, 0x004) +REG32(UNLOCK, 0x008) +REG32(LOCKSTA, 0x00c) + +REG32(ARM_PLL_CTRL, 0x100) +REG32(DDR_PLL_CTRL, 0x104) +REG32(IO_PLL_CTRL, 0x108) +REG32(PLL_STATUS, 0x10c) +REG32(ARM_PLL_CFG, 0x110) +REG32(DDR_PLL_CFG, 0x114) +REG32(IO_PLL_CFG, 0x118) + +REG32(ARM_CLK_CTRL, 0x120) +REG32(DDR_CLK_CTRL, 0x124) +REG32(DCI_CLK_CTRL, 0x128) +REG32(APER_CLK_CTRL, 0x12c) +REG32(USB0_CLK_CTRL, 0x130) +REG32(USB1_CLK_CTRL, 0x134) +REG32(GEM0_RCLK_CTRL, 0x138) +REG32(GEM1_RCLK_CTRL, 0x13c) +REG32(GEM0_CLK_CTRL, 0x140) +REG32(GEM1_CLK_CTRL, 0x144) +REG32(SMC_CLK_CTRL, 0x148) +REG32(LQSPI_CLK_CTRL, 0x14c) +REG32(SDIO_CLK_CTRL, 0x150) +REG32(UART_CLK_CTRL, 0x154) +REG32(SPI_CLK_CTRL, 0x158) +REG32(CAN_CLK_CTRL, 0x15c) +REG32(CAN_MIOCLK_CTRL, 0x160) +REG32(DBG_CLK_CTRL, 0x164) +REG32(PCAP_CLK_CTRL, 0x168) +REG32(TOPSW_CLK_CTRL, 0x16c) =20 #define FPGA_CTRL_REGS(n, start) \ - FPGA ## n ## _CLK_CTRL =3D (start) / 4, \ - FPGA ## n ## _THR_CTRL, \ - FPGA ## n ## _THR_CNT, \ - FPGA ## n ## _THR_STA, - FPGA_CTRL_REGS(0, 0x170) - FPGA_CTRL_REGS(1, 0x180) - FPGA_CTRL_REGS(2, 0x190) - FPGA_CTRL_REGS(3, 0x1a0) - - BANDGAP_TRIP =3D 0x1b8 / 4, - PLL_PREDIVISOR =3D 0x1c0 / 4, - CLK_621_TRUE, - - PSS_RST_CTRL =3D 0x200 / 4, - DDR_RST_CTRL, - TOPSW_RESET_CTRL, - DMAC_RST_CTRL, - USB_RST_CTRL, - GEM_RST_CTRL, - SDIO_RST_CTRL, - SPI_RST_CTRL, - CAN_RST_CTRL, - I2C_RST_CTRL, - UART_RST_CTRL, - GPIO_RST_CTRL, - LQSPI_RST_CTRL, - SMC_RST_CTRL, - OCM_RST_CTRL, - FPGA_RST_CTRL =3D 0x240 / 4, - A9_CPU_RST_CTRL, - - RS_AWDT_CTRL =3D 0x24c / 4, - RST_REASON, - - REBOOT_STATUS =3D 0x258 / 4, - BOOT_MODE, - - APU_CTRL =3D 0x300 / 4, - WDT_CLK_SEL, - - TZ_DMA_NS =3D 0x440 / 4, - TZ_DMA_IRQ_NS, - TZ_DMA_PERIPH_NS, - - PSS_IDCODE =3D 0x530 / 4, - - DDR_URGENT =3D 0x600 / 4, - DDR_CAL_START =3D 0x60c / 4, - DDR_REF_START =3D 0x614 / 4, - DDR_CMD_STA, - DDR_URGENT_SEL, - DDR_DFI_STATUS, - - MIO =3D 0x700 / 4, + REG32(FPGA ## n ## _CLK_CTRL, (start)) \ + REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\ + REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\ + REG32(FPGA ## n ## _THR_STA, (start) + 0xc) +FPGA_CTRL_REGS(0, 0x170) +FPGA_CTRL_REGS(1, 0x180) +FPGA_CTRL_REGS(2, 0x190) +FPGA_CTRL_REGS(3, 0x1a0) + +REG32(BANDGAP_TRIP, 0x1b8) +REG32(PLL_PREDIVISOR, 0x1c0) +REG32(CLK_621_TRUE, 0x1c4) + +REG32(PSS_RST_CTRL, 0x200) + FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) +REG32(DDR_RST_CTRL, 0x204) +REG32(TOPSW_RESET_CTRL, 0x208) +REG32(DMAC_RST_CTRL, 0x20c) +REG32(USB_RST_CTRL, 0x210) +REG32(GEM_RST_CTRL, 0x214) +REG32(SDIO_RST_CTRL, 0x218) +REG32(SPI_RST_CTRL, 0x21c) +REG32(CAN_RST_CTRL, 0x220) +REG32(I2C_RST_CTRL, 0x224) +REG32(UART_RST_CTRL, 0x228) +REG32(GPIO_RST_CTRL, 0x22c) +REG32(LQSPI_RST_CTRL, 0x230) +REG32(SMC_RST_CTRL, 0x234) +REG32(OCM_RST_CTRL, 0x238) +REG32(FPGA_RST_CTRL, 0x240) +REG32(A9_CPU_RST_CTRL, 0x244) + +REG32(RS_AWDT_CTRL, 0x24c) +REG32(RST_REASON, 0x250) + +REG32(REBOOT_STATUS, 0x258) +REG32(BOOT_MODE, 0x25c) + +REG32(APU_CTRL, 0x300) +REG32(WDT_CLK_SEL, 0x304) + +REG32(TZ_DMA_NS, 0x440) +REG32(TZ_DMA_IRQ_NS, 0x444) +REG32(TZ_DMA_PERIPH_NS, 0x448) + +REG32(PSS_IDCODE, 0x530) + +REG32(DDR_URGENT, 0x600) +REG32(DDR_CAL_START, 0x60c) +REG32(DDR_REF_START, 0x614) +REG32(DDR_CMD_STA, 0x618) +REG32(DDR_URGENT_SEL, 0x61c) +REG32(DDR_DFI_STATUS, 0x620) + +REG32(MIO, 0x700) #define MIO_LENGTH 54 =20 - MIO_LOOPBACK =3D 0x804 / 4, - MIO_MST_TRI0, - MIO_MST_TRI1, +REG32(MIO_LOOPBACK, 0x804) +REG32(MIO_MST_TRI0, 0x808) +REG32(MIO_MST_TRI1, 0x80c) =20 - SD0_WP_CD_SEL =3D 0x830 / 4, - SD1_WP_CD_SEL, +REG32(SD0_WP_CD_SEL, 0x830) +REG32(SD1_WP_CD_SEL, 0x834) =20 - LVL_SHFTR_EN =3D 0x900 / 4, - OCM_CFG =3D 0x910 / 4, +REG32(LVL_SHFTR_EN, 0x900) +REG32(OCM_CFG, 0x910) =20 - CPU_RAM =3D 0xa00 / 4, +REG32(CPU_RAM, 0xa00) =20 - IOU =3D 0xa30 / 4, +REG32(IOU, 0xa30) =20 - DMAC_RAM =3D 0xa50 / 4, +REG32(DMAC_RAM, 0xa50) =20 - AFI0 =3D 0xa60 / 4, - AFI1 =3D AFI0 + 3, - AFI2 =3D AFI1 + 3, - AFI3 =3D AFI2 + 3, +REG32(AFI0, 0xa60) +REG32(AFI1, 0xa6c) +REG32(AFI2, 0xa78) +REG32(AFI3, 0xa84) #define AFI_LENGTH 3 =20 - OCM =3D 0xa90 / 4, +REG32(OCM, 0xa90) =20 - DEVCI_RAM =3D 0xaa0 / 4, +REG32(DEVCI_RAM, 0xaa0) =20 - CSG_RAM =3D 0xab0 / 4, +REG32(CSG_RAM, 0xab0) =20 - GPIOB_CTRL =3D 0xb00 / 4, - GPIOB_CFG_CMOS18, - GPIOB_CFG_CMOS25, - GPIOB_CFG_CMOS33, - GPIOB_CFG_HSTL =3D 0xb14 / 4, - GPIOB_DRVR_BIAS_CTRL, +REG32(GPIOB_CTRL, 0xb00) +REG32(GPIOB_CFG_CMOS18, 0xb04) +REG32(GPIOB_CFG_CMOS25, 0xb08) +REG32(GPIOB_CFG_CMOS33, 0xb0c) +REG32(GPIOB_CFG_HSTL, 0xb14) +REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) =20 - DDRIOB =3D 0xb40 / 4, +REG32(DDRIOB, 0xb40) #define DDRIOB_LENGTH 14 -}; =20 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) @@ -189,150 +187,152 @@ static void zynq_slcr_reset(DeviceState *d) =20 DB_PRINT("RESET\n"); =20 - s->regs[LOCKSTA] =3D 1; + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ - s->regs[ARM_PLL_CTRL] =3D 0x0001A008; - s->regs[DDR_PLL_CTRL] =3D 0x0001A008; - s->regs[IO_PLL_CTRL] =3D 0x0001A008; - s->regs[PLL_STATUS] =3D 0x0000003F; - s->regs[ARM_PLL_CFG] =3D 0x00014000; - s->regs[DDR_PLL_CFG] =3D 0x00014000; - s->regs[IO_PLL_CFG] =3D 0x00014000; + s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; + s->regs[R_DDR_PLL_CTRL] =3D 0x0001A008; + s->regs[R_IO_PLL_CTRL] =3D 0x0001A008; + s->regs[R_PLL_STATUS] =3D 0x0000003F; + s->regs[R_ARM_PLL_CFG] =3D 0x00014000; + s->regs[R_DDR_PLL_CFG] =3D 0x00014000; + s->regs[R_IO_PLL_CFG] =3D 0x00014000; =20 /* 0x120 - 0x16C */ - s->regs[ARM_CLK_CTRL] =3D 0x1F000400; - s->regs[DDR_CLK_CTRL] =3D 0x18400003; - s->regs[DCI_CLK_CTRL] =3D 0x01E03201; - s->regs[APER_CLK_CTRL] =3D 0x01FFCCCD; - s->regs[USB0_CLK_CTRL] =3D s->regs[USB1_CLK_CTRL] =3D 0x00101941; - s->regs[GEM0_RCLK_CTRL] =3D s->regs[GEM1_RCLK_CTRL] =3D 0x00000001; - s->regs[GEM0_CLK_CTRL] =3D s->regs[GEM1_CLK_CTRL] =3D 0x00003C01; - s->regs[SMC_CLK_CTRL] =3D 0x00003C01; - s->regs[LQSPI_CLK_CTRL] =3D 0x00002821; - s->regs[SDIO_CLK_CTRL] =3D 0x00001E03; - s->regs[UART_CLK_CTRL] =3D 0x00003F03; - s->regs[SPI_CLK_CTRL] =3D 0x00003F03; - s->regs[CAN_CLK_CTRL] =3D 0x00501903; - s->regs[DBG_CLK_CTRL] =3D 0x00000F03; - s->regs[PCAP_CLK_CTRL] =3D 0x00000F01; + s->regs[R_ARM_CLK_CTRL] =3D 0x1F000400; + s->regs[R_DDR_CLK_CTRL] =3D 0x18400003; + s->regs[R_DCI_CLK_CTRL] =3D 0x01E03201; + s->regs[R_APER_CLK_CTRL] =3D 0x01FFCCCD; + s->regs[R_USB0_CLK_CTRL] =3D s->regs[R_USB1_CLK_CTRL] =3D 0x00101941; + s->regs[R_GEM0_RCLK_CTRL] =3D s->regs[R_GEM1_RCLK_CTRL] =3D 0x00000001; + s->regs[R_GEM0_CLK_CTRL] =3D s->regs[R_GEM1_CLK_CTRL] =3D 0x00003C01; + s->regs[R_SMC_CLK_CTRL] =3D 0x00003C01; + s->regs[R_LQSPI_CLK_CTRL] =3D 0x00002821; + s->regs[R_SDIO_CLK_CTRL] =3D 0x00001E03; + s->regs[R_UART_CLK_CTRL] =3D 0x00003F03; + s->regs[R_SPI_CLK_CTRL] =3D 0x00003F03; + s->regs[R_CAN_CLK_CTRL] =3D 0x00501903; + s->regs[R_DBG_CLK_CTRL] =3D 0x00000F03; + s->regs[R_PCAP_CLK_CTRL] =3D 0x00000F01; =20 /* 0x170 - 0x1AC */ - s->regs[FPGA0_CLK_CTRL] =3D s->regs[FPGA1_CLK_CTRL] =3D s->regs[FPGA2_= CLK_CTRL] - =3D s->regs[FPGA3_CLK_CTRL] =3D 0x00101800; - s->regs[FPGA0_THR_STA] =3D s->regs[FPGA1_THR_STA] =3D s->regs[FPGA2_TH= R_STA] - =3D s->regs[FPGA3_THR_STA] =3D 0x00010000; + s->regs[R_FPGA0_CLK_CTRL] =3D s->regs[R_FPGA1_CLK_CTRL] + =3D s->regs[R_FPGA2_CLK_CTRL] + =3D s->regs[R_FPGA3_CLK_CTRL] =3D 0x00101800; + s->regs[R_FPGA0_THR_STA] =3D s->regs[R_FPGA1_THR_STA] + =3D s->regs[R_FPGA2_THR_STA] + =3D s->regs[R_FPGA3_THR_STA] =3D 0x00010000; =20 /* 0x1B0 - 0x1D8 */ - s->regs[BANDGAP_TRIP] =3D 0x0000001F; - s->regs[PLL_PREDIVISOR] =3D 0x00000001; - s->regs[CLK_621_TRUE] =3D 0x00000001; + s->regs[R_BANDGAP_TRIP] =3D 0x0000001F; + s->regs[R_PLL_PREDIVISOR] =3D 0x00000001; + s->regs[R_CLK_621_TRUE] =3D 0x00000001; =20 /* 0x200 - 0x25C */ - s->regs[FPGA_RST_CTRL] =3D 0x01F33F0F; - s->regs[RST_REASON] =3D 0x00000040; + s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; + s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D 0x00000001; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { - s->regs[MIO + i] =3D 0x00001601; + s->regs[R_MIO + i] =3D 0x00001601; } for (i =3D 2; i <=3D 8; i++) { - s->regs[MIO + i] =3D 0x00000601; + s->regs[R_MIO + i] =3D 0x00000601; } =20 - s->regs[MIO_MST_TRI0] =3D s->regs[MIO_MST_TRI1] =3D 0xFFFFFFFF; + s->regs[R_MIO_MST_TRI0] =3D s->regs[R_MIO_MST_TRI1] =3D 0xFFFFFFFF; =20 - s->regs[CPU_RAM + 0] =3D s->regs[CPU_RAM + 1] =3D s->regs[CPU_RAM + 3] - =3D s->regs[CPU_RAM + 4] =3D s->regs[CPU_RAM + 7] - =3D 0x00010101; - s->regs[CPU_RAM + 2] =3D s->regs[CPU_RAM + 5] =3D 0x01010101; - s->regs[CPU_RAM + 6] =3D 0x00000001; + s->regs[R_CPU_RAM + 0] =3D s->regs[R_CPU_RAM + 1] =3D s->regs[R_CPU_RA= M + 3] + =3D s->regs[R_CPU_RAM + 4] =3D s->regs[R_CPU_RA= M + 7] + =3D 0x00010101; + s->regs[R_CPU_RAM + 2] =3D s->regs[R_CPU_RAM + 5] =3D 0x01010101; + s->regs[R_CPU_RAM + 6] =3D 0x00000001; =20 - s->regs[IOU + 0] =3D s->regs[IOU + 1] =3D s->regs[IOU + 2] =3D s->regs= [IOU + 3] - =3D 0x09090909; - s->regs[IOU + 4] =3D s->regs[IOU + 5] =3D 0x00090909; - s->regs[IOU + 6] =3D 0x00000909; + s->regs[R_IOU + 0] =3D s->regs[R_IOU + 1] =3D s->regs[R_IOU + 2] + =3D s->regs[R_IOU + 3] =3D 0x09090909; + s->regs[R_IOU + 4] =3D s->regs[R_IOU + 5] =3D 0x00090909; + s->regs[R_IOU + 6] =3D 0x00000909; =20 - s->regs[DMAC_RAM] =3D 0x00000009; + s->regs[R_DMAC_RAM] =3D 0x00000009; =20 - s->regs[AFI0 + 0] =3D s->regs[AFI0 + 1] =3D 0x09090909; - s->regs[AFI1 + 0] =3D s->regs[AFI1 + 1] =3D 0x09090909; - s->regs[AFI2 + 0] =3D s->regs[AFI2 + 1] =3D 0x09090909; - s->regs[AFI3 + 0] =3D s->regs[AFI3 + 1] =3D 0x09090909; - s->regs[AFI0 + 2] =3D s->regs[AFI1 + 2] =3D s->regs[AFI2 + 2] - =3D s->regs[AFI3 + 2] =3D 0x00000909; + s->regs[R_AFI0 + 0] =3D s->regs[R_AFI0 + 1] =3D 0x09090909; + s->regs[R_AFI1 + 0] =3D s->regs[R_AFI1 + 1] =3D 0x09090909; + s->regs[R_AFI2 + 0] =3D s->regs[R_AFI2 + 1] =3D 0x09090909; + s->regs[R_AFI3 + 0] =3D s->regs[R_AFI3 + 1] =3D 0x09090909; + s->regs[R_AFI0 + 2] =3D s->regs[R_AFI1 + 2] =3D s->regs[R_AFI2 + 2] + =3D s->regs[R_AFI3 + 2] =3D 0x00000909; =20 - s->regs[OCM + 0] =3D 0x01010101; - s->regs[OCM + 1] =3D s->regs[OCM + 2] =3D 0x09090909; + s->regs[R_OCM + 0] =3D 0x01010101; + s->regs[R_OCM + 1] =3D s->regs[R_OCM + 2] =3D 0x09090909; =20 - s->regs[DEVCI_RAM] =3D 0x00000909; - s->regs[CSG_RAM] =3D 0x00000001; + s->regs[R_DEVCI_RAM] =3D 0x00000909; + s->regs[R_CSG_RAM] =3D 0x00000001; =20 - s->regs[DDRIOB + 0] =3D s->regs[DDRIOB + 1] =3D s->regs[DDRIOB + 2] - =3D s->regs[DDRIOB + 3] =3D 0x00000e00; - s->regs[DDRIOB + 4] =3D s->regs[DDRIOB + 5] =3D s->regs[DDRIOB + 6] - =3D 0x00000e00; - s->regs[DDRIOB + 12] =3D 0x00000021; + s->regs[R_DDRIOB + 0] =3D s->regs[R_DDRIOB + 1] =3D s->regs[R_DDRIOB += 2] + =3D s->regs[R_DDRIOB + 3] =3D 0x00000e00; + s->regs[R_DDRIOB + 4] =3D s->regs[R_DDRIOB + 5] =3D s->regs[R_DDRIOB += 6] + =3D 0x00000e00; + s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 =20 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { switch (offset) { - case LOCK: - case UNLOCK: - case DDR_CAL_START: - case DDR_REF_START: + case R_LOCK: + case R_UNLOCK: + case R_DDR_CAL_START: + case R_DDR_REF_START: return !rnw; /* Write only */ - case LOCKSTA: - case FPGA0_THR_STA: - case FPGA1_THR_STA: - case FPGA2_THR_STA: - case FPGA3_THR_STA: - case BOOT_MODE: - case PSS_IDCODE: - case DDR_CMD_STA: - case DDR_DFI_STATUS: - case PLL_STATUS: + case R_LOCKSTA: + case R_FPGA0_THR_STA: + case R_FPGA1_THR_STA: + case R_FPGA2_THR_STA: + case R_FPGA3_THR_STA: + case R_BOOT_MODE: + case R_PSS_IDCODE: + case R_DDR_CMD_STA: + case R_DDR_DFI_STATUS: + case R_PLL_STATUS: return rnw;/* read only */ - case SCL: - case ARM_PLL_CTRL ... IO_PLL_CTRL: - case ARM_PLL_CFG ... IO_PLL_CFG: - case ARM_CLK_CTRL ... TOPSW_CLK_CTRL: - case FPGA0_CLK_CTRL ... FPGA0_THR_CNT: - case FPGA1_CLK_CTRL ... FPGA1_THR_CNT: - case FPGA2_CLK_CTRL ... FPGA2_THR_CNT: - case FPGA3_CLK_CTRL ... FPGA3_THR_CNT: - case BANDGAP_TRIP: - case PLL_PREDIVISOR: - case CLK_621_TRUE: - case PSS_RST_CTRL ... A9_CPU_RST_CTRL: - case RS_AWDT_CTRL: - case RST_REASON: - case REBOOT_STATUS: - case APU_CTRL: - case WDT_CLK_SEL: - case TZ_DMA_NS ... TZ_DMA_PERIPH_NS: - case DDR_URGENT: - case DDR_URGENT_SEL: - case MIO ... MIO + MIO_LENGTH - 1: - case MIO_LOOPBACK ... MIO_MST_TRI1: - case SD0_WP_CD_SEL: - case SD1_WP_CD_SEL: - case LVL_SHFTR_EN: - case OCM_CFG: - case CPU_RAM: - case IOU: - case DMAC_RAM: - case AFI0 ... AFI3 + AFI_LENGTH - 1: - case OCM: - case DEVCI_RAM: - case CSG_RAM: - case GPIOB_CTRL ... GPIOB_CFG_CMOS33: - case GPIOB_CFG_HSTL: - case GPIOB_DRVR_BIAS_CTRL: - case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1: + case R_SCL: + case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL: + case R_ARM_PLL_CFG ... R_IO_PLL_CFG: + case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL: + case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT: + case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT: + case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT: + case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT: + case R_BANDGAP_TRIP: + case R_PLL_PREDIVISOR: + case R_CLK_621_TRUE: + case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL: + case R_RS_AWDT_CTRL: + case R_RST_REASON: + case R_REBOOT_STATUS: + case R_APU_CTRL: + case R_WDT_CLK_SEL: + case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS: + case R_DDR_URGENT: + case R_DDR_URGENT_SEL: + case R_MIO ... R_MIO + MIO_LENGTH - 1: + case R_MIO_LOOPBACK ... R_MIO_MST_TRI1: + case R_SD0_WP_CD_SEL: + case R_SD1_WP_CD_SEL: + case R_LVL_SHFTR_EN: + case R_OCM_CFG: + case R_CPU_RAM: + case R_IOU: + case R_DMAC_RAM: + case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1: + case R_OCM: + case R_DEVCI_RAM: + case R_CSG_RAM: + case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33: + case R_GPIOB_CFG_HSTL: + case R_GPIOB_DRVR_BIAS_CTRL: + case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1: return true; default: return false; @@ -370,24 +370,24 @@ static void zynq_slcr_write(void *opaque, hwaddr offs= et, } =20 switch (offset) { - case SCL: - s->regs[SCL] =3D val & 0x1; + case R_SCL: + s->regs[R_SCL] =3D val & 0x1; return; - case LOCK: + case R_LOCK: if ((val & 0xFFFF) =3D=3D XILINX_LOCK_KEY) { DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <=3D 0x%x\n", (int)off= set, (unsigned)val & 0xFFFF); - s->regs[LOCKSTA] =3D 1; + s->regs[R_LOCKSTA] =3D 1; } else { DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <=3D 0x%x\n", (int)offset, (unsigned)val & 0xFFFF); } return; - case UNLOCK: + case R_UNLOCK: if ((val & 0xFFFF) =3D=3D XILINX_UNLOCK_KEY) { DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <=3D 0x%x\n", (int)o= ffset, (unsigned)val & 0xFFFF); - s->regs[LOCKSTA] =3D 0; + s->regs[R_LOCKSTA] =3D 0; } else { DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <=3D 0x%x\= n", (int)offset, (unsigned)val & 0xFFFF); @@ -395,7 +395,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, return; } =20 - if (s->regs[LOCKSTA]) { + if (s->regs[R_LOCKSTA]) { qemu_log_mask(LOG_GUEST_ERROR, "SCLR registers are locked. Unlock them first\n"); return; @@ -403,8 +403,8 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, s->regs[offset] =3D val; =20 switch (offset) { - case PSS_RST_CTRL: - if (val & R_PSS_RST_CTRL_SOFT_RST) { + case R_PSS_RST_CTRL: + if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559666403748753.0802472114773; Tue, 4 Jun 2019 09:40:03 -0700 (PDT) Received: from localhost ([127.0.0.1]:55249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCTf-0003Gh-KF for importer@patchew.org; Tue, 04 Jun 2019 12:39:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39378) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYCG1-0000dC-Qh for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYCFz-0003iJ-Tw for qemu-devel@nongnu.org; Tue, 04 Jun 2019 12:25:53 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:40616) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYCFw-0003aF-0A; Tue, 04 Jun 2019 12:25:48 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 6D65596F66; Tue, 4 Jun 2019 16:25:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RJnlyxIty4fLwwQiMvBz/j1I0JzfWGjMPHXoCBbOxXs=; b=PT2EjDQG9SJEPXNUE6DFCZ7TwXTh4S2WsycqvJATPQeQXxlgLNoUWOaOx6XMZfBuo7RnRq wRc80TYY6eZvDkWFKnsOneHWCiBNJT8SgdAnnJlxa08ihAe5oMNY7CQlSurrInpKTRR/xS SVyLvpwYVjinOCDbQrtUyRifYv18R4M= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:23 +0200 Message-Id: <20190604162526.10655-10-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RJnlyxIty4fLwwQiMvBz/j1I0JzfWGjMPHXoCBbOxXs=; b=5uFxHyoMJ2onrUfU8x44gQER65ssz+/p2HTTsBcFh5gg3GjCcgwrRwg/zEvazjZuQpPg26 kkcAITaYgsXXfP1RZdJdjKk9HCBBjKDk+LlGUs26rEUdMxSviIBfhieNvOQDmilDFZr6m4 BfDLyQsDGcnHrAZXkq1B6FD1ljZ4PwY= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1559665547; a=rsa-sha256; cv=none; b=FAQQqQEQH7sumjpQLjQjDjevuovkwfVfkjmWRjiJFXUZmp0pb+HxgRimaHhQMfopISsZLQ CbVUMJBF1NW0xPVBOLNAa1vQ8z0TOS+IanVTmJ09DGIrCmz3xjhHpfnzM2Jvtx7gvp+/a3 pNLqqqe//UmTp3XqsuPIqkIXvmNgFnE= ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=damien smtp.mailfrom=damien.hedde@greensocs.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [RFC PATCH v2 09/12] convert cadence_uart to 3-phases reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, marc.burton@greensocs.com, alistair@alistair23.me, qemu-arm@nongnu.org, Damien Hedde , marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Split the existing reset procedure into 3 phases. Test the resetting flag to discard register accesses and character reception. Also adds a active high reset io. Signed-off-by: Damien Hedde --- hw/char/cadence_uart.c | 81 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fbdbd463bb..27e1c70678 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -38,6 +38,18 @@ #define DB_PRINT(...) #endif =20 +#define CADENCE_UART_CLASS(class) \ + OBJECT_CLASS_CHECK(CadenceUartClass, (class), TYPE_CADENCE_UART) +#define CADENCE_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(CadenceUartClass, (obj), TYPE_CADENCE_UART) + +typedef struct CadenceUartClass { + /*< private >*/ + SysBusDeviceClass parent_class; + + struct ResettablePhases parent_reset_phases; +} CadenceUartClass; + #define UART_SR_INTR_RTRIG 0x00000001 #define UART_SR_INTR_REMPTY 0x00000002 #define UART_SR_INTR_RFUL 0x00000004 @@ -222,6 +234,10 @@ static int uart_can_receive(void *opaque) int ret =3D MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + if (device_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { ret =3D MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); } @@ -337,6 +353,10 @@ static void uart_receive(void *opaque, const uint8_t *= buf, int size) CadenceUARTState *s =3D opaque; uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + if (device_is_resetting((DeviceState *) opaque)) { + return; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -350,6 +370,10 @@ static void uart_event(void *opaque, int event) CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; =20 + if (device_is_resetting((DeviceState *) opaque)) { + return; + } + if (event =3D=3D CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -382,6 +406,10 @@ static void uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s =3D opaque; =20 + if (device_is_resetting((DeviceState *)opaque)) { + return; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { @@ -440,6 +468,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset, CadenceUARTState *s =3D opaque; uint32_t c =3D 0; =20 + if (device_is_resetting((DeviceState *)opaque)) { + return 0; + } + offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { c =3D 0; @@ -459,9 +491,14 @@ static const MemoryRegionOps uart_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, bool cold) { - CadenceUARTState *s =3D CADENCE_UART(dev); + CadenceUARTState *s =3D CADENCE_UART(obj); + CadenceUartClass *cc =3D CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.init) { + cc->parent_reset_phases.init(obj, cold); + } =20 s->r[R_CR] =3D 0x00000128; s->r[R_IMR] =3D 0; @@ -470,6 +507,28 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] =3D 0x0000028B; s->r[R_BDIV] =3D 0x0000000F; s->r[R_TTRIG] =3D 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); + CadenceUartClass *cc =3D CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.hold) { + cc->parent_reset_phases.hold(obj); + } + + qemu_set_irq(s->irq, 0); +} + +static void cadence_uart_reset_exit(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); + CadenceUartClass *cc =3D CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.exit) { + cc->parent_reset_phases.exit(obj); + } =20 uart_rx_reset(s); uart_tx_reset(s); @@ -498,6 +557,8 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); =20 s->char_tx_time =3D (NANOSECONDS_PER_SECOND / 9600) * 10; + + qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_ACTIVE_HIGH); } =20 static int cadence_uart_post_load(void *opaque, int version_id) @@ -532,6 +593,10 @@ static const VMStateDescription vmstate_cadence_uart = =3D { VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &device_vmstate_reset, + NULL } }; =20 @@ -543,12 +608,19 @@ static Property cadence_uart_properties[] =3D { static void cadence_uart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + CadenceUartClass *cc =3D CADENCE_UART_CLASS(klass); =20 dc->realize =3D cadence_uart_realize; dc->vmsd =3D &vmstate_cadence_uart; - dc->reset =3D cadence_uart_reset; dc->props =3D cadence_uart_properties; - } + + resettable_class_set_parent_reset_phases(rc, + cadence_uart_reset_init, + cadence_uart_reset_hold, + cadence_uart_reset_exit, + &cc->parent_reset_phases); +} =20 static const TypeInfo cadence_uart_info =3D { .name =3D TYPE_CADENCE_UART, @@ -556,6 +628,7 @@ static const TypeInfo cadence_uart_info =3D { .instance_size =3D sizeof(CadenceUARTState), .instance_init =3D cadence_uart_init, .class_init =3D cadence_uart_class_init, + .class_size =3D sizeof(CadenceUartClass), }; =20 static void cadence_uart_register_types(void) --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 04 Jun 2019 12:25:49 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPSA id 37ADC96F68; Tue, 4 Jun 2019 16:25:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MCCvN1xRL6lomue9uOOMJhghQO1bTT/gZNsAko9dsf4=; b=GmrGNpaGYaj/GCcw6VZxwbrpC4Q1wL85KYRt6NJ4UAJbWHQydp2Zrx7mRA3ZzlRYm5p89i Q4dqcSMo8YvBd98hPHo4RrEiBK5VGkGGcibIuHwfGvN7sO5UKDSk6tgOgi+HAZWT3vWtLx j3NPIw4jAzr4/FZGD47tT12utKWnaxQ= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:24 +0200 Message-Id: <20190604162526.10655-11-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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charset="utf-8" Change the legacy reset function into the init phase and test the resetting flag in register accesses. Signed-off-by: Damien Hedde --- hw/misc/zynq_slcr.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index baa13d1316..c6d2bba966 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -171,6 +171,17 @@ REG32(DDRIOB, 0xb40) =20 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr" #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR) +#define ZYNQ_SLCR_CLASS(class) \ + OBJECT_CLASS_CHECK(ZynqSLCRClass, (class), TYPE_ZYNQ_SLCR) +#define ZYNQ_SLCR_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ZynqSLCRClass, (obj), TYPE_ZYNQ_SLCR) + +typedef struct ZynqSLCRClass { + /*< private >*/ + SysBusDeviceClass parent_class; + + struct ResettablePhases parent_reset_phases; +} ZynqSLCRClass; =20 typedef struct ZynqSLCRState { SysBusDevice parent_obj; @@ -180,13 +191,18 @@ typedef struct ZynqSLCRState { uint32_t regs[ZYNQ_SLCR_NUM_REGS]; } ZynqSLCRState; =20 -static void zynq_slcr_reset(DeviceState *d) +static void zynq_slcr_reset_init(Object *obj, bool cold) { - ZynqSLCRState *s =3D ZYNQ_SLCR(d); + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + ZynqSLCRClass *zc =3D ZYNQ_SLCR_GET_CLASS(obj); int i; =20 DB_PRINT("RESET\n"); =20 + if (zc->parent_reset_phases.init) { + zc->parent_reset_phases.init(obj, cold); + } + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; @@ -276,7 +292,6 @@ static void zynq_slcr_reset(DeviceState *d) s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 - static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { switch (offset) { @@ -346,6 +361,10 @@ static uint64_t zynq_slcr_read(void *opaque, hwaddr of= fset, offset /=3D 4; uint32_t ret =3D s->regs[offset]; =20 + if (device_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (!zynq_slcr_check_offset(offset, true)) { qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " " addr %" HWADDR_PRIx "\n", offset * 4); @@ -361,6 +380,10 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, ZynqSLCRState *s =3D (ZynqSLCRState *)opaque; offset /=3D 4; =20 + if (device_is_resetting((DeviceState *) opaque)) { + return; + } + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4,= val); =20 if (!zynq_slcr_check_offset(offset, false)) { @@ -439,9 +462,16 @@ static const VMStateDescription vmstate_zynq_slcr =3D { static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ZynqSLCRClass *zc =3D ZYNQ_SLCR_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; - dc->reset =3D zynq_slcr_reset; + + resettable_class_set_parent_reset_phases(rc, + zynq_slcr_reset_init, + NULL, + NULL, + &zc->parent_reset_phases); } =20 static const TypeInfo zynq_slcr_info =3D { @@ -450,6 +480,7 @@ static const TypeInfo zynq_slcr_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(ZynqSLCRState), .instance_init =3D zynq_slcr_init, + .class_size =3D sizeof(ZynqSLCRClass), }; =20 static void zynq_slcr_register_types(void) --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add two gpio outputs to control the uart resets. Signed-off-by: Damien Hedde --- hw/misc/zynq_slcr.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index c6d2bba966..6649c93a90 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -96,6 +96,10 @@ REG32(SPI_RST_CTRL, 0x21c) REG32(CAN_RST_CTRL, 0x220) REG32(I2C_RST_CTRL, 0x224) REG32(UART_RST_CTRL, 0x228) + FIELD(UART_RST_CTRL, UART0_CPU1X_RST, 0, 1) + FIELD(UART_RST_CTRL, UART1_CPU1X_RST, 1, 1) + FIELD(UART_RST_CTRL, UART0_REF_RST, 2, 1) + FIELD(UART_RST_CTRL, UART1_REF_RST, 3, 1) REG32(GPIO_RST_CTRL, 0x22c) REG32(LQSPI_RST_CTRL, 0x230) REG32(SMC_RST_CTRL, 0x234) @@ -189,8 +193,14 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; =20 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + qemu_irq uart0_rst; + qemu_irq uart1_rst; } ZynqSLCRState; =20 +#define ZYNQ_SLCR_REGFIELD_TO_OUT(state, irq, reg, field) \ + qemu_set_irq((state)->irq, ARRAY_FIELD_EX32((state)->regs, reg, field)= !=3D 0) + static void zynq_slcr_reset_init(Object *obj, bool cold) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -292,6 +302,24 @@ static void zynq_slcr_reset_init(Object *obj, bool col= d) s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 +static void zynq_slcr_compute_uart_reset(ZynqSLCRState *s) +{ + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart0_rst, UART_RST_CTRL, UART0_REF_RST); + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart1_rst, UART_RST_CTRL, UART1_REF_RST); +} + +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + ZynqSLCRClass *zc =3D ZYNQ_SLCR_GET_CLASS(obj); + + if (zc->parent_reset_phases.hold) { + zc->parent_reset_phases.hold(obj); + } + + zynq_slcr_compute_uart_reset(s); +} + static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { switch (offset) { @@ -431,6 +459,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_UART_RST_CTRL: + zynq_slcr_compute_uart_reset(s); + break; } } =20 @@ -447,6 +478,9 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_gpio_out_named(DEVICE(obj), &s->uart0_rst, "uart0_rst", 1); + qdev_init_gpio_out_named(DEVICE(obj), &s->uart1_rst, "uart1_rst", 1); } =20 static const VMStateDescription vmstate_zynq_slcr =3D { @@ -469,7 +503,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, vo= id *data) =20 resettable_class_set_parent_reset_phases(rc, zynq_slcr_reset_init, - NULL, + zynq_slcr_reset_hold, NULL, &zc->parent_reset_phases); } --=20 2.21.0 From nobody Sun Apr 28 02:22:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559666396990404.73907134790363; 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c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665549; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hPGMgixGP9cMjZnkAysbw7ZF4rrVQ1Cey8fOKWl2H6M=; b=r3PPACRHX3mKBa1LqS1d0U/U+GxHe/y+LkRaCi46Y/JlC8fkKqxull3KLYelEKlbukSVCK zx5SCJ6ipiQCoCfIgHUS94DLXt+Ljp6p5fkorPrdDa26YON6/ftZ5Jhc0ylGcmP5Fl69wH 6u6wWZA1qYQv6gDQlPR9W33ShpLYb9s= From: Damien Hedde To: qemu-devel@nongnu.org Date: Tue, 4 Jun 2019 18:25:26 +0200 Message-Id: <20190604162526.10655-13-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190604162526.10655-1-damien.hedde@greensocs.com> References: <20190604162526.10655-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1559665549; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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charset="utf-8" Connect the two uart reset inputs to the slcr corresponding outputs. Signed-off-by: Damien Hedde --- hw/arm/xilinx_zynq.c | 14 ++++++++------ include/hw/char/cadence_uart.h | 10 +++++++++- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 198e3f9763..ed7549a6a2 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -166,7 +166,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ext_ram =3D g_new(MemoryRegion, 1); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -211,9 +211,9 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); =20 - dev =3D qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + slcr =3D qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); =20 dev =3D qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -234,8 +234,10 @@ static void zynq_init(MachineState *machine) sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); =20 - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0), + slcr, "uart0_rst", 0); + cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1), + slcr, "uart1_rst", 0); =20 sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NU= LL); diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h index 118e3f10de..b7489a711f 100644 --- a/include/hw/char/cadence_uart.h +++ b/include/hw/char/cadence_uart.h @@ -51,7 +51,10 @@ typedef struct { =20 static inline DeviceState *cadence_uart_create(hwaddr addr, qemu_irq irq, - Chardev *chr) + Chardev *chr, + DeviceState *rst_dev, + const char *rst_name, + int rst_n) { DeviceState *dev; SysBusDevice *s; @@ -63,6 +66,11 @@ static inline DeviceState *cadence_uart_create(hwaddr ad= dr, sysbus_mmio_map(s, 0, addr); sysbus_connect_irq(s, 0, irq); =20 + if (rst_dev) { + qdev_connect_gpio_out_named(rst_dev, rst_name, rst_n, + qdev_get_gpio_in_named(dev, "rst", 0)); + } + return dev; } =20 --=20 2.21.0