From nobody Wed Feb 11 02:55:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559475908; cv=none; d=zoho.com; s=zohoarc; b=Bp64MpYYWQiGojF/3hYZud3XYVE0XlWC6o1kXEXn/77tX2NejZewYAJo5Sbosu5Avm3trTeX3RAt28Zrb9vnLg57SF8ZQa29mNwyOfu2yp93uo47Um1S74airNWzyhlnDL27SutJKb/FsoxB1C4ZyhLV3Mc3aYYBhh7ET9/6YUk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559475908; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GOS59HgANJNHsJGj9faaHX7oRML8JujtEwTvjDZULdM=; b=WE/pZns3oL64jM1gtLZTEX5lmD15jrmsHBxbbJ2banXSs2a1hTMwvUQc1exbzGl3MLaRryYd/qSmYON0DpPk47Y/K3O0E/yKClrY1jtPYsztz3ZyGap8ebYxu+qM21A0KGapzumt1LasoB3FDogricw9sT475YWVZjPGAKLztv4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559475908988127.12547889695804; Sun, 2 Jun 2019 04:45:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:47969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOv7-0006DH-Rm for importer@patchew.org; Sun, 02 Jun 2019 07:45:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtG-0004vL-7S for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOlg-00085o-Dn for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:35:18 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51534 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOlg-00085L-2r; Sun, 02 Jun 2019 07:35:16 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLi-0008A4-8x; Sun, 02 Jun 2019 12:08:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:59 +0100 Message-Id: <20190602110903.3431-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 11/15] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based upon rD and rB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 30 ++++++++++++----------------- target/ppc/helper.h | 20 +++++++++---------- target/ppc/translate/vsx-impl.inc.c | 38 +++++++++++++++++++++++++++------= ---- 3 files changed, 50 insertions(+), 38 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 90d3566ec8..ba52ef597e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2808,10 +2808,9 @@ VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW= (2 * i), VsrD(i), 0) * sfprf - set FPRF */ #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ ppc_vsr_t t =3D *xt; \ int i; \ \ @@ -2975,10 +2974,9 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, Vs= rW(i), VsrW(i), 0U) * rnan - resulting NaN */ #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, uint32_t opcode, = \ + ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ ppc_vsr_t t =3D { }; = \ = \ t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); = \ @@ -3052,10 +3050,9 @@ VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, Vsr= W(i), VsrW(i), 0, 0) * tfld - target vsr_t field */ #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ ppc_vsr_t t =3D *xt; \ \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ @@ -3278,10 +3275,9 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opc= ode, ppc_vsr_t *xb) env->crf[BF(opcode)] =3D cc; } =20 -void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) +void helper_xsrqpi(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t ex =3D Rc(opcode); @@ -3336,10 +3332,9 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) do_float_check_status(env, GETPC()); } =20 -void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) +void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t rmc =3D RMC(opcode); @@ -3391,10 +3386,9 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcod= e) do_float_check_status(env, GETPC()); } =20 -void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) +void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; float_status tstat; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 9134da9cbb..2e0646f5eb 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -402,16 +402,16 @@ DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) -DEF_HELPER_2(xscvdpqp, void, env, i32) +DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpspn, i64, env, i64) DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xscvqpsdz, void, env, i32) -DEF_HELPER_2(xscvqpswz, void, env, i32) -DEF_HELPER_2(xscvqpudz, void, env, i32) -DEF_HELPER_2(xscvqpuwz, void, env, i32) +DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr) -DEF_HELPER_2(xscvsdqp, void, env, i32) +DEF_HELPER_4(xscvsdqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvspdp, void, env, vsr, vsr) DEF_HELPER_2(xscvspdpn, i64, env, i64) DEF_HELPER_3(xscvdpsxds, void, env, vsr, vsr) @@ -421,7 +421,7 @@ DEF_HELPER_3(xscvdpuxws, void, env, vsr, vsr) DEF_HELPER_3(xscvsxddp, void, env, vsr, vsr) DEF_HELPER_3(xscvuxdsp, void, env, vsr, vsr) DEF_HELPER_3(xscvsxdsp, void, env, vsr, vsr) -DEF_HELPER_2(xscvudqp, void, env, i32) +DEF_HELPER_4(xscvudqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvuxddp, void, env, vsr, vsr) DEF_HELPER_3(xststdcsp, void, env, i32, vsr) DEF_HELPER_2(xststdcdp, void, env, i32) @@ -431,9 +431,9 @@ DEF_HELPER_3(xsrdpic, void, env, vsr, vsr) DEF_HELPER_3(xsrdpim, void, env, vsr, vsr) DEF_HELPER_3(xsrdpip, void, env, vsr, vsr) DEF_HELPER_3(xsrdpiz, void, env, vsr, vsr) -DEF_HELPER_2(xsrqpi, void, env, i32) -DEF_HELPER_2(xsrqpxp, void, env, i32) -DEF_HELPER_2(xssqrtqp, void, env, i32) +DEF_HELPER_4(xsrqpi, void, env, i32, vsr, vsr) +DEF_HELPER_4(xsrqpxp, void, env, i32, vsr, vsr) +DEF_HELPER_4(xssqrtqp, void, env, i32, vsr, vsr) DEF_HELPER_5(xssubqp, void, env, i32, vsr, vsr, vsr) =20 DEF_HELPER_4(xsaddsp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 1aa6e04e39..0dd78546d7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1114,6 +1114,24 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xt, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ + xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ + gen_helper_##name(cpu_env, opc, xt, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1170,14 +1188,14 @@ GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA= 300) GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) @@ -1185,7 +1203,7 @@ GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) @@ -1194,9 +1212,9 @@ GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) =20 -GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) +GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) =20 GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) --=20 2.11.0