From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474330; cv=none; d=zoho.com; s=zohoarc; b=Cg+9r2d9UyDkyiypH1oHRhR/QYOUmEnHOHR/J1+rsHmoFMTkmca0sMmRQRfblZRlVHhwG3lOkyg3nZTjands9VAcILxOfv7JO9qVCOFlB9jgpRE2KkjC0g0BwIoul09o89d06S5bf9xBDiGqAEhxZiLLfsZRmZRHSqlqHxxW5Po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474330; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1gW3LGK6IkfTsPNuuoofZ5lkNAMwaqbtGxGNrrdV1ic=; b=HiI0761lz414Fp8RPnO2Wmv9fiNSb4cQ3CkUaLYeRq7gz8wiUZKoz/ztG5xBStH1ZavkIESU7qbHjgx9X8Disf+2GEO/lQNazRdO4WGpnI8poMEMX5p89T27ku48YjvIXIBeWdiUNhwRrsDZC3as0xVWsMKymbGwf3TfBtwej5A= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474330111567.5380417105713; Sun, 2 Jun 2019 04:18:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:47739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOVi-0007lW-Ka for importer@patchew.org; Sun, 02 Jun 2019 07:18:46 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPl-0003Qy-1T for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPe-0003Zf-60 for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:37 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51394 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPd-0002kV-J4; Sun, 02 Jun 2019 07:12:30 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLZ-0008A4-9H; Sun, 02 Jun 2019 12:08:18 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:49 +0100 Message-Id: <20190602110903.3431-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 01/15] target/ppc: remove getVSR()/putVSR() from fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order" functions getVSR() and putVSR() which u= sed to convert the VSR registers into host endian order are no longer required. Signed-off-by: Mark Cave-Ayland --- target/ppc/fpu_helper.c | 762 +++++++++++++++++++++++---------------------= ---- 1 file changed, 366 insertions(+), 396 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 0b7308f539..5edf913a89 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -1803,35 +1803,35 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t= op1, uint64_t op2) #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) = \ void helper_##name(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - xt.fld =3D tp##_##op(xa.fld, xb.fld, &tstat); = \ + t.fld =3D tp##_##op(xa->fld, xb->fld, &tstat); = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ float_invalid_op_addsub(env, sfprf, GETPC(), = \ - tp##_classify(xa.fld) | = \ - tp##_classify(xb.fld)); = \ + tp##_classify(xa->fld) | = \ + tp##_classify(xb->fld)); = \ } = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -1846,12 +1846,12 @@ VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0) =20 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xa, xb; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D *xt; float_status tstat; =20 - getVSR(rA(opcode) + 32, &xa, env); - getVSR(rB(opcode) + 32, &xb, env); - getVSR(rD(opcode) + 32, &xt, env); helper_reset_fpstatus(env); =20 tstat =3D env->fp_status; @@ -1860,18 +1860,18 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opco= de) } =20 set_float_exception_flags(0, &tstat); - xt.f128 =3D float128_add(xa.f128, xb.f128, &tstat); + t.f128 =3D float128_add(xa->f128, xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa.f128) | - float128_classify(xb.f128)); + float128_classify(xa->f128) | + float128_classify(xb->f128)); } =20 - helper_compute_fprf_float128(env, xt.f128); + helper_compute_fprf_float128(env, t.f128); =20 - putVSR(rD(opcode) + 32, &xt, env); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 @@ -1886,36 +1886,36 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opco= de) #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - xt.fld =3D tp##_mul(xa.fld, xb.fld, &tstat); = \ + t.fld =3D tp##_mul(xa->fld, xb->fld, &tstat); = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ float_invalid_op_mul(env, sfprf, GETPC(), = \ - tp##_classify(xa.fld) | = \ - tp##_classify(xb.fld)); = \ + tp##_classify(xa->fld) | = \ + tp##_classify(xb->fld)); = \ } = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -1926,13 +1926,12 @@ VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0) =20 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xa, xb; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D *xt; float_status tstat; =20 - getVSR(rA(opcode) + 32, &xa, env); - getVSR(rB(opcode) + 32, &xb, env); - getVSR(rD(opcode) + 32, &xt, env); - helper_reset_fpstatus(env); tstat =3D env->fp_status; if (unlikely(Rc(opcode) !=3D 0)) { @@ -1940,17 +1939,17 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opco= de) } =20 set_float_exception_flags(0, &tstat); - xt.f128 =3D float128_mul(xa.f128, xb.f128, &tstat); + t.f128 =3D float128_mul(xa->f128, xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { float_invalid_op_mul(env, 1, GETPC(), - float128_classify(xa.f128) | - float128_classify(xb.f128)); + float128_classify(xa->f128) | + float128_classify(xb->f128)); } - helper_compute_fprf_float128(env, xt.f128); + helper_compute_fprf_float128(env, t.f128); =20 - putVSR(rD(opcode) + 32, &xt, env); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 @@ -1965,39 +1964,39 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opco= de) #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - xt.fld =3D tp##_div(xa.fld, xb.fld, &tstat); = \ + t.fld =3D tp##_div(xa->fld, xb->fld, &tstat); = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ float_invalid_op_div(env, sfprf, GETPC(), = \ - tp##_classify(xa.fld) | = \ - tp##_classify(xb.fld)); = \ + tp##_classify(xa->fld) | = \ + tp##_classify(xb->fld)); = \ } = \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) = { \ float_zero_divide_excp(env, GETPC()); = \ } = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2008,13 +2007,12 @@ VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0) =20 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xa, xb; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D *xt; float_status tstat; =20 - getVSR(rA(opcode) + 32, &xa, env); - getVSR(rB(opcode) + 32, &xb, env); - getVSR(rD(opcode) + 32, &xt, env); - helper_reset_fpstatus(env); tstat =3D env->fp_status; if (unlikely(Rc(opcode) !=3D 0)) { @@ -2022,20 +2020,20 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opco= de) } =20 set_float_exception_flags(0, &tstat); - xt.f128 =3D float128_div(xa.f128, xb.f128, &tstat); + t.f128 =3D float128_div(xa->f128, xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { float_invalid_op_div(env, 1, GETPC(), - float128_classify(xa.f128) | - float128_classify(xb.f128)); + float128_classify(xa->f128) | + float128_classify(xb->f128)); } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { float_zero_divide_excp(env, GETPC()); } =20 - helper_compute_fprf_float128(env, xt.f128); - putVSR(rD(opcode) + 32, &xt, env); + helper_compute_fprf_float128(env, t.f128); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 @@ -2050,29 +2048,29 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opco= de) #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ - if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { = \ + if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { = \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ - xt.fld =3D tp##_div(tp##_one, xb.fld, &env->fp_status); = \ + t.fld =3D tp##_div(tp##_one, xb->fld, &env->fp_status); = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2092,37 +2090,37 @@ VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0) #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - xt.fld =3D tp##_sqrt(xb.fld, &tstat); = \ + t.fld =3D tp##_sqrt(xb->fld, &tstat); = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { = \ + if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { = \ float_invalid_op_vxsqrt(env, sfprf, GETPC()); = \ - } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { = \ + } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { = \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2142,38 +2140,38 @@ VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0) #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - xt.fld =3D tp##_sqrt(xb.fld, &tstat); = \ - xt.fld =3D tp##_div(tp##_one, xt.fld, &tstat); = \ + t.fld =3D tp##_sqrt(xb->fld, &tstat); = \ + t.fld =3D tp##_div(tp##_one, t.fld, &tstat); = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { = \ + if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { = \ float_invalid_op_vxsqrt(env, sfprf, GETPC()); = \ - } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { = \ + } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { = \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ if (r2sp) { = \ - xt.fld =3D helper_frsp(env, xt.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2195,37 +2193,35 @@ VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0) #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xa, xb; \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ int i; \ int fe_flag =3D 0; \ int fg_flag =3D 0; \ \ - getVSR(xA(opcode), &xa, env); \ - getVSR(xB(opcode), &xb, env); \ - \ for (i =3D 0; i < nels; i++) { \ - if (unlikely(tp##_is_infinity(xa.fld) || \ - tp##_is_infinity(xb.fld) || \ - tp##_is_zero(xb.fld))) { \ + if (unlikely(tp##_is_infinity(xa->fld) || \ + tp##_is_infinity(xb->fld) || \ + tp##_is_zero(xb->fld))) { \ fe_flag =3D 1; \ fg_flag =3D 1; \ } else { \ - int e_a =3D ppc_##tp##_get_unbiased_exp(xa.fld); \ - int e_b =3D ppc_##tp##_get_unbiased_exp(xb.fld); \ + int e_a =3D ppc_##tp##_get_unbiased_exp(xa->fld); \ + int e_b =3D ppc_##tp##_get_unbiased_exp(xb->fld); \ \ - if (unlikely(tp##_is_any_nan(xa.fld) || \ - tp##_is_any_nan(xb.fld))) { \ + if (unlikely(tp##_is_any_nan(xa->fld) || \ + tp##_is_any_nan(xb->fld))) { \ fe_flag =3D 1; \ } else if ((e_b <=3D emin) || (e_b >=3D (emax - 2))) { = \ fe_flag =3D 1; \ - } else if (!tp##_is_zero(xa.fld) && \ + } else if (!tp##_is_zero(xa->fld) && \ (((e_a - e_b) >=3D emax) || \ ((e_a - e_b) <=3D (emin + 1)) || \ (e_a <=3D (emin + nbits)))) { \ fe_flag =3D 1; \ } \ \ - if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \ + if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \ /* \ * XB is not zero because of the above check and so \ * must be denormalized. \ @@ -2255,34 +2251,31 @@ VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, = 23) #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xa, xb; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ int i; \ int fe_flag =3D 0; \ int fg_flag =3D 0; \ \ - getVSR(xA(opcode), &xa, env); \ - getVSR(xB(opcode), &xb, env); \ - \ for (i =3D 0; i < nels; i++) { \ - if (unlikely(tp##_is_infinity(xb.fld) || \ - tp##_is_zero(xb.fld))) { \ + if (unlikely(tp##_is_infinity(xb->fld) || \ + tp##_is_zero(xb->fld))) { \ fe_flag =3D 1; \ fg_flag =3D 1; \ } else { \ - int e_b =3D ppc_##tp##_get_unbiased_exp(xb.fld); \ + int e_b =3D ppc_##tp##_get_unbiased_exp(xb->fld); \ \ - if (unlikely(tp##_is_any_nan(xb.fld))) { \ + if (unlikely(tp##_is_any_nan(xb->fld))) { \ fe_flag =3D 1; \ - } else if (unlikely(tp##_is_zero(xb.fld))) { \ + } else if (unlikely(tp##_is_zero(xb->fld))) { \ fe_flag =3D 1; \ - } else if (unlikely(tp##_is_neg(xb.fld))) { \ + } else if (unlikely(tp##_is_neg(xb->fld))) { \ fe_flag =3D 1; \ - } else if (!tp##_is_zero(xb.fld) && \ + } else if (!tp##_is_zero(xb->fld) && \ (e_b <=3D (emin + nbits))) { \ fe_flag =3D 1; \ } \ \ - if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \ + if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \ /* \ * XB is not zero because of the above check and \ * therefore must be denormalized. \ @@ -2313,24 +2306,20 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt_in, xa, xb, xt_out; = \ - ppc_vsr_t *b, *c; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt, *b, *c; = \ int i; = \ = \ if (afrm) { /* AxB + T */ = \ - b =3D &xb; = \ - c =3D &xt_in; = \ + b =3D xb; = \ + c =3D xt; = \ } else { /* AxT + B */ = \ - b =3D &xt_in; = \ - c =3D &xb; = \ + b =3D xt; = \ + c =3D xb; = \ } = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt_in, env); = \ - = \ - xt_out =3D xt_in; = \ - = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ @@ -2342,30 +2331,30 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ * result to odd. = \ */ = \ set_float_rounding_mode(float_round_to_zero, &tstat); = \ - xt_out.fld =3D tp##_muladd(xa.fld, b->fld, c->fld, = \ - maddflgs, &tstat); = \ - xt_out.fld |=3D (get_float_exception_flags(&tstat) & = \ - float_flag_inexact) !=3D 0; = \ + t.fld =3D tp##_muladd(xa->fld, b->fld, c->fld, = \ + maddflgs, &tstat); = \ + t.fld |=3D (get_float_exception_flags(&tstat) & = \ + float_flag_inexact) !=3D 0; = \ } else { = \ - xt_out.fld =3D tp##_muladd(xa.fld, b->fld, c->fld, = \ - maddflgs, &tstat); = \ + t.fld =3D tp##_muladd(xa->fld, b->fld, c->fld, = \ + maddflgs, &tstat); = \ } = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - tp##_maddsub_update_excp(env, xa.fld, b->fld, = \ + tp##_maddsub_update_excp(env, xa->fld, b->fld, = \ c->fld, maddflgs, GETPC()); = \ } = \ = \ if (r2sp) { = \ - xt_out.fld =3D helper_frsp(env, xt_out.fld); = \ + t.fld =3D helper_frsp(env, t.fld); = \ } = \ = \ if (sfprf) { = \ - helper_compute_fprf_float64(env, xt_out.fld); = \ + helper_compute_fprf_float64(env, t.fld); = \ } = \ } = \ - putVSR(xT(opcode), &xt_out, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2415,22 +2404,21 @@ VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLG= S, 0, 0, 0) #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vxvc_flag =3D false, vex_flag =3D false; = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ - = \ - if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || = \ - float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { = \ + if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || = \ + float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { = \ vxsnan_flag =3D true; = \ if (fpscr_ve =3D=3D 0 && svxvc) { = \ vxvc_flag =3D true; = \ } = \ } else if (svxvc) { = \ - vxvc_flag =3D float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) ||= \ - float64_is_quiet_nan(xb.VsrD(0), &env->fp_status); = \ + vxvc_flag =3D float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) |= | \ + float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); = \ } = \ if (vxsnan_flag) { = \ float_invalid_op_vxsnan(env, GETPC()); = \ @@ -2441,15 +2429,16 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ vex_flag =3D fpscr_ve && (vxvc_flag || vxsnan_flag); = \ = \ if (!vex_flag) { = \ - if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) =3D=3D = exp) { \ - xt.VsrD(0) =3D -1; = \ - xt.VsrD(1) =3D 0; = \ + if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), = \ + &env->fp_status) =3D=3D exp) { = \ + t.VsrD(0) =3D -1; = \ + t.VsrD(1) =3D 0; = \ } else { = \ - xt.VsrD(0) =3D 0; = \ - xt.VsrD(1) =3D 0; = \ + t.VsrD(0) =3D 0; = \ + t.VsrD(1) =3D 0; = \ } = \ } = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2460,18 +2449,16 @@ VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0) =20 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xa, xb; + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; int64_t exp_a, exp_b; uint32_t cc; =20 - getVSR(xA(opcode), &xa, env); - getVSR(xB(opcode), &xb, env); - - exp_a =3D extract64(xa.VsrD(0), 52, 11); - exp_b =3D extract64(xb.VsrD(0), 52, 11); + exp_a =3D extract64(xa->VsrD(0), 52, 11); + exp_b =3D extract64(xb->VsrD(0), 52, 11); =20 - if (unlikely(float64_is_any_nan(xa.VsrD(0)) || - float64_is_any_nan(xb.VsrD(0)))) { + if (unlikely(float64_is_any_nan(xa->VsrD(0)) || + float64_is_any_nan(xb->VsrD(0)))) { cc =3D CRF_SO; } else { if (exp_a < exp_b) { @@ -2492,18 +2479,16 @@ void helper_xscmpexpdp(CPUPPCState *env, uint32_t o= pcode) =20 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xa, xb; + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; int64_t exp_a, exp_b; uint32_t cc; =20 - getVSR(rA(opcode) + 32, &xa, env); - getVSR(rB(opcode) + 32, &xb, env); - - exp_a =3D extract64(xa.VsrD(0), 48, 15); - exp_b =3D extract64(xb.VsrD(0), 48, 15); + exp_a =3D extract64(xa->VsrD(0), 48, 15); + exp_b =3D extract64(xb->VsrD(0), 48, 15); =20 - if (unlikely(float128_is_any_nan(xa.f128) || - float128_is_any_nan(xb.f128))) { + if (unlikely(float128_is_any_nan(xa->f128) || + float128_is_any_nan(xb->f128))) { cc =3D CRF_SO; } else { if (exp_a < exp_b) { @@ -2525,23 +2510,22 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t o= pcode) #define VSX_SCALAR_CMP(op, ordered) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xa, xb; \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ uint32_t cc =3D 0; = \ bool vxsnan_flag =3D false, vxvc_flag =3D false; = \ \ helper_reset_fpstatus(env); \ - getVSR(xA(opcode), &xa, env); \ - getVSR(xB(opcode), &xb, env); \ \ - if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \ - float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \ + if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \ + float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \ vxsnan_flag =3D true; = \ cc =3D CRF_SO; = \ if (fpscr_ve =3D=3D 0 && ordered) { = \ vxvc_flag =3D true; = \ } \ - } else if (float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \ - float64_is_quiet_nan(xb.VsrD(0), &env->fp_status)) { \ + } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \ + float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \ cc =3D CRF_SO; = \ if (ordered) { \ vxvc_flag =3D true; = \ @@ -2554,9 +2538,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \ + if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ cc |=3D CRF_LT; = \ - } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \ + } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ cc |=3D CRF_GT; = \ } else { \ cc |=3D CRF_EQ; = \ @@ -2575,23 +2559,22 @@ VSX_SCALAR_CMP(xscmpudp, 0) #define VSX_SCALAR_CMPQ(op, ordered) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xa, xb; \ + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ uint32_t cc =3D 0; \ bool vxsnan_flag =3D false, vxvc_flag =3D false; = \ \ helper_reset_fpstatus(env); \ - getVSR(rA(opcode) + 32, &xa, env); \ - getVSR(rB(opcode) + 32, &xb, env); \ \ - if (float128_is_signaling_nan(xa.f128, &env->fp_status) || \ - float128_is_signaling_nan(xb.f128, &env->fp_status)) { \ + if (float128_is_signaling_nan(xa->f128, &env->fp_status) || \ + float128_is_signaling_nan(xb->f128, &env->fp_status)) { \ vxsnan_flag =3D true; \ cc =3D CRF_SO; \ if (fpscr_ve =3D=3D 0 && ordered) { = \ vxvc_flag =3D true; \ } \ - } else if (float128_is_quiet_nan(xa.f128, &env->fp_status) || \ - float128_is_quiet_nan(xb.f128, &env->fp_status)) { \ + } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) || \ + float128_is_quiet_nan(xb->f128, &env->fp_status)) { \ cc =3D CRF_SO; \ if (ordered) { \ vxvc_flag =3D true; \ @@ -2604,9 +2587,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \ + if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \ cc |=3D CRF_LT; \ - } else if (!float128_le(xa.f128, xb.f128, &env->fp_status)) { \ + } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \ cc |=3D CRF_GT; \ } else { \ cc |=3D CRF_EQ; \ @@ -2633,22 +2616,21 @@ VSX_SCALAR_CMPQ(xscmpuqp, 0) #define VSX_MAX_MIN(name, op, nels, tp, fld) = \ void helper_##name(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xA(opcode), &xa, env); = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ - = \ for (i =3D 0; i < nels; i++) { = \ - xt.fld =3D tp##_##op(xa.fld, xb.fld, &env->fp_status); = \ - if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || = \ - tp##_is_signaling_nan(xb.fld, &env->fp_status))) { = \ + t.fld =3D tp##_##op(xa->fld, xb->fld, &env->fp_status); = \ + if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || = \ + tp##_is_signaling_nan(xb->fld, &env->fp_status))) { = \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -2662,27 +2644,26 @@ VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) #define VSX_MAX_MINC(name, max) = \ void helper_##name(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; = \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ + ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vex_flag =3D false; = \ = \ - getVSR(rA(opcode) + 32, &xa, env); = \ - getVSR(rB(opcode) + 32, &xb, env); = \ - getVSR(rD(opcode) + 32, &xt, env); = \ - = \ - if (unlikely(float64_is_any_nan(xa.VsrD(0)) || = \ - float64_is_any_nan(xb.VsrD(0)))) { = \ - if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || = \ - float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { = \ + if (unlikely(float64_is_any_nan(xa->VsrD(0)) || = \ + float64_is_any_nan(xb->VsrD(0)))) { = \ + if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || = \ + float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { = \ vxsnan_flag =3D true; = \ } = \ - xt.VsrD(0) =3D xb.VsrD(0); = \ + t.VsrD(0) =3D xb->VsrD(0); = \ } else if ((max && = \ - !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || = \ + !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || = \ (!max && = \ - float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { = \ - xt.VsrD(0) =3D xa.VsrD(0); = \ + float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { = \ + t.VsrD(0) =3D xa->VsrD(0); = \ } else { = \ - xt.VsrD(0) =3D xb.VsrD(0); = \ + t.VsrD(0) =3D xb->VsrD(0); = \ } = \ = \ vex_flag =3D fpscr_ve & vxsnan_flag; = \ @@ -2690,7 +2671,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ if (!vex_flag) { = \ - putVSR(rD(opcode) + 32, &xt, env); = \ + *xt =3D t; = \ } = \ } = \ =20 @@ -2700,44 +2681,46 @@ VSX_MAX_MINC(xsmincdp, 0); #define VSX_MAX_MINJ(name, max) = \ void helper_##name(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xa, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; = \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ + ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vex_flag =3D false; = \ = \ - getVSR(rA(opcode) + 32, &xa, env); = \ - getVSR(rB(opcode) + 32, &xb, env); = \ - getVSR(rD(opcode) + 32, &xt, env); = \ - = \ - if (unlikely(float64_is_any_nan(xa.VsrD(0)))) { = \ - if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status)) { = \ + if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { = \ + if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { = \ vxsnan_flag =3D true; = \ } = \ - xt.VsrD(0) =3D xa.VsrD(0); = \ - } else if (unlikely(float64_is_any_nan(xb.VsrD(0)))) { = \ - if (float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { = \ + t.VsrD(0) =3D xa->VsrD(0); = \ + } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { = \ + if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { = \ vxsnan_flag =3D true; = \ } = \ - xt.VsrD(0) =3D xb.VsrD(0); = \ - } else if (float64_is_zero(xa.VsrD(0)) && float64_is_zero(xb.VsrD(0)))= { \ + t.VsrD(0) =3D xb->VsrD(0); = \ + } else if (float64_is_zero(xa->VsrD(0)) && = \ + float64_is_zero(xb->VsrD(0))) { = \ if (max) { = \ - if (!float64_is_neg(xa.VsrD(0)) || !float64_is_neg(xb.VsrD(0))= ) { \ - xt.VsrD(0) =3D 0ULL; = \ + if (!float64_is_neg(xa->VsrD(0)) || = \ + !float64_is_neg(xb->VsrD(0))) { = \ + t.VsrD(0) =3D 0ULL; = \ } else { = \ - xt.VsrD(0) =3D 0x8000000000000000ULL; = \ + t.VsrD(0) =3D 0x8000000000000000ULL; = \ } = \ } else { = \ - if (float64_is_neg(xa.VsrD(0)) || float64_is_neg(xb.VsrD(0))) = { \ - xt.VsrD(0) =3D 0x8000000000000000ULL; = \ + if (float64_is_neg(xa->VsrD(0)) || = \ + float64_is_neg(xb->VsrD(0))) { = \ + t.VsrD(0) =3D 0x8000000000000000ULL; = \ } else { = \ - xt.VsrD(0) =3D 0ULL; = \ + t.VsrD(0) =3D 0ULL; = \ } = \ } = \ } else if ((max && = \ - !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || = \ + !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || = \ (!max && = \ - float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { = \ - xt.VsrD(0) =3D xa.VsrD(0); = \ + float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { = \ + t.VsrD(0) =3D xa->VsrD(0); = \ } else { = \ - xt.VsrD(0) =3D xb.VsrD(0); = \ + t.VsrD(0) =3D xb->VsrD(0); = \ } = \ = \ vex_flag =3D fpscr_ve & vxsnan_flag; = \ @@ -2745,7 +2728,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ float_invalid_op_vxsnan(env, GETPC()); = \ } = \ if (!vex_flag) { = \ - putVSR(rD(opcode) + 32, &xt, env); = \ + *xt =3D t; = \ } = \ } = \ =20 @@ -2765,39 +2748,38 @@ VSX_MAX_MINJ(xsminjdp, 0); #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xa, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; \ int all_true =3D 1; = \ int all_false =3D 1; = \ \ - getVSR(xA(opcode), &xa, env); \ - getVSR(xB(opcode), &xb, env); \ - getVSR(xT(opcode), &xt, env); \ - \ for (i =3D 0; i < nels; i++) { = \ - if (unlikely(tp##_is_any_nan(xa.fld) || \ - tp##_is_any_nan(xb.fld))) { \ - if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \ - tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \ + if (unlikely(tp##_is_any_nan(xa->fld) || \ + tp##_is_any_nan(xb->fld))) { \ + if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \ + tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \ float_invalid_op_vxsnan(env, GETPC()); \ } \ if (svxvc) { \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ - xt.fld =3D 0; = \ + t.fld =3D 0; = \ all_true =3D 0; = \ } else { \ - if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) =3D=3D exp) { = \ - xt.fld =3D -1; = \ + if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) =3D=3D exp) = { \ + t.fld =3D -1; = \ all_false =3D 0; = \ } else { \ - xt.fld =3D 0; = \ + t.fld =3D 0; = \ all_true =3D 0; = \ } \ } \ } \ \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; = \ if ((opcode >> (31 - 21)) & 1) { \ env->crf[6] =3D (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); = \ } \ @@ -2826,25 +2808,24 @@ VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0) #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ + ppc_vsr_t t =3D *xt; \ int i; \ \ - getVSR(xB(opcode), &xb, env); \ - getVSR(xT(opcode), &xt, env); \ - \ for (i =3D 0; i < nels; i++) { \ - xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ - if (unlikely(stp##_is_signaling_nan(xb.sfld, \ + t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ + if (unlikely(stp##_is_signaling_nan(xb->sfld, \ &env->fp_status))) { \ float_invalid_op_vxsnan(env, GETPC()); \ - xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ + t.tfld =3D ttp##_snan_to_qnan(t.tfld); \ } \ if (sfprf) { \ - helper_compute_fprf_##ttp(env, xt.tfld); \ + helper_compute_fprf_##ttp(env, t.tfld); \ } \ } \ \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -2866,25 +2847,24 @@ VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, Vsr= W(2 * i), VsrD(i), 0) #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ + ppc_vsr_t t =3D *xt; \ int i; \ \ - getVSR(rB(opcode) + 32, &xb, env); \ - getVSR(rD(opcode) + 32, &xt, env); \ - \ for (i =3D 0; i < nels; i++) { \ - xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ - if (unlikely(stp##_is_signaling_nan(xb.sfld, \ + t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ + if (unlikely(stp##_is_signaling_nan(xb->sfld, \ &env->fp_status))) { \ float_invalid_op_vxsnan(env, GETPC()); \ - xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ + t.tfld =3D ttp##_snan_to_qnan(t.tfld); \ } \ if (sfprf) { \ - helper_compute_fprf_##ttp(env, xt.tfld); \ + helper_compute_fprf_##ttp(env, t.tfld); \ } \ } \ \ - putVSR(rD(opcode) + 32, &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -2904,25 +2884,24 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float= 128, VsrD(0), f128, 1) #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ + ppc_vsr_t t =3D { }; \ int i; \ \ - getVSR(xB(opcode), &xb, env); \ - memset(&xt, 0, sizeof(xt)); \ - \ for (i =3D 0; i < nels; i++) { \ - xt.tfld =3D stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \ - if (unlikely(stp##_is_signaling_nan(xb.sfld, \ + t.tfld =3D stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \ + if (unlikely(stp##_is_signaling_nan(xb->sfld, \ &env->fp_status))) { \ float_invalid_op_vxsnan(env, GETPC()); \ - xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ + t.tfld =3D ttp##_snan_to_qnan(t.tfld); \ } \ if (sfprf) { \ - helper_compute_fprf_##ttp(env, xt.tfld); \ + helper_compute_fprf_##ttp(env, t.tfld); \ } \ } \ \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -2937,26 +2916,25 @@ VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, = VsrH(2 * i + 1), VsrW(i), 0) */ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xb; + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; + ppc_vsr_t t =3D { }; float_status tstat; =20 - getVSR(rB(opcode) + 32, &xb, env); - memset(&xt, 0, sizeof(xt)); - tstat =3D env->fp_status; if (unlikely(Rc(opcode) !=3D 0)) { tstat.float_rounding_mode =3D float_round_to_odd; } =20 - xt.VsrD(0) =3D float128_to_float64(xb.f128, &tstat); + t.VsrD(0) =3D float128_to_float64(xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; - if (unlikely(float128_is_signaling_nan(xb.f128, &tstat))) { + if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) { float_invalid_op_vxsnan(env, GETPC()); - xt.VsrD(0) =3D float64_snan_to_qnan(xt.VsrD(0)); + t.VsrD(0) =3D float64_snan_to_qnan(t.VsrD(0)); } - helper_compute_fprf_float64(env, xt.VsrD(0)); + helper_compute_fprf_float64(env, t.VsrD(0)); =20 - putVSR(rD(opcode) + 32, &xt, env); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 @@ -2990,24 +2968,23 @@ uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_= t xb) void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ int all_flags =3D env->fp_status.float_exception_flags, flags; = \ - ppc_vsr_t xt, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - getVSR(xB(opcode), &xb, env); = \ - getVSR(xT(opcode), &xt, env); = \ - = \ for (i =3D 0; i < nels; i++) { = \ env->fp_status.float_exception_flags =3D 0; = \ - xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_statu= s); \ + t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_statu= s); \ flags =3D env->fp_status.float_exception_flags; = \ if (unlikely(flags & float_flag_invalid)) { = \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); = \ - xt.tfld =3D rnan; = \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); = \ + t.tfld =3D rnan; = \ } = \ all_flags |=3D flags; = \ } = \ = \ - putVSR(xT(opcode), &xt, env); = \ + *xt =3D t; = \ env->fp_status.float_exception_flags =3D all_flags; = \ do_float_check_status(env, GETPC()); = \ } @@ -3042,18 +3019,17 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, V= srW(i), VsrW(i), 0U) #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ - ppc_vsr_t xt, xb; = \ + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ + ppc_vsr_t t =3D { }; = \ = \ - getVSR(rB(opcode) + 32, &xb, env); = \ - memset(&xt, 0, sizeof(xt)); = \ - = \ - xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); = \ + t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); = \ if (env->fp_status.float_exception_flags & float_flag_invalid) { = \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); = \ - xt.tfld =3D rnan; = \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); = \ + t.tfld =3D rnan; = \ } = \ = \ - putVSR(rD(opcode) + 32, &xt, env); = \ + *xt =3D t; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -3079,23 +3055,22 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint3= 2, f128, VsrD(0), 0x0ULL) #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ + ppc_vsr_t t =3D *xt; \ int i; \ \ - getVSR(xB(opcode), &xb, env); \ - getVSR(xT(opcode), &xt, env); \ - \ for (i =3D 0; i < nels; i++) { \ - xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ + t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ if (r2sp) { \ - xt.tfld =3D helper_frsp(env, xt.tfld); \ + t.tfld =3D helper_frsp(env, t.tfld); \ } \ if (sfprf) { \ - helper_compute_fprf_float64(env, xt.tfld); \ + helper_compute_fprf_float64(env, t.tfld); \ } \ } \ \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -3123,15 +3098,14 @@ VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, Vs= rW(i), VsrW(i), 0, 0) #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ - \ - getVSR(rB(opcode) + 32, &xb, env); \ - getVSR(rD(opcode) + 32, &xt, env); \ + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ + ppc_vsr_t t =3D *xt; \ \ - xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ - helper_compute_fprf_##ttp(env, xt.tfld); \ + t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ + helper_compute_fprf_##ttp(env, t.tfld); \ \ - putVSR(xT(opcode) + 32, &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -3157,25 +3131,25 @@ VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128= , VsrD(0), f128) #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ + ppc_vsr_t t =3D *xt; \ int i; \ - getVSR(xB(opcode), &xb, env); \ - getVSR(xT(opcode), &xt, env); \ \ if (rmode !=3D FLOAT_ROUND_CURRENT) { \ set_float_rounding_mode(rmode, &env->fp_status); \ } \ \ for (i =3D 0; i < nels; i++) { \ - if (unlikely(tp##_is_signaling_nan(xb.fld, \ + if (unlikely(tp##_is_signaling_nan(xb->fld, \ &env->fp_status))) { \ float_invalid_op_vxsnan(env, GETPC()); \ - xt.fld =3D tp##_snan_to_qnan(xb.fld); \ + t.fld =3D tp##_snan_to_qnan(xb->fld); \ } else { \ - xt.fld =3D tp##_round_to_int(xb.fld, &env->fp_status); \ + t.fld =3D tp##_round_to_int(xb->fld, &env->fp_status); \ } \ if (sfprf) { \ - helper_compute_fprf_float64(env, xt.fld); \ + helper_compute_fprf_float64(env, t.fld); \ } \ } \ \ @@ -3189,7 +3163,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fp_status.float_exception_flags &=3D ~float_flag_inexact; \ } \ \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; \ do_float_check_status(env, GETPC()); \ } =20 @@ -3225,21 +3199,21 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) #define VSX_XXPERM(op, indexed) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xa, pcv, xto; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; \ + ppc_vsr_t *pcv =3D &env->vsr[xB(opcode)]; \ + ppc_vsr_t t =3D *xt; \ int i, idx; \ \ - getVSR(xA(opcode), &xa, env); \ - getVSR(xT(opcode), &xt, env); \ - getVSR(xB(opcode), &pcv, env); \ - \ for (i =3D 0; i < 16; i++) { \ - idx =3D pcv.VsrB(i) & 0x1F; \ + idx =3D pcv->VsrB(i) & 0x1F; \ if (indexed) { \ idx =3D 31 - idx; \ } \ - xto.VsrB(i) =3D (idx <=3D 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \ + t.VsrB(i) =3D (idx <=3D 15) ? xa->VsrB(idx) \ + : xt->VsrB(idx - 16); \ } \ - putVSR(xT(opcode), &xto, env); \ + *xt =3D t; \ } =20 VSX_XXPERM(xxperm, 0) @@ -3247,22 +3221,21 @@ VSX_XXPERM(xxpermr, 1) =20 void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xb; + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; + ppc_vsr_t t =3D *xt; uint32_t exp, i, fraction; =20 - getVSR(xB(opcode), &xb, env); - memset(&xt, 0, sizeof(xt)); - for (i =3D 0; i < 4; i++) { - exp =3D (xb.VsrW(i) >> 23) & 0xFF; - fraction =3D xb.VsrW(i) & 0x7FFFFF; + exp =3D (xb->VsrW(i) >> 23) & 0xFF; + fraction =3D xb->VsrW(i) & 0x7FFFFF; if (exp !=3D 0 && exp !=3D 255) { - xt.VsrW(i) =3D fraction | 0x00800000; + t.VsrW(i) =3D fraction | 0x00800000; } else { - xt.VsrW(i) =3D fraction; + t.VsrW(i) =3D fraction; } } - putVSR(xT(opcode), &xt, env); + *xt =3D t; } =20 /* @@ -3279,27 +3252,28 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opc= ode) #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ - ppc_vsr_t xt, xb; \ + ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ + ppc_vsr_t *xb =3D &env->vsr[xbn]; \ + ppc_vsr_t t =3D { }; \ uint32_t i, sign, dcmx; \ uint32_t cc, match =3D 0; \ \ - getVSR(xbn, &xb, env); \ if (!scrf) { \ - memset(&xt, 0, sizeof(xt)); \ dcmx =3D DCMX_XV(opcode); \ } else { \ + t =3D *xt; \ dcmx =3D DCMX(opcode); \ } \ \ for (i =3D 0; i < nels; i++) { \ - sign =3D tp##_is_neg(xb.fld); \ - if (tp##_is_any_nan(xb.fld)) { \ + sign =3D tp##_is_neg(xb->fld); \ + if (tp##_is_any_nan(xb->fld)) { \ match =3D extract32(dcmx, 6, 1); \ - } else if (tp##_is_infinity(xb.fld)) { \ + } else if (tp##_is_infinity(xb->fld)) { \ match =3D extract32(dcmx, 4 + !sign, 1); \ - } else if (tp##_is_zero(xb.fld)) { \ + } else if (tp##_is_zero(xb->fld)) { \ match =3D extract32(dcmx, 2 + !sign, 1); \ - } else if (tp##_is_zero_or_denormal(xb.fld)) { \ + } else if (tp##_is_zero_or_denormal(xb->fld)) { \ match =3D extract32(dcmx, 0 + !sign, 1); \ } \ \ @@ -3309,12 +3283,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ env->fpscr |=3D cc << FPSCR_FPRF; \ env->crf[BF(opcode)] =3D cc; \ } else { \ - xt.tfld =3D match ? fld_max : 0; \ + t.tfld =3D match ? fld_max : 0; \ } \ match =3D 0; \ } \ if (!scrf) { \ - putVSR(xT(opcode), &xt, env); \ + *xt =3D t; \ } \ } =20 @@ -3325,29 +3299,28 @@ VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float1= 28, f128, VsrD(0), 0, 1) =20 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xb; + ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; uint32_t dcmx, sign, exp; uint32_t cc, match =3D 0, not_sp =3D 0; =20 - getVSR(xB(opcode), &xb, env); dcmx =3D DCMX(opcode); - exp =3D (xb.VsrD(0) >> 52) & 0x7FF; + exp =3D (xb->VsrD(0) >> 52) & 0x7FF; =20 - sign =3D float64_is_neg(xb.VsrD(0)); - if (float64_is_any_nan(xb.VsrD(0))) { + sign =3D float64_is_neg(xb->VsrD(0)); + if (float64_is_any_nan(xb->VsrD(0))) { match =3D extract32(dcmx, 6, 1); - } else if (float64_is_infinity(xb.VsrD(0))) { + } else if (float64_is_infinity(xb->VsrD(0))) { match =3D extract32(dcmx, 4 + !sign, 1); - } else if (float64_is_zero(xb.VsrD(0))) { + } else if (float64_is_zero(xb->VsrD(0))) { match =3D extract32(dcmx, 2 + !sign, 1); - } else if (float64_is_zero_or_denormal(xb.VsrD(0)) || + } else if (float64_is_zero_or_denormal(xb->VsrD(0)) || (exp > 0 && exp < 0x381)) { match =3D extract32(dcmx, 0 + !sign, 1); } =20 - not_sp =3D !float64_eq(xb.VsrD(0), + not_sp =3D !float64_eq(xb->VsrD(0), float32_to_float64( - float64_to_float32(xb.VsrD(0), &env->fp_statu= s), + float64_to_float32(xb->VsrD(0), &env->fp_stat= us), &env->fp_status), &env->fp_status); =20 cc =3D sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT; @@ -3358,16 +3331,15 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t op= code) =20 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xb; - ppc_vsr_t xt; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t ex =3D Rc(opcode); uint8_t rmc =3D RMC(opcode); uint8_t rmode =3D 0; float_status tstat; =20 - getVSR(rB(opcode) + 32, &xb, env); - memset(&xt, 0, sizeof(xt)); helper_reset_fpstatus(env); =20 if (r =3D=3D 0 && rmc =3D=3D 0) { @@ -3396,13 +3368,13 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcod= e) tstat =3D env->fp_status; set_float_exception_flags(0, &tstat); set_float_rounding_mode(rmode, &tstat); - xt.f128 =3D float128_round_to_int(xb.f128, &tstat); + t.f128 =3D float128_round_to_int(xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb.f128, &tstat)) { + if (float128_is_signaling_nan(xb->f128, &tstat)) { float_invalid_op_vxsnan(env, GETPC()); - xt.f128 =3D float128_snan_to_qnan(xt.f128); + t.f128 =3D float128_snan_to_qnan(t.f128); } } =20 @@ -3410,23 +3382,22 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcod= e) env->fp_status.float_exception_flags &=3D ~float_flag_inexact; } =20 - helper_compute_fprf_float128(env, xt.f128); + helper_compute_fprf_float128(env, t.f128); + *xt =3D t; do_float_check_status(env, GETPC()); - putVSR(rD(opcode) + 32, &xt, env); } =20 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xb; - ppc_vsr_t xt; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t rmc =3D RMC(opcode); uint8_t rmode =3D 0; floatx80 round_res; float_status tstat; =20 - getVSR(rB(opcode) + 32, &xb, env); - memset(&xt, 0, sizeof(xt)); helper_reset_fpstatus(env); =20 if (r =3D=3D 0 && rmc =3D=3D 0) { @@ -3455,30 +3426,29 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opco= de) tstat =3D env->fp_status; set_float_exception_flags(0, &tstat); set_float_rounding_mode(rmode, &tstat); - round_res =3D float128_to_floatx80(xb.f128, &tstat); - xt.f128 =3D floatx80_to_float128(round_res, &tstat); + round_res =3D float128_to_floatx80(xb->f128, &tstat); + t.f128 =3D floatx80_to_float128(round_res, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb.f128, &tstat)) { + if (float128_is_signaling_nan(xb->f128, &tstat)) { float_invalid_op_vxsnan(env, GETPC()); - xt.f128 =3D float128_snan_to_qnan(xt.f128); + t.f128 =3D float128_snan_to_qnan(t.f128); } } =20 - helper_compute_fprf_float128(env, xt.f128); - putVSR(rD(opcode) + 32, &xt, env); + helper_compute_fprf_float128(env, t.f128); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xb; - ppc_vsr_t xt; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D { }; float_status tstat; =20 - getVSR(rB(opcode) + 32, &xb, env); - memset(&xt, 0, sizeof(xt)); helper_reset_fpstatus(env); =20 tstat =3D env->fp_status; @@ -3487,34 +3457,34 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opc= ode) } =20 set_float_exception_flags(0, &tstat); - xt.f128 =3D float128_sqrt(xb.f128, &tstat); + t.f128 =3D float128_sqrt(xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb.f128, &tstat)) { + if (float128_is_signaling_nan(xb->f128, &tstat)) { float_invalid_op_vxsnan(env, GETPC()); - xt.f128 =3D float128_snan_to_qnan(xb.f128); - } else if (float128_is_quiet_nan(xb.f128, &tstat)) { - xt.f128 =3D xb.f128; - } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128))= { + t.f128 =3D float128_snan_to_qnan(xb->f128); + } else if (float128_is_quiet_nan(xb->f128, &tstat)) { + t.f128 =3D xb->f128; + } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128= )) { float_invalid_op_vxsqrt(env, 1, GETPC()); - xt.f128 =3D float128_default_nan(&env->fp_status); + t.f128 =3D float128_default_nan(&env->fp_status); } } =20 - helper_compute_fprf_float128(env, xt.f128); - putVSR(rD(opcode) + 32, &xt, env); + helper_compute_fprf_float128(env, t.f128); + *xt =3D t; do_float_check_status(env, GETPC()); } =20 void helper_xssubqp(CPUPPCState *env, uint32_t opcode) { - ppc_vsr_t xt, xa, xb; + ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; + ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; + ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; + ppc_vsr_t t =3D *xt; float_status tstat; =20 - getVSR(rA(opcode) + 32, &xa, env); - getVSR(rB(opcode) + 32, &xb, env); - getVSR(rD(opcode) + 32, &xt, env); helper_reset_fpstatus(env); =20 tstat =3D env->fp_status; @@ -3523,16 +3493,16 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opco= de) } =20 set_float_exception_flags(0, &tstat); - xt.f128 =3D float128_sub(xa.f128, xb.f128, &tstat); + t.f128 =3D float128_sub(xa->f128, xb->f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa.f128) | - float128_classify(xb.f128)); + float128_classify(xa->f128) | + float128_classify(xb->f128)); } =20 - helper_compute_fprf_float128(env, xt.f128); - putVSR(rD(opcode) + 32, &xt, env); + helper_compute_fprf_float128(env, t.f128); + *xt =3D t; do_float_check_status(env, GETPC()); } --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474086; cv=none; d=zoho.com; s=zohoarc; b=GT6Vva4yBZVj1r0Ww/t2KI3lYIRFQHrz3jxzuHQDVJZYBWj+g1EfpB7NXJZY7BS/Ixfag9rl03B5KbW29oUZkhNMK0ZUbMgvbNa0QGTnHqIwEk0O8pM8g6k4mBrUY5QzPPy+ZYl8LbYImsgYiZNMzj78+wKic8nD9t46Aygxuf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474086; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BoD3dMI2k2Q0BiohK5P96LJFCEs9QM5yND88g0BySQY=; b=LkB9bzofiUfRDGEljfRPmStcckb3FT1HBZmOX+TW/i8oaLnrXb4eUghewxP3yQFmUsbphiJkh9CpF8PjKlL5P6oEUoMDRdSlg1xm2QFffyAnCj/jn1p/DBvj4JKw9A8A+BOPNIkFJ0Wzx9w7ZLLIIquFRDxq4UfF3wRgFcQHUeU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155947408667981.22614633102023; Sun, 2 Jun 2019 04:14:46 -0700 (PDT) Received: from localhost ([127.0.0.1]:47675 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXORb-0004UM-Is for importer@patchew.org; Sun, 02 Jun 2019 07:14:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34060) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPc-0003LN-VE for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPb-0003X4-SA for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:28 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51382 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPb-0002iF-M9; Sun, 02 Jun 2019 07:12:27 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLb-0008A4-2A; Sun, 02 Jun 2019 12:08:20 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:50 +0100 Message-Id: <20190602110903.3431-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 02/15] target/ppc: remove getVSR()/putVSR() from mem_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order" functions getVSR() and putVSR() which u= sed to convert the VSR registers into host endian order are no longer required. Signed-off-by: Mark Cave-Ayland --- target/ppc/mem_helper.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 5b0f9ee50d..17a3c931a9 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -417,26 +417,27 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32) void helper_##name(CPUPPCState *env, target_ulong addr, \ target_ulong xt_num, target_ulong rb) \ { \ - int i; \ - ppc_vsr_t xt; \ + ppc_vsr_t *xt =3D &env->vsr[xt_num]; \ + ppc_vsr_t t; \ uint64_t nb =3D GET_NB(rb); \ + int i; \ \ - xt.s128 =3D int128_zero(); \ + t.s128 =3D int128_zero(); \ if (nb) { \ nb =3D (nb >=3D 16) ? 16 : nb; = \ if (msr_le && !lj) { \ for (i =3D 16; i > 16 - nb; i--) { \ - xt.VsrB(i - 1) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ + t.VsrB(i - 1) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } else { \ for (i =3D 0; i < nb; i++) { \ - xt.VsrB(i) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ + t.VsrB(i) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } \ } \ - putVSR(xt_num, &xt, env); \ + *xt =3D t; \ } =20 VSX_LXVL(lxvl, 0) @@ -447,26 +448,28 @@ VSX_LXVL(lxvll, 1) void helper_##name(CPUPPCState *env, target_ulong addr, \ target_ulong xt_num, target_ulong rb) \ { \ - int i; \ - ppc_vsr_t xt; \ + ppc_vsr_t *xt =3D &env->vsr[xt_num]; \ + ppc_vsr_t t =3D *xt; \ target_ulong nb =3D GET_NB(rb); \ + int i; \ \ if (!nb) { \ return; \ } \ - getVSR(xt_num, &xt, env); \ + \ nb =3D (nb >=3D 16) ? 16 : nb; \ if (msr_le && !lj) { \ for (i =3D 16; i > 16 - nb; i--) { \ - cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \ + cpu_stb_data_ra(env, addr, t.VsrB(i - 1), GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } else { \ for (i =3D 0; i < nb; i++) { \ - cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \ + cpu_stb_data_ra(env, addr, t.VsrB(i), GETPC()) ; \ addr =3D addr_add(env, addr, 1); \ } \ } \ + *xt =3D t; \ } =20 VSX_STXVL(stxvl, 0) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474542; cv=none; d=zoho.com; s=zohoarc; b=Xk/CZCSjba4WOLUjpO7Wju6UHLUGC64f5n4RAfBeb665u+0k15X2BiiJ9vJR767fF1C4Cjy/EAScab6GqQAW1HSXgJm5p3CsbsDIQ61HWnrVwQPMcN8nZv7zpmVOTFzdlhAx7OzOh5VpF5SlV13Xv2xkrbPY0NONFfbN5UOybO4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474542; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=z5uz5MK4FPp2WSiOhjH0XPnM6py5nxOhW0L/trt/m7Q=; b=NgUSNTTUgsP/GFMCfopUNrrS0OXNqtegyejFvU0p6RNz/LacwyMWQKom0eMZyNuiuOFgK0nlJ3SkwKXAJ2ajb8RzQzjpo1vJkjGkM/Gi8ny9/26blUrhQ01i0imd+nqkPMgFoSBbMG3qLchK6LG5FMms20EElZolsdnemAniLwk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474542562418.0922648642006; Sun, 2 Jun 2019 04:22:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:47803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOZ2-00025M-Fj for importer@patchew.org; Sun, 02 Jun 2019 07:22:12 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPf-0003Ld-Gz for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPe-0003ZS-2K for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:31 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51406 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPd-0002kX-RA; Sun, 02 Jun 2019 07:12:29 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLd-0008A4-0L; Sun, 02 Jun 2019 12:08:21 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:51 +0100 Message-Id: <20190602110903.3431-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 03/15] target/ppc: remove getVSR()/putVSR() from int_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order" functions getVSR() and putVSR() which u= sed to convert the VSR registers into host endian order are no longer required. Now that there are now no more users of getVSR()/putVSR() these functions c= an be completely removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/int_helper.c | 22 ++++++++++------------ target/ppc/internal.h | 12 ------------ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8ce89f2ad9..3b8939edcc 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1902,38 +1902,36 @@ VEXTRACT(d, u64) void helper_xxextractuw(CPUPPCState *env, target_ulong xtn, target_ulong xbn, uint32_t index) { - ppc_vsr_t xt, xb; + ppc_vsr_t *xt =3D &env->vsr[xtn]; + ppc_vsr_t *xb =3D &env->vsr[xbn]; + ppc_vsr_t t =3D { }; size_t es =3D sizeof(uint32_t); uint32_t ext_index; int i; =20 - getVSR(xbn, &xb, env); - memset(&xt, 0, sizeof(xt)); - ext_index =3D index; for (i =3D 0; i < es; i++, ext_index++) { - xt.VsrB(8 - es + i) =3D xb.VsrB(ext_index % 16); + t.VsrB(8 - es + i) =3D xb->VsrB(ext_index % 16); } =20 - putVSR(xtn, &xt, env); + *xt =3D t; } =20 void helper_xxinsertw(CPUPPCState *env, target_ulong xtn, target_ulong xbn, uint32_t index) { - ppc_vsr_t xt, xb; + ppc_vsr_t *xt =3D &env->vsr[xtn]; + ppc_vsr_t *xb =3D &env->vsr[xbn]; + ppc_vsr_t t =3D *xt; size_t es =3D sizeof(uint32_t); int ins_index, i =3D 0; =20 - getVSR(xbn, &xb, env); - getVSR(xtn, &xt, env); - ins_index =3D index; for (i =3D 0; i < es && ins_index < 16; i++, ins_index++) { - xt.VsrB(ins_index) =3D xb.VsrB(8 - es + i); + t.VsrB(ins_index) =3D xb->VsrB(8 - es + i); } =20 - putVSR(xtn, &xt, env); + *xt =3D t; } =20 #define VEXT_SIGNED(name, element, cast) \ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index fb6f64ed1e..d3d327e548 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -204,18 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8); EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); =20 -static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) -{ - vsr->VsrD(0) =3D env->vsr[n].VsrD(0); - vsr->VsrD(1) =3D env->vsr[n].VsrD(1); -} - -static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) -{ - env->vsr[n].VsrD(0) =3D vsr->VsrD(0); - env->vsr[n].VsrD(1) =3D vsr->VsrD(1); -} - void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474257; cv=none; d=zoho.com; s=zohoarc; b=aGi3U5a0INqNuXdAAjwjGIl6WK8yX3n9HB87vQFDStjQuVO82KuzVY5bFEbybWlfpeXjYK/T/5fi1NMz4seuzzYTFRN/OeGJ4ZQKrM1mewbVzJTvSCpVBAIKVKFg6P0FDtdBzgs3WO2B9sZesSEQ3nzp/JgeNeWHKBH8TrWJps0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474257; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=14RLDSeAR17UqPp5f/gDUTAdYREfYC09D+HY+8mF3Dk=; b=fY3bik8AuZcgu60EfSS/GcsPfD/MEP8PFAkilM6VPa5uc29A6BFnqHOuxQ3Ih0ObMGRfZK27ga3FqsawlAVZvH0SlZDorwty7joQ3R+2RibgzIaJQqNwIezfeXatNCxO0GXkYVvG8+f5Q4dEV4pgMK9DJJkcJE4Of5vBhB3PAoM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474257775889.574389209262; Sun, 2 Jun 2019 04:17:37 -0700 (PDT) Received: from localhost ([127.0.0.1]:47735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOUU-0006zJ-MO for importer@patchew.org; Sun, 02 Jun 2019 07:17:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPd-0003LO-HN for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPb-0003X9-SW for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:29 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51378 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPb-0002iH-M8; Sun, 02 Jun 2019 07:12:27 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLd-0008A4-FD; Sun, 02 Jun 2019 12:08:21 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:52 +0100 Message-Id: <20190602110903.3431-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 04/15] target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new VSX_CMP macro which performs the decode based upon xT, xA and xB at translation time. Subsequent commits will make the same changes for other instructions however the xvcmp* instructions are different in that they return a set of flags to= be optionally written back to the crf[6] register. Move this logic from the helper function to the generator function, along with the float_status upda= te. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 15 +++++------- target/ppc/helper.h | 20 +++++++++------ target/ppc/translate/vsx-impl.inc.c | 49 +++++++++++++++++++++++++++++++--= ---- 3 files changed, 59 insertions(+), 25 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5edf913a89..4b9b695333 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2746,12 +2746,11 @@ VSX_MAX_MINJ(xsminjdp, 0); * exp - expected result of comparison */ #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ + uint32_t crf6 =3D 0; = \ int i; \ int all_true =3D 1; = \ int all_false =3D 1; = \ @@ -2780,11 +2779,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ *xt =3D t; = \ - if ((opcode >> (31 - 21)) & 1) { \ - env->crf[6] =3D (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); = \ - } \ - do_float_check_status(env, GETPC()); \ - } + crf6 =3D (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); = \ + return crf6; \ +} =20 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1) VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 02b67a333e..8666415169 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -108,6 +108,10 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i6= 4) #define dh_ctype_avr ppc_avr_t * #define dh_is_signed_avr dh_is_signed_ptr =20 +#define dh_alias_vsr ptr +#define dh_ctype_vsr ppc_vsr_t * +#define dh_is_signed_vsr dh_is_signed_ptr + DEF_HELPER_3(vavgub, void, avr, avr, avr) DEF_HELPER_3(vavguh, void, avr, avr, avr) DEF_HELPER_3(vavguw, void, avr, avr, avr) @@ -468,10 +472,10 @@ DEF_HELPER_2(xvnmsubadp, void, env, i32) DEF_HELPER_2(xvnmsubmdp, void, env, i32) DEF_HELPER_2(xvmaxdp, void, env, i32) DEF_HELPER_2(xvmindp, void, env, i32) -DEF_HELPER_2(xvcmpeqdp, void, env, i32) -DEF_HELPER_2(xvcmpgedp, void, env, i32) -DEF_HELPER_2(xvcmpgtdp, void, env, i32) -DEF_HELPER_2(xvcmpnedp, void, env, i32) +DEF_HELPER_FLAGS_4(xvcmpeqdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpgedp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpgtdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpnedp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_2(xvcvdpsp, void, env, i32) DEF_HELPER_2(xvcvdpsxds, void, env, i32) DEF_HELPER_2(xvcvdpsxws, void, env, i32) @@ -506,10 +510,10 @@ DEF_HELPER_2(xvnmsubasp, void, env, i32) DEF_HELPER_2(xvnmsubmsp, void, env, i32) DEF_HELPER_2(xvmaxsp, void, env, i32) DEF_HELPER_2(xvminsp, void, env, i32) -DEF_HELPER_2(xvcmpeqsp, void, env, i32) -DEF_HELPER_2(xvcmpgesp, void, env, i32) -DEF_HELPER_2(xvcmpgtsp, void, env, i32) -DEF_HELPER_2(xvcmpnesp, void, env, i32) +DEF_HELPER_FLAGS_4(xvcmpeqsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpgesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpgtsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) +DEF_HELPER_FLAGS_4(xvcmpnesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_2(xvcvspdp, void, env, i32) DEF_HELPER_2(xvcvsphp, void, env, i32) DEF_HELPER_2(xvcvhpsp, void, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 199d22da97..fb52a5bbf7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -20,6 +20,13 @@ static inline void set_cpu_vsrl(int n, TCGv_i64 src) tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false)); } =20 +static inline TCGv_ptr gen_vsr_ptr(int reg) +{ + TCGv_ptr r =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg)); + return r; +} + #define VSX_LOAD_SCALAR(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -957,6 +964,40 @@ VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) =20 +#define VSX_CMP(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 ignored; = \ + TCGv_ptr xt, xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + if ((ctx->opcode >> (31 - 21)) & 1) { = \ + gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); = \ + } else { = \ + ignored =3D tcg_temp_new_i32(); = \ + gen_helper_##name(ignored, cpu_env, xt, xa, xb); = \ + tcg_temp_free_i32(ignored); = \ + } = \ + gen_helper_float_check_status(cpu_env); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + +VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) +VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) +VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) +VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300) +VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) +VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) +VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) +VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) + #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) = \ static void gen_##name(DisasContext *ctx) = \ { = \ @@ -1096,10 +1137,6 @@ GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) @@ -1134,10 +1171,6 @@ GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) GEN_VSX_HELPER_2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474429; cv=none; d=zoho.com; s=zohoarc; b=PhvOebJhIquQAiHkNXlX00NFdE42IrFqyvW1gdKCCuCZebr/5/LmJVDKfyTq8jrF7qkbYcGWQSwIC51vw/zCPHEYYRQudX1bRxwWRiMDb2PMuMwel9m8dHcmOvDGlW4VOPykjuKNHevDnFAffkLbKE3WzG4G25GWPxKXgBgy/m0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474429; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=MkW2FilYbJIOgeV60C+2BZLXejt5OmqFYGSTueJKOo8=; b=RghSjxRDe5kcQNxW/hE4g8FGfEoz5gUG+p1zsKzEXaocOC4dKlPrXeTJFccZYGIJ08Mo2emVTfsQdmNhTAAd5YWEXG6fntg8BFs/CtQEC96eDkSgJKfXAeoJIIppQelOqRc+g5EnAUVqDWfv88uDOHHhCpqgFjjcOOS6bL2ZM4o= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474429950738.0982422214188; Sun, 2 Jun 2019 04:20:29 -0700 (PDT) Received: from localhost ([127.0.0.1]:47755 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOX8-0000R0-HI for importer@patchew.org; Sun, 02 Jun 2019 07:20:14 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPh-0003MS-2m for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPd-0003YW-8i for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:33 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51386 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPc-0002iG-VX; Sun, 02 Jun 2019 07:12:29 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLe-0008A4-1o; Sun, 02 Jun 2019 12:08:22 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:53 +0100 Message-Id: <20190602110903.3431-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 05/15] target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X3 macro which performs the decode based upon xT, xA and xB at translation time. With the previous changes to the VSX_CMP generator and helper macros the opcode parameter is no longer required in the common case and can be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 42 ++++------- target/ppc/helper.h | 120 +++++++++++++++---------------- target/ppc/translate/vsx-impl.inc.c | 137 ++++++++++++++++++++------------= ---- 3 files changed, 151 insertions(+), 148 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 4b9b695333..386db30681 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -1801,11 +1801,9 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t = op1, uint64_t op2) * sfprf - set FPRF */ #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode) = \ +void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -1884,11 +1882,9 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcod= e) * sfprf - set FPRF */ #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -1962,11 +1958,9 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcod= e) * sfprf - set FPRF */ #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -2304,11 +2298,9 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) * sfprf - set FPRF */ #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt, *b, *c; = \ int i; = \ = \ @@ -2402,11 +2394,9 @@ VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS= , 0, 0, 0) * svxvc - set VXVC bit */ #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vxvc_flag =3D false, vex_flag =3D false; = \ = \ @@ -2614,11 +2604,9 @@ VSX_SCALAR_CMPQ(xscmpuqp, 0) * fld - vsr_t field (VsrD(*) or VsrW(*)) */ #define VSX_MAX_MIN(name, op, nels, tp, fld) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode) = \ +void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, = \ + ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -3194,11 +3182,9 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) } =20 #define VSX_XXPERM(op, indexed) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ + ppc_vsr_t *xa, ppc_vsr_t *pcv) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; \ - ppc_vsr_t *pcv =3D &env->vsr[xB(opcode)]; \ ppc_vsr_t t =3D *xt; \ int i, idx; \ \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8666415169..f6a97cedc6 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -365,38 +365,38 @@ DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdutrunc, i32, avr, avr, avr, i32) =20 -DEF_HELPER_2(xsadddp, void, env, i32) +DEF_HELPER_4(xsadddp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsaddqp, void, env, i32) -DEF_HELPER_2(xssubdp, void, env, i32) -DEF_HELPER_2(xsmuldp, void, env, i32) +DEF_HELPER_4(xssubdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmuldp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsmulqp, void, env, i32) -DEF_HELPER_2(xsdivdp, void, env, i32) +DEF_HELPER_4(xsdivdp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsdivqp, void, env, i32) DEF_HELPER_2(xsredp, void, env, i32) DEF_HELPER_2(xssqrtdp, void, env, i32) DEF_HELPER_2(xsrsqrtedp, void, env, i32) DEF_HELPER_2(xstdivdp, void, env, i32) DEF_HELPER_2(xstsqrtdp, void, env, i32) -DEF_HELPER_2(xsmaddadp, void, env, i32) -DEF_HELPER_2(xsmaddmdp, void, env, i32) -DEF_HELPER_2(xsmsubadp, void, env, i32) -DEF_HELPER_2(xsmsubmdp, void, env, i32) -DEF_HELPER_2(xsnmaddadp, void, env, i32) -DEF_HELPER_2(xsnmaddmdp, void, env, i32) -DEF_HELPER_2(xsnmsubadp, void, env, i32) -DEF_HELPER_2(xsnmsubmdp, void, env, i32) -DEF_HELPER_2(xscmpeqdp, void, env, i32) -DEF_HELPER_2(xscmpgtdp, void, env, i32) -DEF_HELPER_2(xscmpgedp, void, env, i32) -DEF_HELPER_2(xscmpnedp, void, env, i32) +DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmsubadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmaddadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmaddmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmsubadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xscmpexpdp, void, env, i32) DEF_HELPER_2(xscmpexpqp, void, env, i32) DEF_HELPER_2(xscmpodp, void, env, i32) DEF_HELPER_2(xscmpudp, void, env, i32) DEF_HELPER_2(xscmpoqp, void, env, i32) DEF_HELPER_2(xscmpuqp, void, env, i32) -DEF_HELPER_2(xsmaxdp, void, env, i32) -DEF_HELPER_2(xsmindp, void, env, i32) +DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsmaxcdp, void, env, i32) DEF_HELPER_2(xsmincdp, void, env, i32) DEF_HELPER_2(xsmaxjdp, void, env, i32) @@ -436,42 +436,42 @@ DEF_HELPER_2(xsrqpxp, void, env, i32) DEF_HELPER_2(xssqrtqp, void, env, i32) DEF_HELPER_2(xssubqp, void, env, i32) =20 -DEF_HELPER_2(xsaddsp, void, env, i32) -DEF_HELPER_2(xssubsp, void, env, i32) -DEF_HELPER_2(xsmulsp, void, env, i32) -DEF_HELPER_2(xsdivsp, void, env, i32) +DEF_HELPER_4(xsaddsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xssubsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmulsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsdivsp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsresp, void, env, i32) DEF_HELPER_2(xsrsp, i64, env, i64) DEF_HELPER_2(xssqrtsp, void, env, i32) DEF_HELPER_2(xsrsqrtesp, void, env, i32) -DEF_HELPER_2(xsmaddasp, void, env, i32) -DEF_HELPER_2(xsmaddmsp, void, env, i32) -DEF_HELPER_2(xsmsubasp, void, env, i32) -DEF_HELPER_2(xsmsubmsp, void, env, i32) -DEF_HELPER_2(xsnmaddasp, void, env, i32) -DEF_HELPER_2(xsnmaddmsp, void, env, i32) -DEF_HELPER_2(xsnmsubasp, void, env, i32) -DEF_HELPER_2(xsnmsubmsp, void, env, i32) +DEF_HELPER_4(xsmaddasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmaddmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmsubasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmsubmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmaddasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmaddmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmsubasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsnmsubmsp, void, env, vsr, vsr, vsr) =20 -DEF_HELPER_2(xvadddp, void, env, i32) -DEF_HELPER_2(xvsubdp, void, env, i32) -DEF_HELPER_2(xvmuldp, void, env, i32) -DEF_HELPER_2(xvdivdp, void, env, i32) +DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmuldp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvdivdp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xvredp, void, env, i32) DEF_HELPER_2(xvsqrtdp, void, env, i32) DEF_HELPER_2(xvrsqrtedp, void, env, i32) DEF_HELPER_2(xvtdivdp, void, env, i32) DEF_HELPER_2(xvtsqrtdp, void, env, i32) -DEF_HELPER_2(xvmaddadp, void, env, i32) -DEF_HELPER_2(xvmaddmdp, void, env, i32) -DEF_HELPER_2(xvmsubadp, void, env, i32) -DEF_HELPER_2(xvmsubmdp, void, env, i32) -DEF_HELPER_2(xvnmaddadp, void, env, i32) -DEF_HELPER_2(xvnmaddmdp, void, env, i32) -DEF_HELPER_2(xvnmsubadp, void, env, i32) -DEF_HELPER_2(xvnmsubmdp, void, env, i32) -DEF_HELPER_2(xvmaxdp, void, env, i32) -DEF_HELPER_2(xvmindp, void, env, i32) +DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmsubadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmaddadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmaddmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmsubadp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmaxdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmindp, void, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpeqdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgedp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgtdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) @@ -491,25 +491,25 @@ DEF_HELPER_2(xvrdpim, void, env, i32) DEF_HELPER_2(xvrdpip, void, env, i32) DEF_HELPER_2(xvrdpiz, void, env, i32) =20 -DEF_HELPER_2(xvaddsp, void, env, i32) -DEF_HELPER_2(xvsubsp, void, env, i32) -DEF_HELPER_2(xvmulsp, void, env, i32) -DEF_HELPER_2(xvdivsp, void, env, i32) +DEF_HELPER_4(xvaddsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvsubsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmulsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvdivsp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xvresp, void, env, i32) DEF_HELPER_2(xvsqrtsp, void, env, i32) DEF_HELPER_2(xvrsqrtesp, void, env, i32) DEF_HELPER_2(xvtdivsp, void, env, i32) DEF_HELPER_2(xvtsqrtsp, void, env, i32) -DEF_HELPER_2(xvmaddasp, void, env, i32) -DEF_HELPER_2(xvmaddmsp, void, env, i32) -DEF_HELPER_2(xvmsubasp, void, env, i32) -DEF_HELPER_2(xvmsubmsp, void, env, i32) -DEF_HELPER_2(xvnmaddasp, void, env, i32) -DEF_HELPER_2(xvnmaddmsp, void, env, i32) -DEF_HELPER_2(xvnmsubasp, void, env, i32) -DEF_HELPER_2(xvnmsubmsp, void, env, i32) -DEF_HELPER_2(xvmaxsp, void, env, i32) -DEF_HELPER_2(xvminsp, void, env, i32) +DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmsubasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmsubmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmaddasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmaddmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmsubasp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvnmsubmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvmaxsp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xvminsp, void, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpeqsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgtsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) @@ -532,8 +532,8 @@ DEF_HELPER_2(xvrspic, void, env, i32) DEF_HELPER_2(xvrspim, void, env, i32) DEF_HELPER_2(xvrspip, void, env, i32) DEF_HELPER_2(xvrspiz, void, env, i32) -DEF_HELPER_2(xxperm, void, env, i32) -DEF_HELPER_2(xxpermr, void, env, i32) +DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr) DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32) DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32) DEF_HELPER_2(xvxsigsp, void, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index fb52a5bbf7..0befbb508f 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1011,6 +1011,23 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i32(opc); = \ } =20 +#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_ptr xt, xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + gen_helper_##name(cpu_env, xt, xa, xb); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1029,38 +1046,38 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i64(t1); \ } =20 -GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) @@ -1097,46 +1114,46 @@ GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA30= 0) GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_2(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) =20 -GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) =20 -GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) @@ -1152,25 +1169,25 @@ GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) =20 -GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) GEN_VSX_HELPER_2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) @@ -1189,8 +1206,8 @@ GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) =20 static void gen_xxbrd(DisasContext *ctx) { --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474086; cv=none; d=zoho.com; s=zohoarc; b=HpHhOrF0m2zcOWZoPKoz2bqR1W47XJfJ1OAHYDQt7YQCBzOd1dXNzz63I3hrCy6MDWwOVjrEC4wmcK+aQW7Ir+rqre5iYHZ5/ZmctHMNZjHTkG4k1nm+4Rxt2ZQ/z/B6HheQ+Len5tG28a7MYjBvwLlFHhvO5DE1/QmSeP28K/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474086; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1eX+C0xfFu8NPC9j16PkGGW+HPVPAOCHqBPtuGu8QPY=; b=SmwE/bTKckByo5y9lRPZxt2541I0aYpoTen3OzS9jIWRj44qS0aYlRWIlPxtFLPBm2K7H7wI5jCzdv03wFqlJOP9lPQ42RxeVFZIXaJ8sTLHR+eeElu8+/ILFWi+NKhW6HNaHZR/JBfVNgGY/yGln5otkRU3pVSdHab6f4Cxgvo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474086212261.4923258284971; Sun, 2 Jun 2019 04:14:46 -0700 (PDT) Received: from localhost ([127.0.0.1]:47673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXORa-0004Se-JQ for importer@patchew.org; Sun, 02 Jun 2019 07:14:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPc-0003LM-V5 for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPb-0003Wu-Oi for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:28 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51390 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPb-0002iJ-Is; Sun, 02 Jun 2019 07:12:27 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLf-0008A4-0O; Sun, 02 Jun 2019 12:08:23 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:54 +0100 Message-Id: <20190602110903.3431-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 06/15] target/ppc: introduce separate generator and helper for xscvqpdp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new generator and helper function which perform the decode based upon xT and xB at translation time. The xscvqpdp helper is the only 2 parameter xT/xB implementation that requi= res the opcode to be passed as an additional parameter, so handling this separa= tely allows us to optimise the conversion in the next commit. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 5 ++--- target/ppc/helper.h | 2 +- target/ppc/translate/vsx-impl.inc.c | 18 +++++++++++++++++- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 386db30681..a6556781e1 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2899,10 +2899,9 @@ VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, V= srH(2 * i + 1), VsrW(i), 0) * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be * added to this later. */ -void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode) +void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; ppc_vsr_t t =3D { }; float_status tstat; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f6a97cedc6..5d15166988 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -405,7 +405,7 @@ DEF_HELPER_2(xscvdphp, void, env, i32) DEF_HELPER_2(xscvdpqp, void, env, i32) DEF_HELPER_2(xscvdpsp, void, env, i32) DEF_HELPER_2(xscvdpspn, i64, env, i64) -DEF_HELPER_2(xscvqpdp, void, env, i32) +DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscvqpsdz, void, env, i32) DEF_HELPER_2(xscvqpswz, void, env, i32) DEF_HELPER_2(xscvqpudz, void, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 0befbb508f..eac8c8937b 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -998,6 +998,23 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) =20 +static void gen_xscvqpdp(DisasContext *ctx) +{ + TCGv_i32 opc; + TCGv_ptr xt, xb; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + opc =3D tcg_const_i32(ctx->opcode); + xt =3D gen_vsr_ptr(xT(ctx->opcode)); + xb =3D gen_vsr_ptr(xB(ctx->opcode)); + gen_helper_xscvqpdp(cpu_env, opc, xt, xb); + tcg_temp_free_i32(opc); + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xb); +} + #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) = \ static void gen_##name(DisasContext *ctx) = \ { = \ @@ -1086,7 +1103,6 @@ GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA= 300) GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474131; cv=none; d=zoho.com; s=zohoarc; b=SJnHAMWxXSrUneK/0ptRVEgXP/ZN3STn6/RQDmrdx1CgjR1/div7BPp9GiyyTnfWOw0kWQ3jPLHKBs5kEiSHtOxyhw4pV1N65CtJ43GL7RcFdQhDQuICJ77muURtnTX7hpkhzxNL0mpXLpPnme407BGxLiQC5GazJ8x7sB/QftM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474131; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XIUtr6G/U8A8cjp9tXo2vRMW+y1yaPj9s5xeaKZY6Hg=; b=nwE69msaIw9+gHTa225tDgIUwg5Yxj6Ec53s1fvvn26rnJDlpSZCspB+QLUCCJ/wEwumfHiyHuDkudQmeGR9xI+Ul7AHsZRO79musfe/oM+LJ8fV1h9nVtALrFIGy93YIMXtQ93tQjA0UHQIUzeRRGorHGlCtD7rWgjKDa2M7X8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474131143289.34447999022746; Sun, 2 Jun 2019 04:15:31 -0700 (PDT) Received: from localhost ([127.0.0.1]:47680 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOSS-000581-Ud for importer@patchew.org; Sun, 02 Jun 2019 07:15:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPh-0003NC-Mt for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPd-0003ZB-SY for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:33 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51398 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPd-0002kW-JF; Sun, 02 Jun 2019 07:12:29 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLf-0008A4-F1; Sun, 02 Jun 2019 12:08:24 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:55 +0100 Message-Id: <20190602110903.3431-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 07/15] target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X2 macro which performs the decode based upon xT and xB at translation time. With the previous change to the xscvqpdp generator and helper functions the opcode parameter is no longer required in the common case and can be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 36 +++------- target/ppc/helper.h | 120 ++++++++++++++++---------------- target/ppc/translate/vsx-impl.inc.c | 135 ++++++++++++++++++++------------= ---- 3 files changed, 144 insertions(+), 147 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index a6556781e1..c7f5b49e03 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2040,10 +2040,8 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcod= e) * sfprf - set FPRF */ #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -2082,10 +2080,8 @@ VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0) * sfprf - set FPRF */ #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -2132,10 +2128,8 @@ VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0) * sfprf - set FPRF */ #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -2791,10 +2785,8 @@ VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0) * sfprf - set FPRF */ #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ ppc_vsr_t t =3D *xt; \ int i; \ \ @@ -2867,10 +2859,8 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float1= 28, VsrD(0), f128, 1) * sfprf - set FPRF */ #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ ppc_vsr_t t =3D { }; \ int i; \ \ @@ -2949,11 +2939,9 @@ uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t= xb) * rnan - resulting NaN */ #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ int all_flags =3D env->fp_status.float_exception_flags, flags; = \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ ppc_vsr_t t =3D *xt; = \ int i; = \ = \ @@ -3037,10 +3025,8 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32= , f128, VsrD(0), 0x0ULL) * sfprf - set FPRF */ #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ ppc_vsr_t t =3D *xt; \ int i; \ \ @@ -3113,10 +3099,8 @@ VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128,= VsrD(0), f128) * sfprf - set FPRF */ #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ ppc_vsr_t t =3D *xt; \ int i; \ \ @@ -3201,10 +3185,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ VSX_XXPERM(xxperm, 0) VSX_XXPERM(xxpermr, 1) =20 -void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode) +void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[xT(opcode)]; - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; ppc_vsr_t t =3D *xt; uint32_t exp, i, fraction; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5d15166988..f56476ec41 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -372,9 +372,9 @@ DEF_HELPER_4(xsmuldp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsmulqp, void, env, i32) DEF_HELPER_4(xsdivdp, void, env, vsr, vsr, vsr) DEF_HELPER_2(xsdivqp, void, env, i32) -DEF_HELPER_2(xsredp, void, env, i32) -DEF_HELPER_2(xssqrtdp, void, env, i32) -DEF_HELPER_2(xsrsqrtedp, void, env, i32) +DEF_HELPER_3(xsredp, void, env, vsr, vsr) +DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) +DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) DEF_HELPER_2(xstdivdp, void, env, i32) DEF_HELPER_2(xstsqrtdp, void, env, i32) DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) @@ -401,36 +401,36 @@ DEF_HELPER_2(xsmaxcdp, void, env, i32) DEF_HELPER_2(xsmincdp, void, env, i32) DEF_HELPER_2(xsmaxjdp, void, env, i32) DEF_HELPER_2(xsminjdp, void, env, i32) -DEF_HELPER_2(xscvdphp, void, env, i32) +DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpqp, void, env, i32) -DEF_HELPER_2(xscvdpsp, void, env, i32) +DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpspn, i64, env, i64) DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscvqpsdz, void, env, i32) DEF_HELPER_2(xscvqpswz, void, env, i32) DEF_HELPER_2(xscvqpudz, void, env, i32) DEF_HELPER_2(xscvqpuwz, void, env, i32) -DEF_HELPER_2(xscvhpdp, void, env, i32) +DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr) DEF_HELPER_2(xscvsdqp, void, env, i32) -DEF_HELPER_2(xscvspdp, void, env, i32) +DEF_HELPER_3(xscvspdp, void, env, vsr, vsr) DEF_HELPER_2(xscvspdpn, i64, env, i64) -DEF_HELPER_2(xscvdpsxds, void, env, i32) -DEF_HELPER_2(xscvdpsxws, void, env, i32) -DEF_HELPER_2(xscvdpuxds, void, env, i32) -DEF_HELPER_2(xscvdpuxws, void, env, i32) -DEF_HELPER_2(xscvsxddp, void, env, i32) -DEF_HELPER_2(xscvuxdsp, void, env, i32) -DEF_HELPER_2(xscvsxdsp, void, env, i32) +DEF_HELPER_3(xscvdpsxds, void, env, vsr, vsr) +DEF_HELPER_3(xscvdpsxws, void, env, vsr, vsr) +DEF_HELPER_3(xscvdpuxds, void, env, vsr, vsr) +DEF_HELPER_3(xscvdpuxws, void, env, vsr, vsr) +DEF_HELPER_3(xscvsxddp, void, env, vsr, vsr) +DEF_HELPER_3(xscvuxdsp, void, env, vsr, vsr) +DEF_HELPER_3(xscvsxdsp, void, env, vsr, vsr) DEF_HELPER_2(xscvudqp, void, env, i32) -DEF_HELPER_2(xscvuxddp, void, env, i32) +DEF_HELPER_3(xscvuxddp, void, env, vsr, vsr) DEF_HELPER_2(xststdcsp, void, env, i32) DEF_HELPER_2(xststdcdp, void, env, i32) DEF_HELPER_2(xststdcqp, void, env, i32) -DEF_HELPER_2(xsrdpi, void, env, i32) -DEF_HELPER_2(xsrdpic, void, env, i32) -DEF_HELPER_2(xsrdpim, void, env, i32) -DEF_HELPER_2(xsrdpip, void, env, i32) -DEF_HELPER_2(xsrdpiz, void, env, i32) +DEF_HELPER_3(xsrdpi, void, env, vsr, vsr) +DEF_HELPER_3(xsrdpic, void, env, vsr, vsr) +DEF_HELPER_3(xsrdpim, void, env, vsr, vsr) +DEF_HELPER_3(xsrdpip, void, env, vsr, vsr) +DEF_HELPER_3(xsrdpiz, void, env, vsr, vsr) DEF_HELPER_2(xsrqpi, void, env, i32) DEF_HELPER_2(xsrqpxp, void, env, i32) DEF_HELPER_2(xssqrtqp, void, env, i32) @@ -440,10 +440,10 @@ DEF_HELPER_4(xsaddsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xssubsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmulsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsdivsp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xsresp, void, env, i32) +DEF_HELPER_3(xsresp, void, env, vsr, vsr) DEF_HELPER_2(xsrsp, i64, env, i64) -DEF_HELPER_2(xssqrtsp, void, env, i32) -DEF_HELPER_2(xsrsqrtesp, void, env, i32) +DEF_HELPER_3(xssqrtsp, void, env, vsr, vsr) +DEF_HELPER_3(xsrsqrtesp, void, env, vsr, vsr) DEF_HELPER_4(xsmaddasp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmaddmsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmsubasp, void, env, vsr, vsr, vsr) @@ -457,9 +457,9 @@ DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmuldp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvdivdp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xvredp, void, env, i32) -DEF_HELPER_2(xvsqrtdp, void, env, i32) -DEF_HELPER_2(xvrsqrtedp, void, env, i32) +DEF_HELPER_3(xvredp, void, env, vsr, vsr) +DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) +DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) DEF_HELPER_2(xvtdivdp, void, env, i32) DEF_HELPER_2(xvtsqrtdp, void, env, i32) DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) @@ -476,28 +476,28 @@ DEF_HELPER_FLAGS_4(xvcmpeqdp, TCG_CALL_NO_RWG, i32, e= nv, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgedp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgtdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpnedp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) -DEF_HELPER_2(xvcvdpsp, void, env, i32) -DEF_HELPER_2(xvcvdpsxds, void, env, i32) -DEF_HELPER_2(xvcvdpsxws, void, env, i32) -DEF_HELPER_2(xvcvdpuxds, void, env, i32) -DEF_HELPER_2(xvcvdpuxws, void, env, i32) -DEF_HELPER_2(xvcvsxddp, void, env, i32) -DEF_HELPER_2(xvcvuxddp, void, env, i32) -DEF_HELPER_2(xvcvsxwdp, void, env, i32) -DEF_HELPER_2(xvcvuxwdp, void, env, i32) -DEF_HELPER_2(xvrdpi, void, env, i32) -DEF_HELPER_2(xvrdpic, void, env, i32) -DEF_HELPER_2(xvrdpim, void, env, i32) -DEF_HELPER_2(xvrdpip, void, env, i32) -DEF_HELPER_2(xvrdpiz, void, env, i32) +DEF_HELPER_3(xvcvdpsp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvdpsxds, void, env, vsr, vsr) +DEF_HELPER_3(xvcvdpsxws, void, env, vsr, vsr) +DEF_HELPER_3(xvcvdpuxds, void, env, vsr, vsr) +DEF_HELPER_3(xvcvdpuxws, void, env, vsr, vsr) +DEF_HELPER_3(xvcvsxddp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvuxddp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvsxwdp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvuxwdp, void, env, vsr, vsr) +DEF_HELPER_3(xvrdpi, void, env, vsr, vsr) +DEF_HELPER_3(xvrdpic, void, env, vsr, vsr) +DEF_HELPER_3(xvrdpim, void, env, vsr, vsr) +DEF_HELPER_3(xvrdpip, void, env, vsr, vsr) +DEF_HELPER_3(xvrdpiz, void, env, vsr, vsr) =20 DEF_HELPER_4(xvaddsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvsubsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmulsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvdivsp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xvresp, void, env, i32) -DEF_HELPER_2(xvsqrtsp, void, env, i32) -DEF_HELPER_2(xvrsqrtesp, void, env, i32) +DEF_HELPER_3(xvresp, void, env, vsr, vsr) +DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) +DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) DEF_HELPER_2(xvtdivsp, void, env, i32) DEF_HELPER_2(xvtsqrtsp, void, env, i32) DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) @@ -514,29 +514,29 @@ DEF_HELPER_FLAGS_4(xvcmpeqsp, TCG_CALL_NO_RWG, i32, e= nv, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpgtsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpnesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) -DEF_HELPER_2(xvcvspdp, void, env, i32) -DEF_HELPER_2(xvcvsphp, void, env, i32) -DEF_HELPER_2(xvcvhpsp, void, env, i32) -DEF_HELPER_2(xvcvspsxds, void, env, i32) -DEF_HELPER_2(xvcvspsxws, void, env, i32) -DEF_HELPER_2(xvcvspuxds, void, env, i32) -DEF_HELPER_2(xvcvspuxws, void, env, i32) -DEF_HELPER_2(xvcvsxdsp, void, env, i32) -DEF_HELPER_2(xvcvuxdsp, void, env, i32) -DEF_HELPER_2(xvcvsxwsp, void, env, i32) -DEF_HELPER_2(xvcvuxwsp, void, env, i32) +DEF_HELPER_3(xvcvspdp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvsphp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvhpsp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvspsxds, void, env, vsr, vsr) +DEF_HELPER_3(xvcvspsxws, void, env, vsr, vsr) +DEF_HELPER_3(xvcvspuxds, void, env, vsr, vsr) +DEF_HELPER_3(xvcvspuxws, void, env, vsr, vsr) +DEF_HELPER_3(xvcvsxdsp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvuxdsp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvsxwsp, void, env, vsr, vsr) +DEF_HELPER_3(xvcvuxwsp, void, env, vsr, vsr) DEF_HELPER_2(xvtstdcsp, void, env, i32) DEF_HELPER_2(xvtstdcdp, void, env, i32) -DEF_HELPER_2(xvrspi, void, env, i32) -DEF_HELPER_2(xvrspic, void, env, i32) -DEF_HELPER_2(xvrspim, void, env, i32) -DEF_HELPER_2(xvrspip, void, env, i32) -DEF_HELPER_2(xvrspiz, void, env, i32) +DEF_HELPER_3(xvrspi, void, env, vsr, vsr) +DEF_HELPER_3(xvrspic, void, env, vsr, vsr) +DEF_HELPER_3(xvrspim, void, env, vsr, vsr) +DEF_HELPER_3(xvrspip, void, env, vsr, vsr) +DEF_HELPER_3(xvrspiz, void, env, vsr, vsr) DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr) DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr) DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32) DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32) -DEF_HELPER_2(xvxsigsp, void, env, i32) +DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr) =20 DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index eac8c8937b..1fb2bf7064 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1045,6 +1045,21 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_ptr xt, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + gen_helper_##name(cpu_env, xt, xb); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1070,9 +1085,9 @@ GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) @@ -1099,30 +1114,30 @@ GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA3= 00) GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) GEN_VSX_HELPER_2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) =20 GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) @@ -1134,9 +1149,9 @@ GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) @@ -1145,8 +1160,8 @@ GEN_VSX_HELPER_X3(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX= 207) GEN_VSX_HELPER_X3(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) @@ -1155,9 +1170,9 @@ GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) @@ -1170,28 +1185,28 @@ GEN_VSX_HELPER_X3(xvnmsubadp, 0x04, 0x1E, 0, PPC2_V= SX) GEN_VSX_HELPER_X3(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) =20 GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) @@ -1204,22 +1219,22 @@ GEN_VSX_HELPER_X3(xvnmsubasp, 0x04, 0x1A, 0, PPC2_V= SX) GEN_VSX_HELPER_X3(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) -GEN_VSX_HELPER_2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) -GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) +GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) +GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) @@ -1898,7 +1913,7 @@ static void gen_xvxexpdp(DisasContext *ctx) tcg_temp_free_i64(xbl); } =20 -GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) =20 static void gen_xvxsigdp(DisasContext *ctx) { --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474087; cv=none; d=zoho.com; s=zohoarc; b=EsTPQha1sllAj8a4TqgFsVjZpev6VOLPMWLRdiVNtuAAGnfpgKa3HdWKpNa4CYy6f5kU5yMqPj2QqarER3ITu63+CB2o8s38/ZnAoElp3X7otNZZYEa1gUUlmlw4J2xjG/n3ORU0hPUu6w6q66mavDrJ981fARWuVvJsWKPWu3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474087; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0Ubn/dPoAsxQ/Lv+l9T3t2F6ozOXd4rBOuUpJ6Y2JgI=; b=h6kr7Gxd0juYIBQFgQOqaT/M6tIVf+zBSICnpXpt2Iiyg6SBWitJ+0hAHzwfbfQL3d1DnHZHRkwdLNd0KOz9MhJ8fDdU5M7FT2tDlqlahIPErZxu8z4PaSW5Alpx+WouMF3I7XNSj3kS3U1UHQDD8IPtY7WRQCK7xa/Sqrs2IVM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474087195428.52393449681847; Sun, 2 Jun 2019 04:14:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:47677 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXORh-0004Zb-J8 for importer@patchew.org; Sun, 02 Jun 2019 07:14:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPg-0003Ls-Dw for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPd-0003Z0-Nj for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:32 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51402 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPd-0002kU-I2; Sun, 02 Jun 2019 07:12:29 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLg-0008A4-F8; Sun, 02 Jun 2019 12:08:24 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:56 +0100 Message-Id: <20190602110903.3431-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 08/15] target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X2_AB macro which performs the decode based upon xA and xB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 15 ++++++--------- target/ppc/helper.h | 12 ++++++------ target/ppc/translate/vsx-impl.inc.c | 30 ++++++++++++++++++++++++------ 3 files changed, 36 insertions(+), 21 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c7f5b49e03..628621d1b2 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2179,10 +2179,9 @@ VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0) * nbits - number of fraction bits */ #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ int i; \ int fe_flag =3D 0; \ int fg_flag =3D 0; \ @@ -2431,10 +2430,9 @@ VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1) VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1) VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0) =20 -void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode) +void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; int64_t exp_a, exp_b; uint32_t cc; =20 @@ -2492,10 +2490,9 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t op= code) } =20 #define VSX_SCALAR_CMP(op, ordered) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xa =3D &env->vsr[xA(opcode)]; = \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; = \ uint32_t cc =3D 0; = \ bool vxsnan_flag =3D false, vxvc_flag =3D false; = \ \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f56476ec41..0ab1ef2aee 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -375,7 +375,7 @@ DEF_HELPER_2(xsdivqp, void, env, i32) DEF_HELPER_3(xsredp, void, env, vsr, vsr) DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) -DEF_HELPER_2(xstdivdp, void, env, i32) +DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xstsqrtdp, void, env, i32) DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) @@ -389,10 +389,10 @@ DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xscmpexpdp, void, env, i32) +DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscmpexpqp, void, env, i32) -DEF_HELPER_2(xscmpodp, void, env, i32) -DEF_HELPER_2(xscmpudp, void, env, i32) +DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscmpudp, void, env, i32, vsr, vsr) DEF_HELPER_2(xscmpoqp, void, env, i32) DEF_HELPER_2(xscmpuqp, void, env, i32) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) @@ -460,7 +460,7 @@ DEF_HELPER_4(xvdivdp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xvredp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) -DEF_HELPER_2(xvtdivdp, void, env, i32) +DEF_HELPER_4(xvtdivdp, void, env, i32, vsr, vsr) DEF_HELPER_2(xvtsqrtdp, void, env, i32) DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) @@ -498,7 +498,7 @@ DEF_HELPER_4(xvdivsp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xvresp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) -DEF_HELPER_2(xvtdivsp, void, env, i32) +DEF_HELPER_4(xvtdivsp, void, env, i32, vsr, vsr) DEF_HELPER_2(xvtsqrtsp, void, env, i32) DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 1fb2bf7064..d8e9b80d4a 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1060,6 +1060,24 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + gen_helper_##name(cpu_env, opc, xa, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1088,7 +1106,7 @@ GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) @@ -1102,10 +1120,10 @@ GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_IS= A300) GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) @@ -1173,7 +1191,7 @@ GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) @@ -1207,7 +1225,7 @@ GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559474264; cv=none; d=zoho.com; s=zohoarc; b=EHtG3dd9fcm6sy1oW1ddPyNzdifk5nDm91toNpbtM01F+VVAxlbe/IZXWTBwPfn1/7ZjH0jnokyztVKl81J7NVUS/Lxbf3LGOXlBroCyyFbtAVNhUWwOeg9fKzdxuRXJI60L9xuTu6Jx/zmBxVsXMc+V/aKxgk1eBnhxIfpuaWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559474264; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZJqIfbTcsuL47h4utLeCXpSt5k113pptR8JdLODZCzw=; b=GDPCggsJ+gAt/W/nn6KV9wWTARuBlg3eGA4d4GWiC4XVwbhYX1pPbz04v/OOMpiEC7xNtTKLjbfWu7duhg+6Ko8HxmWDDWTMRYUyaXKBlJFFZhPRs+MIf3KWs8I7TtovOKVQHf8LD88Jg0JsiIlV16Ws2hTuLiuG4QIEAA20BME= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559474264707305.9804620049192; Sun, 2 Jun 2019 04:17:44 -0700 (PDT) Received: from localhost ([127.0.0.1]:47737 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOUd-00073q-Ib for importer@patchew.org; Sun, 02 Jun 2019 07:17:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOPh-0003NO-On for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOPf-0003bj-OV for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:12:33 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51410 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOPf-0002mJ-Hy; Sun, 02 Jun 2019 07:12:31 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLh-0008A4-2d; Sun, 02 Jun 2019 12:08:25 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:57 +0100 Message-Id: <20190602110903.3431-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 09/15] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based upon xB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 6 ++---- target/ppc/helper.h | 8 ++++---- target/ppc/translate/vsx-impl.inc.c | 24 ++++++++++++++++++++---- 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 628621d1b2..953d57d34e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2236,9 +2236,8 @@ VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23) * nbits - number of fraction bits */ #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; \ int i; \ int fe_flag =3D 0; \ int fg_flag =3D 0; \ @@ -3258,9 +3257,8 @@ VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i= ), VsrW(i), UINT32_MAX, 0) VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1) VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1) =20 -void helper_xststdcsp(CPUPPCState *env, uint32_t opcode) +void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) { - ppc_vsr_t *xb =3D &env->vsr[xB(opcode)]; uint32_t dcmx, sign, exp; uint32_t cc, match =3D 0, not_sp =3D 0; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 0ab1ef2aee..a8886c56ad 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -376,7 +376,7 @@ DEF_HELPER_3(xsredp, void, env, vsr, vsr) DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xstsqrtdp, void, env, i32) +DEF_HELPER_3(xstsqrtdp, void, env, i32, vsr) DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmsubadp, void, env, vsr, vsr, vsr) @@ -423,7 +423,7 @@ DEF_HELPER_3(xscvuxdsp, void, env, vsr, vsr) DEF_HELPER_3(xscvsxdsp, void, env, vsr, vsr) DEF_HELPER_2(xscvudqp, void, env, i32) DEF_HELPER_3(xscvuxddp, void, env, vsr, vsr) -DEF_HELPER_2(xststdcsp, void, env, i32) +DEF_HELPER_3(xststdcsp, void, env, i32, vsr) DEF_HELPER_2(xststdcdp, void, env, i32) DEF_HELPER_2(xststdcqp, void, env, i32) DEF_HELPER_3(xsrdpi, void, env, vsr, vsr) @@ -461,7 +461,7 @@ DEF_HELPER_3(xvredp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xvtsqrtdp, void, env, i32) +DEF_HELPER_3(xvtsqrtdp, void, env, i32, vsr) DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmsubadp, void, env, vsr, vsr, vsr) @@ -499,7 +499,7 @@ DEF_HELPER_3(xvresp, void, env, vsr, vsr) DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivsp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xvtsqrtsp, void, env, i32) +DEF_HELPER_3(xvtsqrtsp, void, env, i32, vsr) DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmsubasp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index d8e9b80d4a..e4831700bf 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1078,6 +1078,22 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + gen_helper_##name(cpu_env, opc, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1107,7 +1123,7 @@ GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) @@ -1180,7 +1196,7 @@ GEN_VSX_HELPER_X3(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX= 207) GEN_VSX_HELPER_X3(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) =20 @@ -1192,7 +1208,7 @@ GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) @@ -1226,7 +1242,7 @@ GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559475909; cv=none; d=zoho.com; s=zohoarc; b=e9vnBQxTvwAtlD0mnegMy49Qe2cg5C4Ae6x9WSb0g2vUQmRfyU/XRY6ix1BWFPGfb7t1DehdCz1s5qrDS50f605qNQj7PD2ugfhy3jIs67HjVQFWj5x5hZqgBNP0yHnoFcIzyfUQA7Rs6hwLQvVCjGnaSufwVP3PcRnlEX3TByI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559475909; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=rPU30Nkze0R4o2OmAf6s9HgmKS0OP6s4fJ1p1E1vO2A=; b=MUPIZ7Ch5YTrO70esjOYIk+a/ftOw/eyQrKJTRmFZFF7qt9bKz9680Wv0Yx6yOHLGyd/nY2oC3xELCdRzOfKoj5W/oAmKV/ipZh+U6oyfyFkgkfyOlb/CmAieiX/447a5oZPOcUBwCnw4mARpd9eRV9WSMQzrePqGFMJZ+MCems= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559475909854478.3663173797222; Sun, 2 Jun 2019 04:45:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:47971 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOvB-0006Fh-Sq for importer@patchew.org; Sun, 02 Jun 2019 07:45:05 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtE-0004pU-GG for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOln-0008Cq-TY for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:35:25 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51542 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOln-0008BY-Ba; Sun, 02 Jun 2019 07:35:23 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLh-0008A4-Kl; Sun, 02 Jun 2019 12:08:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:58 +0100 Message-Id: <20190602110903.3431-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 10/15] target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R3 macro which performs the decode based upon rD, rA and rB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 36 ++++++++++++---------------------= --- target/ppc/helper.h | 16 ++++++++-------- target/ppc/translate/vsx-impl.inc.c | 36 ++++++++++++++++++++++++++++-----= --- 3 files changed, 48 insertions(+), 40 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 953d57d34e..90d3566ec8 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -1842,11 +1842,9 @@ VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1) VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0) VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0) =20 -void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) +void helper_xsaddqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D *xt; float_status tstat; =20 @@ -1920,11 +1918,9 @@ VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1) VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0) VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0) =20 -void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) +void helper_xsmulqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D *xt; float_status tstat; =20 @@ -1999,11 +1995,9 @@ VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1) VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0) VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0) =20 -void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) +void helper_xsdivqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D *xt; float_status tstat; =20 @@ -2620,11 +2614,9 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i)) VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) =20 #define VSX_MAX_MINC(name, max) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode) = \ +void helper_##name(CPUPPCState *env, uint32_t opcode, = \ + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; = \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vex_flag =3D false; = \ = \ @@ -2657,11 +2649,9 @@ VSX_MAX_MINC(xsmaxcdp, 1); VSX_MAX_MINC(xsmincdp, 0); =20 #define VSX_MAX_MINJ(name, max) = \ -void helper_##name(CPUPPCState *env, uint32_t opcode) = \ +void helper_##name(CPUPPCState *env, uint32_t opcode, = \ + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; = \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ ppc_vsr_t t =3D *xt; = \ bool vxsnan_flag =3D false, vex_flag =3D false; = \ = \ @@ -3436,11 +3426,9 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opco= de) do_float_check_status(env, GETPC()); } =20 -void helper_xssubqp(CPUPPCState *env, uint32_t opcode) +void helper_xssubqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D *xt; float_status tstat; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a8886c56ad..9134da9cbb 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -366,12 +366,12 @@ DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdutrunc, i32, avr, avr, avr, i32) =20 DEF_HELPER_4(xsadddp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xsaddqp, void, env, i32) +DEF_HELPER_5(xsaddqp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_4(xssubdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmuldp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xsmulqp, void, env, i32) +DEF_HELPER_5(xsmulqp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_4(xsdivdp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xsdivqp, void, env, i32) +DEF_HELPER_5(xsdivqp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_3(xsredp, void, env, vsr, vsr) DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) @@ -397,10 +397,10 @@ DEF_HELPER_2(xscmpoqp, void, env, i32) DEF_HELPER_2(xscmpuqp, void, env, i32) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) -DEF_HELPER_2(xsmaxcdp, void, env, i32) -DEF_HELPER_2(xsmincdp, void, env, i32) -DEF_HELPER_2(xsmaxjdp, void, env, i32) -DEF_HELPER_2(xsminjdp, void, env, i32) +DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpqp, void, env, i32) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) @@ -434,7 +434,7 @@ DEF_HELPER_3(xsrdpiz, void, env, vsr, vsr) DEF_HELPER_2(xsrqpi, void, env, i32) DEF_HELPER_2(xsrqpxp, void, env, i32) DEF_HELPER_2(xssqrtqp, void, env, i32) -DEF_HELPER_2(xssubqp, void, env, i32) +DEF_HELPER_5(xssubqp, void, env, i32, vsr, vsr, vsr) =20 DEF_HELPER_4(xsaddsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xssubsp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index e4831700bf..1aa6e04e39 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1094,6 +1094,26 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xt, xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ + xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ + xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ + gen_helper_##name(cpu_env, opc, xt, xa, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1113,12 +1133,12 @@ static void gen_##name(DisasContext *ctx) = \ } =20 GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) @@ -1144,10 +1164,10 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) @@ -1177,7 +1197,7 @@ GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_V= SX207) GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) -GEN_VSX_HELPER_2(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) =20 GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559475908; cv=none; d=zoho.com; s=zohoarc; b=Bp64MpYYWQiGojF/3hYZud3XYVE0XlWC6o1kXEXn/77tX2NejZewYAJo5Sbosu5Avm3trTeX3RAt28Zrb9vnLg57SF8ZQa29mNwyOfu2yp93uo47Um1S74airNWzyhlnDL27SutJKb/FsoxB1C4ZyhLV3Mc3aYYBhh7ET9/6YUk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559475908; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=GOS59HgANJNHsJGj9faaHX7oRML8JujtEwTvjDZULdM=; b=WE/pZns3oL64jM1gtLZTEX5lmD15jrmsHBxbbJ2banXSs2a1hTMwvUQc1exbzGl3MLaRryYd/qSmYON0DpPk47Y/K3O0E/yKClrY1jtPYsztz3ZyGap8ebYxu+qM21A0KGapzumt1LasoB3FDogricw9sT475YWVZjPGAKLztv4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559475908988127.12547889695804; Sun, 2 Jun 2019 04:45:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:47969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOv7-0006DH-Rm for importer@patchew.org; Sun, 02 Jun 2019 07:45:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtG-0004vL-7S for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOlg-00085o-Dn for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:35:18 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51534 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOlg-00085L-2r; Sun, 02 Jun 2019 07:35:16 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLi-0008A4-8x; Sun, 02 Jun 2019 12:08:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:08:59 +0100 Message-Id: <20190602110903.3431-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 11/15] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based upon rD and rB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 30 ++++++++++++----------------- target/ppc/helper.h | 20 +++++++++---------- target/ppc/translate/vsx-impl.inc.c | 38 +++++++++++++++++++++++++++------= ---- 3 files changed, 50 insertions(+), 38 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 90d3566ec8..ba52ef597e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2808,10 +2808,9 @@ VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW= (2 * i), VsrD(i), 0) * sfprf - set FPRF */ #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ ppc_vsr_t t =3D *xt; \ int i; \ \ @@ -2975,10 +2974,9 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, Vs= rW(i), VsrW(i), 0U) * rnan - resulting NaN */ #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) = \ -void helper_##op(CPUPPCState *env, uint32_t opcode) = \ +void helper_##op(CPUPPCState *env, uint32_t opcode, = \ + ppc_vsr_t *xt, ppc_vsr_t *xb) = \ { = \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; = \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; = \ ppc_vsr_t t =3D { }; = \ = \ t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); = \ @@ -3052,10 +3050,9 @@ VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, Vsr= W(i), VsrW(i), 0, 0) * tfld - target vsr_t field */ #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ ppc_vsr_t t =3D *xt; \ \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ @@ -3278,10 +3275,9 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opc= ode, ppc_vsr_t *xb) env->crf[BF(opcode)] =3D cc; } =20 -void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) +void helper_xsrqpi(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t ex =3D Rc(opcode); @@ -3336,10 +3332,9 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) do_float_check_status(env, GETPC()); } =20 -void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) +void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; uint8_t r =3D Rrm(opcode); uint8_t rmc =3D RMC(opcode); @@ -3391,10 +3386,9 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcod= e) do_float_check_status(env, GETPC()); } =20 -void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) +void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xt, ppc_vsr_t *xb) { - ppc_vsr_t *xt =3D &env->vsr[rD(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; ppc_vsr_t t =3D { }; float_status tstat; =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 9134da9cbb..2e0646f5eb 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -402,16 +402,16 @@ DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) -DEF_HELPER_2(xscvdpqp, void, env, i32) +DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpspn, i64, env, i64) DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xscvqpsdz, void, env, i32) -DEF_HELPER_2(xscvqpswz, void, env, i32) -DEF_HELPER_2(xscvqpudz, void, env, i32) -DEF_HELPER_2(xscvqpuwz, void, env, i32) +DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr) -DEF_HELPER_2(xscvsdqp, void, env, i32) +DEF_HELPER_4(xscvsdqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvspdp, void, env, vsr, vsr) DEF_HELPER_2(xscvspdpn, i64, env, i64) DEF_HELPER_3(xscvdpsxds, void, env, vsr, vsr) @@ -421,7 +421,7 @@ DEF_HELPER_3(xscvdpuxws, void, env, vsr, vsr) DEF_HELPER_3(xscvsxddp, void, env, vsr, vsr) DEF_HELPER_3(xscvuxdsp, void, env, vsr, vsr) DEF_HELPER_3(xscvsxdsp, void, env, vsr, vsr) -DEF_HELPER_2(xscvudqp, void, env, i32) +DEF_HELPER_4(xscvudqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvuxddp, void, env, vsr, vsr) DEF_HELPER_3(xststdcsp, void, env, i32, vsr) DEF_HELPER_2(xststdcdp, void, env, i32) @@ -431,9 +431,9 @@ DEF_HELPER_3(xsrdpic, void, env, vsr, vsr) DEF_HELPER_3(xsrdpim, void, env, vsr, vsr) DEF_HELPER_3(xsrdpip, void, env, vsr, vsr) DEF_HELPER_3(xsrdpiz, void, env, vsr, vsr) -DEF_HELPER_2(xsrqpi, void, env, i32) -DEF_HELPER_2(xsrqpxp, void, env, i32) -DEF_HELPER_2(xssqrtqp, void, env, i32) +DEF_HELPER_4(xsrqpi, void, env, i32, vsr, vsr) +DEF_HELPER_4(xsrqpxp, void, env, i32, vsr, vsr) +DEF_HELPER_4(xssqrtqp, void, env, i32, vsr, vsr) DEF_HELPER_5(xssubqp, void, env, i32, vsr, vsr, vsr) =20 DEF_HELPER_4(xsaddsp, void, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 1aa6e04e39..0dd78546d7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1114,6 +1114,24 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xt, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ + xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ + gen_helper_##name(cpu_env, opc, xt, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1170,14 +1188,14 @@ GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA= 300) GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) -GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) @@ -1185,7 +1203,7 @@ GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) @@ -1194,9 +1212,9 @@ GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) =20 -GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) +GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) =20 GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559476227; cv=none; d=zoho.com; s=zohoarc; b=kAnn5V1Eumel3YCgpe41wFk3kFDHhgTBdjHWJmgUuDu4pkRpzcTJhvmSdbt9OHevkEeX7qibeEmXobFXL4nZiM/rFtass0QC3erLKsBUZzLm1P+qOQ2XkZGoArksG9c1bFLJo7kBlwhEwp+3Dze2nRNRIa/1I7vVqVT/s4MV038= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559476227; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=DGr2L4Dnk5OaYLatHv9sjDsR5jJStA4ZMGYcvytAM9I=; b=naJxtYQRG7S2eF33pFC34LNZslGco3pl67jXBrLPGpgQQbqPdZLuUzm5kAGLiEFcHxzakfWLXYrufyEmC7h7V5Db8ZpLDe+l9vJdwOj0Cu6/Bu/9p3naEYKfX5LZLuOLAng7fyp7Z72onwxN9mJdahWe8HAn2Nz31ThWUIH7oOU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559476227853918.2698685591391; Sun, 2 Jun 2019 04:50:27 -0700 (PDT) Received: from localhost ([127.0.0.1]:48039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXP0B-0001UB-R7 for importer@patchew.org; Sun, 02 Jun 2019 07:50:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtI-0004pJ-DC for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOlH-0007i7-SU for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:34:53 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51518 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOlH-0007hT-Ml; Sun, 02 Jun 2019 07:34:51 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLi-0008A4-Tb; Sun, 02 Jun 2019 12:08:28 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:09:00 +0100 Message-Id: <20190602110903.3431-13-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 12/15] target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based upon rA and rB at translation time. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 10 ++++------ target/ppc/helper.h | 6 +++--- target/ppc/translate/vsx-impl.inc.c | 24 +++++++++++++++++++++--- 3 files changed, 28 insertions(+), 12 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ba52ef597e..350505e420 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2452,10 +2452,9 @@ void helper_xscmpexpdp(CPUPPCState *env, uint32_t op= code, do_float_check_status(env, GETPC()); } =20 -void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode) +void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode, + ppc_vsr_t *xa, ppc_vsr_t *xb) { - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; int64_t exp_a, exp_b; uint32_t cc; =20 @@ -2531,10 +2530,9 @@ VSX_SCALAR_CMP(xscmpodp, 1) VSX_SCALAR_CMP(xscmpudp, 0) =20 #define VSX_SCALAR_CMPQ(op, ordered) \ -void helper_##op(CPUPPCState *env, uint32_t opcode) \ +void helper_##op(CPUPPCState *env, uint32_t opcode, \ + ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ - ppc_vsr_t *xa =3D &env->vsr[rA(opcode) + 32]; \ - ppc_vsr_t *xb =3D &env->vsr[rB(opcode) + 32]; \ uint32_t cc =3D 0; \ bool vxsnan_flag =3D false, vxvc_flag =3D false; = \ \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 2e0646f5eb..a5e12a3933 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -390,11 +390,11 @@ DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xscmpexpqp, void, env, i32) +DEF_HELPER_4(xscmpexpqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr) DEF_HELPER_4(xscmpudp, void, env, i32, vsr, vsr) -DEF_HELPER_2(xscmpoqp, void, env, i32) -DEF_HELPER_2(xscmpuqp, void, env, i32) +DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr) +DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 0dd78546d7..e05756b8c1 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1132,6 +1132,24 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_ptr(xb); = \ } =20 +#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_i32 opc; = \ + TCGv_ptr xa, xb; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + opc =3D tcg_const_i32(ctx->opcode); = \ + xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ + xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ + gen_helper_##name(cpu_env, opc, xa, xb); = \ + tcg_temp_free_i32(opc); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(xb); = \ +} + #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -1175,11 +1193,11 @@ GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_IS= A300) GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559476064; cv=none; d=zoho.com; s=zohoarc; b=QxNCVKW2S4Itbzkl3CKO7NrSWUrMUba+LzlPqcLFr4yC8rrcWTTbHn3eKvRvgTKNXjXu5s4jnw3iOVDwUtkT4LU4hiymCqriXvmcj7kvgmdUWuUpfHfEzT4ToGm+XV7WUQGQZC1E4XCaVxdidY/YVuJNuzYbtkMCSny/GJDq93Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559476064; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=E7p5STJmYYRt61xSHl0hegAc2wmwQwvR41bbKrxG7wQ=; b=RJtzFB7nj6wnBmwU9/2BZ/Iu+tcIjqvfEBf0ug/EMFfgBkEl0n43R4H4Vxeq0rZ5EKoY3lDswyoq339PZDl/NDKCMKu2SDjbjjTIU9q5jUndFW1sBjMbrsMPqJLiMRLqc9etorYRH9Z6y1LvnUddpPKemMYS2TNJKxo1cL4ZN9w= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559476064386537.975881706049; Sun, 2 Jun 2019 04:47:44 -0700 (PDT) Received: from localhost ([127.0.0.1]:48015 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOxd-0008DR-A9 for importer@patchew.org; Sun, 02 Jun 2019 07:47:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtD-0004pU-9d for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOlx-0008Jc-EB for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:35:34 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51550 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOlv-0008Hl-H7; Sun, 02 Jun 2019 07:35:33 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLk-0008A4-Qj; Sun, 02 Jun 2019 12:08:29 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:09:01 +0100 Message-Id: <20190602110903.3431-14-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 13/15] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/helper.h | 8 +++---- target/ppc/mem_helper.c | 6 ++--- target/ppc/translate/vsx-impl.inc.c | 47 +++++++++++++++++++--------------= ---- 3 files changed, 30 insertions(+), 31 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a5e12a3933..7ed9effff2 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -279,10 +279,10 @@ DEF_HELPER_3(stvebx, void, env, avr, tl) DEF_HELPER_3(stvehx, void, env, avr, tl) DEF_HELPER_3(stvewx, void, env, avr, tl) #if defined(TARGET_PPC64) -DEF_HELPER_4(lxvl, void, env, tl, tl, tl) -DEF_HELPER_4(lxvll, void, env, tl, tl, tl) -DEF_HELPER_4(stxvl, void, env, tl, tl, tl) -DEF_HELPER_4(stxvll, void, env, tl, tl, tl) +DEF_HELPER_4(lxvl, void, env, tl, vsr, tl) +DEF_HELPER_4(lxvll, void, env, tl, vsr, tl) +DEF_HELPER_4(stxvl, void, env, tl, vsr, tl) +DEF_HELPER_4(stxvll, void, env, tl, vsr, tl) #endif DEF_HELPER_4(vsumsws, void, env, avr, avr, avr) DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 17a3c931a9..c533f88dc1 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -415,9 +415,8 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32) =20 #define VSX_LXVL(name, lj) \ void helper_##name(CPUPPCState *env, target_ulong addr, \ - target_ulong xt_num, target_ulong rb) \ + ppc_vsr_t *xt, target_ulong rb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xt_num]; \ ppc_vsr_t t; \ uint64_t nb =3D GET_NB(rb); \ int i; \ @@ -446,9 +445,8 @@ VSX_LXVL(lxvll, 1) =20 #define VSX_STXVL(name, lj) \ void helper_##name(CPUPPCState *env, target_ulong addr, \ - target_ulong xt_num, target_ulong rb) \ + ppc_vsr_t *xt, target_ulong rb) \ { \ - ppc_vsr_t *xt =3D &env->vsr[xt_num]; \ ppc_vsr_t t =3D *xt; \ target_ulong nb =3D GET_NB(rb); \ int i; \ diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index e05756b8c1..931c7c33ac 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -343,29 +343,30 @@ VSX_VECTOR_STORE(stxv, st_i64, 0) VSX_VECTOR_STORE(stxvx, st_i64, 1) =20 #ifdef TARGET_PPC64 -#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA, xt; \ - \ - if (xT(ctx->opcode) < 32) { \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - EA =3D tcg_temp_new(); \ - xt =3D tcg_const_tl(xT(ctx->opcode)); \ - gen_set_access_type(ctx, ACCESS_INT); \ - gen_addr_register(ctx, EA); \ - gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ - tcg_temp_free(EA); \ - tcg_temp_free(xt); \ +#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_ptr xt; \ + \ + if (xT(ctx->opcode) < 32) { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + } else { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + } \ + EA =3D tcg_temp_new(); \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); \ + gen_set_access_type(ctx, ACCESS_INT); \ + gen_addr_register(ctx, EA); \ + gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(xt); \ } =20 VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559476067; cv=none; d=zoho.com; s=zohoarc; b=Uqjy9oAWYDkes3RjBGwOCL5nbwqEK8UR129XR6VFgxiSSj9PIYRu1ODtxzrEm8ZPf+VTao3DMD2XbXSmZwWqz7soDl+ZdNc+JrZlv460qPBHYauPL0bNN1/kwAA9YhvFlhNF0AoVOW+Q6gqFM9UbcpaAC4RsW19OavPbpIInrsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559476067; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NxK/YIUxIxYN5/b66LJaoZq38vlbVYsQcK5y3PnQwG0=; b=gfAcaHTfKQ3Nr1mJTBloKskcIaB641ihnuGU7IhKgkdSdNjY6T5KjZ7R+gP6nqwfY60KONf/LIGDlXCqfyiNlL6UNz5ZYeo4Qme0kzX60qDDO7RLdXyK3MLpxlCjP9aGLwrDcNie97+ytpfKNrmwiH8etD7eJj87eLCSTcYTvuA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155947606741440.46529563944557; Sun, 2 Jun 2019 04:47:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:48017 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOxg-0008G1-DQ for importer@patchew.org; Sun, 02 Jun 2019 07:47:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtH-0004vL-Tm for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOlT-0007rk-0L for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:35:04 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51526 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOlS-0007rH-Q8; Sun, 02 Jun 2019 07:35:02 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLl-0008A4-Dp; Sun, 02 Jun 2019 12:08:29 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:09:02 +0100 Message-Id: <20190602110903.3431-15-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 14/15] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/helper.h | 4 ++-- target/ppc/int_helper.c | 12 ++++-------- target/ppc/translate/vsx-impl.inc.c | 10 +++++----- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7ed9effff2..3d5150a524 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -534,8 +534,8 @@ DEF_HELPER_3(xvrspip, void, env, vsr, vsr) DEF_HELPER_3(xvrspiz, void, env, vsr, vsr) DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr) DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32) -DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32) +DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32) +DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32) DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr) =20 DEF_HELPER_2(efscfsi, i32, env, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 3b8939edcc..5c07ef3e4d 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1899,11 +1899,9 @@ VEXTRACT(uw, u32) VEXTRACT(d, u64) #undef VEXTRACT =20 -void helper_xxextractuw(CPUPPCState *env, target_ulong xtn, - target_ulong xbn, uint32_t index) +void helper_xxextractuw(CPUPPCState *env, ppc_vsr_t *xt, + ppc_vsr_t *xb, uint32_t index) { - ppc_vsr_t *xt =3D &env->vsr[xtn]; - ppc_vsr_t *xb =3D &env->vsr[xbn]; ppc_vsr_t t =3D { }; size_t es =3D sizeof(uint32_t); uint32_t ext_index; @@ -1917,11 +1915,9 @@ void helper_xxextractuw(CPUPPCState *env, target_ulo= ng xtn, *xt =3D t; } =20 -void helper_xxinsertw(CPUPPCState *env, target_ulong xtn, - target_ulong xbn, uint32_t index) +void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt, + ppc_vsr_t *xb, uint32_t index) { - ppc_vsr_t *xt =3D &env->vsr[xtn]; - ppc_vsr_t *xb =3D &env->vsr[xbn]; ppc_vsr_t t =3D *xt; size_t es =3D sizeof(uint32_t); int ins_index, i =3D 0; diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 931c7c33ac..b3bb1746ee 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1651,7 +1651,7 @@ static void gen_xxsldwi(DisasContext *ctx) #define VSX_EXTRACT_INSERT(name) \ static void gen_##name(DisasContext *ctx) \ { \ - TCGv xt, xb; \ + TCGv_ptr xt, xb; \ TCGv_i32 t0; \ TCGv_i64 t1; \ uint8_t uimm =3D UIMM4(ctx->opcode); \ @@ -1660,8 +1660,8 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - xt =3D tcg_const_tl(xT(ctx->opcode)); \ - xb =3D tcg_const_tl(xB(ctx->opcode)); \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); \ + xb =3D gen_vsr_ptr(xB(ctx->opcode)); \ t0 =3D tcg_temp_new_i32(); \ t1 =3D tcg_temp_new_i64(); \ /* \ @@ -1676,8 +1676,8 @@ static void gen_##name(DisasContext *ctx) = \ } \ tcg_gen_movi_i32(t0, uimm); \ gen_helper_##name(cpu_env, xt, xb, t0); \ - tcg_temp_free(xb); \ - tcg_temp_free(xt); \ + tcg_temp_free_ptr(xb); \ + tcg_temp_free_ptr(xt); \ tcg_temp_free_i32(t0); \ tcg_temp_free_i64(t1); \ } --=20 2.11.0 From nobody Thu May 9 06:43:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559476074; cv=none; d=zoho.com; s=zohoarc; b=LY7cP5U5JETbxDgWajtAlg605Uzix6yrnbZu4HHbYE1JC+fb7tAjWaEkgURyyTBinmZbh+9LB7677EmW9Q922rxmoKupHqZgbrQWHT+5IEhsdd20RJ0bsaREIIaWrR3oYuiAxlWB7VZRcUUHApaAL78VYwq2ChvkkRfTbnGXJzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559476074; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YaOMZiR18VBar1Ol0HvZHZJ19vDoflHLkZ3Qb9HzqwI=; b=A5I7u9kVpOIL5CJcQzH611ShwZT/Xragq7ZjaQk6qCyrbxcEVVV31bq68LUZ7Az0IyRJoTmG7XzEuj2Enuths1jNSdUPiXGSkYHMYKAVntGAUovPmhOepxxF1q7MW0ceUvJrPGE5/OiLjgL52MKUMVgWaB2MPqFNI4pqbAR7PZY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559476074570397.32888927876024; Sun, 2 Jun 2019 04:47:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:48019 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOxq-0008KS-Pf for importer@patchew.org; Sun, 02 Jun 2019 07:47:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hXOtK-0004pU-CB for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:43:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hXOj9-0005e7-4t for qemu-devel@nongnu.org; Sun, 02 Jun 2019 07:32:41 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:51506 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hXOj8-0005cv-SJ; Sun, 02 Jun 2019 07:32:39 -0400 Received: from host81-158-188-206.range81-158.btcentralplus.com ([81.158.188.206] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hXOLl-0008A4-WB; Sun, 02 Jun 2019 12:08:31 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 2 Jun 2019 12:09:03 +0100 Message-Id: <20190602110903.3431-16-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> References: <20190602110903.3431-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 81.158.188.206 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2 15/15] target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Introduce a new GEN_VSX_HELPER_VSX_MADD macro for the generator function wh= ich enables the source and destination registers to be decoded at translation t= ime. This enables the determination of a or m form to be made at translation tim= e so that a single helper function can now be used for both variants. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 68 ++++++++++--------------------- target/ppc/helper.h | 48 ++++++++-------------- target/ppc/translate/vsx-impl.inc.c | 81 +++++++++++++++++++++------------= ---- target/ppc/translate/vsx-ops.inc.c | 70 +++++++++++++++++--------------- 4 files changed, 122 insertions(+), 145 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 350505e420..f13855d324 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2280,24 +2280,15 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) * fld - vsr_t field (VsrD(*) or VsrW(*)) * maddflgs - flags for the float*muladd routine that control the * various forms (madd, msub, nmadd, nmsub) - * afrm - A form (1=3DA, 0=3DM) * sfprf - set FPRF */ -#define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) = \ +#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) = \ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ - ppc_vsr_t *xa, ppc_vsr_t *xb) = \ + ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) = \ { = \ - ppc_vsr_t t =3D *xt, *b, *c; = \ + ppc_vsr_t t =3D *xt; = \ int i; = \ = \ - if (afrm) { /* AxB + T */ = \ - b =3D xb; = \ - c =3D xt; = \ - } else { /* AxT + B */ = \ - b =3D xt; = \ - c =3D xb; = \ - } = \ - = \ helper_reset_fpstatus(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ @@ -2336,41 +2327,24 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ do_float_check_status(env, GETPC()); = \ } =20 -VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0) -VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0) -VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0) -VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0) -VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0) -VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0) -VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0) -VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0) - -VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1) -VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1) -VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1) -VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1) -VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1) -VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1) -VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1) -VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1) - -VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0) -VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0) -VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0) -VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0) -VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0) -VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0) -VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0) -VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0) - -VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0) -VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0) -VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0) -VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0) -VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0) -VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0) -VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0) -VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0) +VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0) +VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0) +VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0) +VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0) +VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1) +VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1) +VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1) +VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1) + +VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0) +VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0) +VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0) +VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0) + +VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0) +VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0) +VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0) +VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0) =20 /* * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3d5150a524..380c9b1e2a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -377,14 +377,10 @@ DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr) DEF_HELPER_3(xstsqrtdp, void, env, i32, vsr) -DEF_HELPER_4(xsmaddadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmaddmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmsubadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmsubmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmaddadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmaddmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmsubadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_5(xsmadddp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsmsubdp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsnmadddp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsnmsubdp, void, env, vsr, vsr, vsr, vsr) DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr) @@ -444,14 +440,10 @@ DEF_HELPER_3(xsresp, void, env, vsr, vsr) DEF_HELPER_2(xsrsp, i64, env, i64) DEF_HELPER_3(xssqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xsrsqrtesp, void, env, vsr, vsr) -DEF_HELPER_4(xsmaddasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmaddmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmsubasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsmsubmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmaddasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmaddmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmsubasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xsnmsubmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_5(xsmaddsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsmsubsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsnmaddsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xsnmsubsp, void, env, vsr, vsr, vsr, vsr) =20 DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr) @@ -462,14 +454,10 @@ DEF_HELPER_3(xvsqrtdp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtedp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivdp, void, env, i32, vsr, vsr) DEF_HELPER_3(xvtsqrtdp, void, env, i32, vsr) -DEF_HELPER_4(xvmaddadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmaddmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmsubadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmsubmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmaddadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmaddmdp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmsubadp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmsubmdp, void, env, vsr, vsr, vsr) +DEF_HELPER_5(xvmadddp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvmsubdp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvnmadddp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvnmsubdp, void, env, vsr, vsr, vsr, vsr) DEF_HELPER_4(xvmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvmindp, void, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpeqdp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) @@ -500,14 +488,10 @@ DEF_HELPER_3(xvsqrtsp, void, env, vsr, vsr) DEF_HELPER_3(xvrsqrtesp, void, env, vsr, vsr) DEF_HELPER_4(xvtdivsp, void, env, i32, vsr, vsr) DEF_HELPER_3(xvtsqrtsp, void, env, i32, vsr) -DEF_HELPER_4(xvmaddasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmaddmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmsubasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvmsubmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmaddasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmaddmsp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmsubasp, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xvnmsubmsp, void, env, vsr, vsr, vsr) +DEF_HELPER_5(xvmaddsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvmsubsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvnmaddsp, void, env, vsr, vsr, vsr, vsr) +DEF_HELPER_5(xvnmsubsp, void, env, vsr, vsr, vsr, vsr) DEF_HELPER_4(xvmaxsp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xvminsp, void, env, vsr, vsr, vsr) DEF_HELPER_FLAGS_4(xvcmpeqsp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index b3bb1746ee..0b9dcfc718 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1181,14 +1181,6 @@ GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) @@ -1230,12 +1222,10 @@ GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) - GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) - GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) @@ -1243,14 +1233,6 @@ GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX20= 7) GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) @@ -1266,14 +1248,6 @@ GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) @@ -1300,14 +1274,6 @@ GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) @@ -1331,6 +1297,53 @@ GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) =20 +#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) = \ +static void gen_##name(DisasContext *ctx) = \ +{ = \ + TCGv_ptr xt, xa, b, c; = \ + if (unlikely(!ctx->vsx_enabled)) { = \ + gen_exception(ctx, POWERPC_EXCP_VSXU); = \ + return; = \ + } = \ + xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ + if (ctx->opcode & PPC_BIT(25)) { = \ + /* = \ + * AxT + B = \ + */ = \ + b =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + c =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + } else { = \ + /* = \ + * AxB + T = \ + */ = \ + b =3D gen_vsr_ptr(xB(ctx->opcode)); = \ + c =3D gen_vsr_ptr(xT(ctx->opcode)); = \ + } = \ + gen_helper_##name(cpu_env, xt, xa, b, c); = \ + tcg_temp_free_ptr(xt); = \ + tcg_temp_free_ptr(xa); = \ + tcg_temp_free_ptr(b); = \ + tcg_temp_free_ptr(c); = \ +} + +GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX) + static void gen_xxbrd(DisasContext *ctx) { TCGv_i64 xth; diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-= ops.inc.c index 5030c4aceb..7fd3942b84 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -63,6 +63,12 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC= _NONE, fl2), \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) =20 +#define GEN_XX3FORM_NAME(name, opcname, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) + #define GEN_XX2IFORM(name, opc2, opc3, fl2) \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \ @@ -182,14 +188,14 @@ GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), -GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX), -GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX), -GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX), -GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX), -GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX), -GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX), -GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX), -GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX), +GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX), +GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX), +GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX), +GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX), GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300), GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300), GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300), @@ -235,14 +241,14 @@ GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), -GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207), -GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207), -GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207), -GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207), -GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207), -GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207), -GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207), -GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207), GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), =20 @@ -255,14 +261,14 @@ GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), -GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX), -GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX), -GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX), -GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX), -GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX), -GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX), -GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX), -GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX), +GEN_XX3FORM_NAME(xvmadddp, "xvmaddadp", 0x04, 0x0C, PPC2_VSX), +GEN_XX3FORM_NAME(xvmadddp, "xvmaddmdp", 0x04, 0x0D, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubdp, "xvmsubadp", 0x04, 0x0E, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubdp, "xvmsubmdp", 0x04, 0x0F, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddadp", 0x04, 0x1C, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddmdp", 0x04, 0x1D, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubadp", 0x04, 0x1E, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubmdp", 0x04, 0x1F, PPC2_VSX), GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), @@ -293,14 +299,14 @@ GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), -GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX), -GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX), -GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX), -GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX), -GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX), -GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX), -GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX), -GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX), +GEN_XX3FORM_NAME(xvmaddsp, "xvmaddasp", 0x04, 0x08, PPC2_VSX), +GEN_XX3FORM_NAME(xvmaddsp, "xvmaddmsp", 0x04, 0x09, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubsp, "xvmsubasp", 0x04, 0x0A, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubsp, "xvmsubmsp", 0x04, 0x0B, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddasp", 0x04, 0x18, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddmsp", 0x04, 0x19, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubasp", 0x04, 0x1A, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubmsp", 0x04, 0x1B, PPC2_VSX), GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), --=20 2.11.0