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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id r23sm2391176otg.49.2019.05.31.06.43.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 May 2019 06:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gyvqL6c4/oaHwFa3XHYMgL2lVq/nblv9jYZvWQQxxMs=; b=KAa4Nw2AriMhrKHg3Q/NJriL9L9fpRqjo11Qni7wcBSo0/Z84ulhexsjd2QiF9rEgO 92lnJN0VaFBunOu4snm75LsvJLB/yOKC4JzEaM+CXmuw1hxenrTImEknBTAIvbvz3D85 kkRi91Q3D5tdKanE1SIWFv4isE85Itoury2ZTtiCv/N0e7CGDRRpBvza2wP3or8IS3xT /w+3XQO15y/OYe9t36M8U2zpvTJnR0JgnUfPDfG2k0i/6zkqlBMaXOC/+53QaARMauI3 uYNt4/nG9YlcCch94rlDo36eXSjSRS/VSu7XKTHqfyZJIm7QQwTKjHoXiC3CXZB5DdWk MIJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gyvqL6c4/oaHwFa3XHYMgL2lVq/nblv9jYZvWQQxxMs=; b=J5pjBk74cSn2v5+LCNkAJWUcGxbERq3QE/pdkFIsymK/ZmIs4WFYpLF6Pet8dQ8jY2 O2/yK+sEqzEj7HyxMtdxWmIxiBi3tj6Cy76r3v8SKYvts6uGy3yKdfNapEKns9vPKTHP 7Y9nkG/4VPXeyiuucFcbe+cApKa8t0NkF6l/fVyg1bv/8yuUedx9lA3gWFjzyfpCCVbf hPgl2VPK7h+YU8wLrNnTEbxDwwosHe51YDubD3ha+PinSTEmiswtA6Kx+1h694eVM9Av uIaf/lyoBczf6gJWPwdJNWivA69587ke6ad9GvwlhCx2YknzP8ImdEUwA+WztS7aJ2Ax JvDg== X-Gm-Message-State: APjAAAW8Y5GWsGh5eV01s+EDDpvWF9KmI/CYmfk7BGWno9ZC7DkHa1Qb S7G83DF8gq3jS13lszPQkwmlRULuRE6H2Q== X-Google-Smtp-Source: APXvYqx57xT4HbczMW68A5RQFqgWbHDpV0B0t5Lo+bTXeknaIK6b2Jv00Xq1vWMUT3IUTLJmK7TXPw== X-Received: by 2002:a9d:480a:: with SMTP id c10mr1836044otf.10.1559310218531; Fri, 31 May 2019 06:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 31 May 2019 08:43:05 -0500 Message-Id: <20190531134315.4109-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190531134315.4109-1-richard.henderson@linaro.org> References: <20190531134315.4109-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v16 13/23] target/rx: Fix cpu types and names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, ysato@users.sourceforge.jp Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There was confusion here about abstract classes and naming cpus. We had registered a concrete class named "-rxcpu". This was put into the default cpu fields, and matched, so basic tests worked. However, no value for -cpu could ever match in rx_cpu_class_by_name. Rename the base class to "rx-cpu" and make it abstract. This matches what we do for most other targets. Create a new concrete cpu with the name "rx62n-rx-cpu". Signed-off-by: Richard Henderson --- target/rx/cpu.h | 12 ++++++------ hw/rx/rx-virt.c | 2 +- hw/rx/rx62n.c | 2 +- target/rx/cpu.c | 43 ++++++++++++++++++++++++++----------------- 4 files changed, 34 insertions(+), 25 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 8c1a4e448d..a0b6975963 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -24,14 +24,14 @@ #include "hw/registerfields.h" #include "qom/cpu.h" =20 -#define TYPE_RXCPU "rxcpu" +#define TYPE_RX_CPU "rx-cpu" =20 #define RXCPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RXCPU) + OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU) #define RXCPU(obj) \ - OBJECT_CHECK(RXCPU, (obj), TYPE_RXCPU) + OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU) #define RXCPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RXCPU) + OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU) =20 /* * RXCPUClass: @@ -164,9 +164,9 @@ static inline RXCPU *rx_env_get_cpu(CPURXState *env) =20 #define ENV_OFFSET offsetof(RXCPU, env) =20 -#define RX_CPU_TYPE_SUFFIX "-" TYPE_RXCPU +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX -#define CPU_RESOLVING_TYPE TYPE_RXCPU +#define CPU_RESOLVING_TYPE TYPE_RX_CPU =20 extern const char rx_crname[][6]; =20 diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c index 3deb7cb335..72a2989fcf 100644 --- a/hw/rx/rx-virt.c +++ b/hw/rx/rx-virt.c @@ -88,7 +88,7 @@ static void rxvirt_class_init(ObjectClass *oc, void *data) mc->desc =3D "RX QEMU Virtual Target"; mc->init =3D rxvirt_init; mc->is_default =3D 1; - mc->default_cpu_type =3D TYPE_RXCPU; + mc->default_cpu_type =3D RX_CPU_TYPE_NAME("rx62n"); } =20 static const TypeInfo rxvirt_type =3D { diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index c6660b75b4..3a8fe7b0bf 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -195,7 +195,7 @@ static void rx62n_realize(DeviceState *dev, Error **err= p) } =20 object_initialize_child(OBJECT(s), "cpu", &s->cpu, - sizeof(RXCPU), TYPE_RXCPU, + sizeof(RXCPU), RX_CPU_TYPE_NAME("rx62n"), errp, NULL); object_property_set_bool(OBJECT(&s->cpu), true, "realized", errp); =20 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 3268077d08..41fe1de4bb 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -74,13 +74,14 @@ static void rx_cpu_list_entry(gpointer data, gpointer u= ser_data) const char *typename =3D object_class_get_name(OBJECT_CLASS(data)); int len =3D strlen(typename) - strlen(RX_CPU_TYPE_SUFFIX); =20 - qemu_printf("%.*s\n", len, typename); + qemu_printf(" %.*s\n", len, typename); } =20 void rx_cpu_list(void) { - GSList *list; - list =3D object_class_get_list_sorted(TYPE_RXCPU, false); + GSList *list =3D object_class_get_list_sorted(TYPE_RX_CPU, false); + + qemu_printf("Available CPUs:\n"); g_slist_foreach(list, rx_cpu_list_entry, NULL); g_slist_free(list); } @@ -88,15 +89,17 @@ void rx_cpu_list(void) static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; - char *typename =3D NULL; + char *typename; =20 - typename =3D g_strdup_printf(RX_CPU_TYPE_NAME("")); + typename =3D g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); oc =3D object_class_by_name(typename); - if (oc !=3D NULL && object_class_is_abstract(oc)) { - oc =3D NULL; - } - g_free(typename); + + if (oc =3D=3D NULL || + object_class_is_abstract(oc) || + !object_class_dynamic_cast(oc, TYPE_RX_CPU)) { + return NULL; + } return oc; } =20 @@ -166,7 +169,7 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 -static void rxcpu_class_init(ObjectClass *klass, void *data) +static void rx_cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); CPUClass *cc =3D CPU_CLASS(klass); @@ -195,22 +198,28 @@ static void rxcpu_class_init(ObjectClass *klass, void= *data) cc->gdb_num_core_regs =3D 26; } =20 -static const TypeInfo rxcpu_info =3D { - .name =3D TYPE_RXCPU, +static const TypeInfo rx_cpu_info =3D { + .name =3D TYPE_RX_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(RXCPU), .instance_init =3D rx_cpu_init, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(RXCPUClass), - .class_init =3D rxcpu_class_init, + .class_init =3D rx_cpu_class_init, }; =20 -static void rxcpu_register_types(void) +static const TypeInfo rx62n_rx_cpu_info =3D { + .name =3D RX_CPU_TYPE_NAME("rx62n"), + .parent =3D TYPE_RX_CPU, +}; + +static void rx_cpu_register_types(void) { - type_register_static(&rxcpu_info); + type_register_static(&rx_cpu_info); + type_register_static(&rx62n_rx_cpu_info); } =20 -type_init(rxcpu_register_types) +type_init(rx_cpu_register_types) =20 static uint32_t extable[32]; =20 --=20 2.17.1