From nobody Wed Feb 11 00:55:26 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1559310973; cv=none; d=zoho.com; s=zohoarc; b=Vq/u3MvsIAV1r2aXHj7ikXB+x6ac/VXN8Q9TJqbVKT5rEipispUAHVYd6PT9y0ecBcGzKUoB4MPUO+vucSheZmHHuwfjJsg+UDnNXRwLdG7KTfLxTYguuz2K06PMJbb6ZY+ZCP8ZwlEJnkd2BMwfioeq81rgTKDEJSEgv6zDe6Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559310973; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1XbDcSxPxIwShmL7ibaMkqeCI/KNLPvufrTgWj8SAo0=; b=ijDdLNjbXL7xMnPm22T3LXRriBW8CEXmLTUu0C5sCGzgutPIWzClzGnKjNZMFKnSFVKBlA7ALOgbK8zi2T0QMzN46pWJnHz5TN51w9OdJZQ7cOS7WTzIf2BIzRPMIToDymfbnnTAeg+q6FeJVePGeoilZnXC0VwjfjRsf+UHtBk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559310973777498.10638413361494; Fri, 31 May 2019 06:56:13 -0700 (PDT) Received: from localhost ([127.0.0.1]:43966 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hWi0u-0008M4-Nw for importer@patchew.org; Fri, 31 May 2019 09:56:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hWhon-0007Tn-F3 for qemu-devel@nongnu.org; Fri, 31 May 2019 09:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hWhom-0000L2-7y for qemu-devel@nongnu.org; Fri, 31 May 2019 09:43:37 -0400 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]:37234) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hWhom-0000JW-1z for qemu-devel@nongnu.org; Fri, 31 May 2019 09:43:36 -0400 Received: by mail-ot1-x343.google.com with SMTP id r10so9216927otd.4 for ; Fri, 31 May 2019 06:43:36 -0700 (PDT) Received: from localhost.localdomain (168.189-204-159.bestelclientes.com.mx. [189.204.159.168]) by smtp.gmail.com with ESMTPSA id r23sm2391176otg.49.2019.05.31.06.43.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 May 2019 06:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1XbDcSxPxIwShmL7ibaMkqeCI/KNLPvufrTgWj8SAo0=; b=DjtHXRHxrYfFzwevW4bKlMnGwULoonBQA7Vt6JPJzAc07Xy8fZ8YG0lT3EqL9cpDHn ZWQ5xV5RBPLTyuuN0buX9LQhI2QwVFkFxXFy59neaUwaqIn+f9QJxfdQwtnlUf2WPcfh /JrgqHhg4tgBhIpcGb5YsPDw0aUZ/3+CbgVNbgYDGu4OVVSBjZARvzD7Ss8V0a0hFObC Ljh2HBA0HbPZDe9TvSHZw/QJaBXBZmuB2V0U4Ir7dGzJ3BLiqaqg8HDDPNM3AynCr1kF FZkie+4SqFROIUFSn8qNZ8+NyAmTrLdH+R6YMtAUpa8IJCnTp8WODNVXvZgEs6Tqy3T7 LsUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1XbDcSxPxIwShmL7ibaMkqeCI/KNLPvufrTgWj8SAo0=; b=aPO3SCStj+GC2yCqSmMNJh3L/3cDowst7wZeYFKqhh4A1oBGYl+hPMhhKNTWzBoLGM W7LWWz8ZZnj8Hsm/wzqArrwRHqgigmhjy+xGHHMIJUHomTj9bBfk2xjV2XOpyLFhA6da 62sKVAjyWoKfmtWpRg+82Rq42X/7DjybxpBHdu+mlM8UB3Zy0FEttGxgVuwXlwN5HFq+ gWbz+GU9QNtl+ujDjhusyRce7J5rvgeR3kxa+dEmYMoxZBPHP3VEpnderRQkSBIpqBsQ 4amsTjK7Cfyeq801cf+pi8FtQepXVPB9HP1PwywtIQH3opsvJweWasZAX5gUm4lqSt/o SMcQ== X-Gm-Message-State: APjAAAXa20v3znTr3fq5gIBCyBH+KdW4CUDktbB0yg5Fd6Rxxvrd74wP Z/Eo1m90+F7BaYYSoqLXv3GgaaVYqZAn+w== X-Google-Smtp-Source: APXvYqwqaaiFDBOXi1COP9v1gkAfA6VrZWmI/djIrASB0I+0p8WV3556C7KNnIjC0b5xQqQmLw3BIg== X-Received: by 2002:a9d:6e0f:: with SMTP id e15mr2024004otr.0.1559310215125; Fri, 31 May 2019 06:43:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 31 May 2019 08:43:02 -0500 Message-Id: <20190531134315.4109-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190531134315.4109-1-richard.henderson@linaro.org> References: <20190531134315.4109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v16 10/23] hw/registerfields.h: Add 8bit and 16bit register macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, ysato@users.sourceforge.jp Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190516055244.95559-11-ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson --- include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..a0bb0654d6 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,6 +22,14 @@ enum { A_ ## reg =3D (addr) }; = \ enum { R_ ## reg =3D (addr) / 4 }; =20 +#define REG8(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) }; + +#define REG16(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) / 2 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ =20 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LE= NGTH @@ -34,6 +42,12 @@ MAKE_64BIT_MASK(shift, length)}; =20 /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +63,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint8_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint16_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ @@ -57,7 +87,7 @@ d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ R_ ## reg ## _ ## field ## _LENGTH, v.v); \ d; }) -#define FIELD_DP64(storage, reg, field, val) ({ \ +#define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ } v =3D { .v =3D val }; = \ --=20 2.17.1