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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH RFC v20 8/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , Michael Rolnik , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Sarah Harris Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 +++++ arch_init.c | 2 ++ configure | 6 +++++ default-configs/avr-softmmu.mak | 5 +++++ include/disas/dis-asm.h | 6 +++++ include/sysemu/arch_init.h | 1 + qapi/common.json | 2 +- target/avr/Makefile.objs | 40 +++++++++++++++++++++++++++++++++ tests/machine-none-test.c | 1 + 9 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 default-configs/avr-softmmu.mak create mode 100644 target/avr/Makefile.objs diff --git a/MAINTAINERS b/MAINTAINERS index 1f5f8b7a2c..4bad81f974 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -162,6 +162,12 @@ S: Maintained F: hw/arm/smmu* F: include/hw/arm/smmu* =20 +AVR +M: Michael Rolnik +S: Odd Fixes +F: target/avr/ +F: hw/avr/ + CRIS M: Edgar E. Iglesias S: Maintained diff --git a/arch_init.c b/arch_init.c index f4f3f610c8..184cdca6dd 100644 --- a/arch_init.c +++ b/arch_init.c @@ -86,6 +86,8 @@ int graphic_depth =3D 32; #define QEMU_ARCH QEMU_ARCH_UNICORE32 #elif defined(TARGET_XTENSA) #define QEMU_ARCH QEMU_ARCH_XTENSA +#elif defined(TARGET_AVR) +#define QEMU_ARCH QEMU_ARCH_AVR #endif =20 const uint32_t arch_type =3D QEMU_ARCH; diff --git a/configure b/configure index 528b9ff705..933c166b02 100755 --- a/configure +++ b/configure @@ -7484,6 +7484,9 @@ case "$target_name" in target_compiler=3D$cross_cc_aarch64 eval "target_compiler_cflags=3D\$cross_cc_cflags_${target_name}" ;; + avr) + target_compiler=3D$cross_cc_avr + ;; cris) target_compiler=3D$cross_cc_cris ;; @@ -7759,6 +7762,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do disas_config "ARM_A64" fi ;; + avr) + disas_config "AVR" + ;; cris) disas_config "CRIS" ;; diff --git a/default-configs/avr-softmmu.mak b/default-configs/avr-softmmu.= mak new file mode 100644 index 0000000000..d1e1c28118 --- /dev/null +++ b/default-configs/avr-softmmu.mak @@ -0,0 +1,5 @@ +# Default configuration for avr-softmmu + +# Boards: +# +CONFIG_AVR_SAMPLE=3Dy diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 9240ec32c2..a7d230ba66 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -211,6 +211,12 @@ enum bfd_architecture #define bfd_mach_m32r 0 /* backwards compatibility */ bfd_arch_mn10200, /* Matsushita MN10200 */ bfd_arch_mn10300, /* Matsushita MN10300 */ + bfd_arch_avr, /* Atmel AVR microcontrollers. */ +#define bfd_mach_avr1 1 +#define bfd_mach_avr2 2 +#define bfd_mach_avr3 3 +#define bfd_mach_avr4 4 +#define bfd_mach_avr5 5 bfd_arch_cris, /* Axis CRIS */ #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 10cbafe970..aff57bfe61 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -25,6 +25,7 @@ enum { QEMU_ARCH_NIOS2 =3D (1 << 17), QEMU_ARCH_HPPA =3D (1 << 18), QEMU_ARCH_RISCV =3D (1 << 19), + QEMU_ARCH_AVR =3D (1 << 20), }; =20 extern const uint32_t arch_type; diff --git a/qapi/common.json b/qapi/common.json index 99d313ef3b..eeacd0e3c2 100644 --- a/qapi/common.json +++ b/qapi/common.json @@ -187,7 +187,7 @@ # Since: 3.0 ## { 'enum' : 'SysEmuTarget', - 'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32', + 'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm= 32', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64', 'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc', 'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4', diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs new file mode 100644 index 0000000000..9ceddf1fdb --- /dev/null +++ b/target/avr/Makefile.objs @@ -0,0 +1,40 @@ +# +# QEMU AVR CPU +# +# Copyright (c) 2016 Michael Rolnik +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see +# +# + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py +decode32-y =3D $(SRC_PATH)/target/avr/insn32.decode +decode16-y =3D $(SRC_PATH)/target/avr/insn16.decode + +target/avr/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ + "GEN", $(TARGET_DIR)$@) + +target/avr/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<,= \ + "GEN", $(TARGET_DIR)$@) + +target/avr/translate.o: target/avr/decode_insn32.inc.c \ + target/avr/decode_insn16.inc.c + +obj-y +=3D translate.o cpu.o helper.o +obj-y +=3D gdbstub.o +obj-$(CONFIG_SOFTMMU) +=3D machine.o diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 4c6d470798..361927bb76 100644 --- a/tests/machine-none-test.c +++ b/tests/machine-none-test.c @@ -27,6 +27,7 @@ static struct arch2cpu cpus_map[] =3D { /* tested targets list */ { "arm", "cortex-a15" }, { "aarch64", "cortex-a57" }, + { "avr", "avr6" }, { "x86_64", "qemu64,apic-id=3D0" }, { "i386", "qemu32,apic-id=3D0" }, { "alpha", "ev67" }, --=20 2.18.0