From nobody Sun May 5 22:25:41 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559162586; cv=none; d=zoho.com; s=zohoarc; b=BPbnM0et8mfZZ1wE7JA1yAs1Ia2M4UR9DY1ENvFOhxjB8LabnJERSa2GyFaaLp79T15SLhOn5vcViQAGZ3qQ5aypTH3gw34v9R3f4QA5GXL9Siso0BHlknYeQ6ienBkcUBXNtpqXpqIVUl7TMBEFLkNQ43qopvqJxbg8EE2w1ro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559162586; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=80RE6I//gD2gYR0rctF2qVLsvsYc9yppzUaiacmJdRE=; b=eLS1ZJiDAycSc5IjLROrGicXdJ3qfcCsHPiphaZMcg9jjDaMPjsFz01dosO32+3m839lp5Ra7TK/B1bc6YdQQgjLteMzIDlUadzGBQ69FMi8OQDewsKb3dFNn8oPPsWYxvRJPwfLp7YOaEGom0ZvOP4W1T4wXunzybvlLqBzgjg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559162586756349.45327329928966; Wed, 29 May 2019 13:43:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:38744 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hW5PJ-0007M7-AE for importer@patchew.org; Wed, 29 May 2019 16:42:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:55020) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hW5OK-00073A-Va for qemu-devel@nongnu.org; Wed, 29 May 2019 16:41:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hW5OJ-0006Da-RA for qemu-devel@nongnu.org; Wed, 29 May 2019 16:41:44 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hW5OJ-00069q-3M for qemu-devel@nongnu.org; Wed, 29 May 2019 16:41:43 -0400 Received: by mail-pf1-f196.google.com with SMTP id d126so2403660pfd.2 for ; Wed, 29 May 2019 13:41:40 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id x18sm600635pfo.8.2019.05.29.13.41.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 29 May 2019 13:41:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=80RE6I//gD2gYR0rctF2qVLsvsYc9yppzUaiacmJdRE=; b=kg2TO/mMaNsL/q24stpBkdztuLxhjPNvYudzwyZvVQMxqd2xS64wRTtEg+x3NlibLh UmH1TDCT7ayCg4X1PfZR4MTWFTIEX/k76LuzQrHYP26BYVZ4fWGp1aYLPrj/Frvaqt85 FMpIEfl9r1E23Aoh0TgLvl7GSywwAcNud/Xf3VrJAan68xusY9/2wLhdxiNSNlzJsCgv LqA6IU+WWhP6pJqvOzOTA6d4HMyWpW2IQiIbn+xhwaqCLdlGPcKZoLv0D8WmJYYbVx+s iutee4tVC0n5J9f2qXJavZqvYWQXumyNh+XRTjFaERaICjPKWoib5YERTMWEY8s2RMRy Lfuw== X-Gm-Message-State: APjAAAVJraduJyRIuOl0fC6KDQDC13er4ySdD5kuq7x0D7nCinfdXvFy 1VMHXZjmeoewXenOGqPeM8fAqqAEbUA= X-Google-Smtp-Source: APXvYqx3G0/l4zgBQZQ4CYLRplw/Yk2QiR3I7o6HhqzVyOywxPqIwPRZdqALxF3YBn2SdhxIqwC8Ig== X-Received: by 2002:a17:90a:65c2:: with SMTP id i2mr14222559pjs.54.1559162499192; Wed, 29 May 2019 13:41:39 -0700 (PDT) Date: Wed, 29 May 2019 13:41:02 -0700 Message-Id: <20190529204101.26907-1-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.196 Subject: [Qemu-devel] [PATCH] sifive_prci: Read and write PRCI registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nathaniel Graff , Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Nathaniel Graff Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 49 ++++++++++++++++++++++++++++------ include/hw/riscv/sifive_prci.h | 32 ++++++++++++++++++++++ 2 files changed, 73 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index 0910ea32c1a5..d3716a928568 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -23,15 +23,18 @@ #include "target/riscv/cpu.h" #include "hw/riscv/sifive_prci.h" =20 -/* currently implements enough to mock freedom-e-sdk BSP clock programming= */ - static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int s= ize) { - if (addr =3D=3D 0 /* PRCI_HFROSCCFG */) { - return 1 << 31; /* ROSC_RDY */ - } - if (addr =3D=3D 8 /* PRCI_PLLCFG */) { - return 1 << 31; /* PLL_LOCK */ + SiFivePRCIState *s =3D opaque; + switch (addr) { + case SIFIVE_PRCI_HFROSCCFG: + return s->hfrosccfg; + case SIFIVE_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_PRCI_PLLCFG: + return s->pllcfg; + case SIFIVE_PRCI_PLLOUTDIV: + return s->plloutdiv; } hw_error("%s: read: addr=3D0x%x\n", __func__, (int)addr); return 0; @@ -40,7 +43,30 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr ad= dr, unsigned int size) static void sifive_prci_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { - /* discard writes */ + SiFivePRCIState *s =3D opaque; + switch (addr) { + case SIFIVE_PRCI_HFROSCCFG: + s->hfrosccfg =3D (uint32_t) val64; + /* OSC stays ready */ + s->hfrosccfg |=3D SIFIVE_PRCI_HFROSCCFG_RDY; + break; + case SIFIVE_PRCI_HFXOSCCFG: + s->hfxosccfg =3D (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |=3D SIFIVE_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_PRCI_PLLCFG: + s->pllcfg =3D (uint32_t) val64; + /* PLL stays locked */ + s->pllcfg |=3D SIFIVE_PRCI_PLLCFG_LOCK; + break; + case SIFIVE_PRCI_PLLOUTDIV: + s->plloutdiv =3D (uint32_t) val64; + break; + default: + hw_error("%s: bad write: addr=3D0x%x v=3D0x%x\n", + __func__, (int)addr, (int)val64); + } } =20 static const MemoryRegionOps sifive_prci_ops =3D { @@ -60,6 +86,13 @@ static void sifive_prci_init(Object *obj) memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, TYPE_SIFIVE_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->hfrosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); + s->hfxosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); + s->pllcfg =3D (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | + SIFIVE_PRCI_PLLCFG_LOCK); + s->plloutdiv =3D SIFIVE_PRCI_PLLOUTDIV_DIV1; + } =20 static const TypeInfo sifive_prci_info =3D { diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h index b6f4c486cc1e..bd51c4af3c1c 100644 --- a/include/hw/riscv/sifive_prci.h +++ b/include/hw/riscv/sifive_prci.h @@ -19,6 +19,34 @@ #ifndef HW_SIFIVE_PRCI_H #define HW_SIFIVE_PRCI_H =20 +enum { + SIFIVE_PRCI_HFROSCCFG =3D 0x0, + SIFIVE_PRCI_HFXOSCCFG =3D 0x4, + SIFIVE_PRCI_PLLCFG =3D 0x8, + SIFIVE_PRCI_PLLOUTDIV =3D 0xC +}; + +enum { + SIFIVE_PRCI_HFROSCCFG_RDY =3D (1 << 31), + SIFIVE_PRCI_HFROSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_PRCI_HFXOSCCFG_RDY =3D (1 << 31), + SIFIVE_PRCI_HFXOSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_PRCI_PLLCFG_PLLSEL =3D (1 << 16), + SIFIVE_PRCI_PLLCFG_REFSEL =3D (1 << 17), + SIFIVE_PRCI_PLLCFG_BYPASS =3D (1 << 18), + SIFIVE_PRCI_PLLCFG_LOCK =3D (1 << 31) +}; + +enum { + SIFIVE_PRCI_PLLOUTDIV_DIV1 =3D (1 << 8) +}; + #define TYPE_SIFIVE_PRCI "riscv.sifive.prci" =20 #define SIFIVE_PRCI(obj) \ @@ -30,6 +58,10 @@ typedef struct SiFivePRCIState { =20 /*< public >*/ MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; } SiFivePRCIState; =20 DeviceState *sifive_prci_create(hwaddr addr); --=20 2.21.0