From nobody Mon Feb 9 17:59:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559113595; cv=none; d=zoho.com; s=zohoarc; b=fbRbiPB2h9SqVT/SXJiBVRRLvt3Pk3JNtc6tgoi/JFeghTh4zSpdiB3JLxWS/bQn4UwjPApb6dEFD/8TH+2VG3cp70udVH6SGtCx9OgL2TaC9Kxm46u1WEX9TbZsBocMdykbY6WILoEUYmS0idmKOdfzQzdI0UFk9E7+IEdJMjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559113595; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8UM/t40g+9v4tfu2A18Ady40JuZBcJ0ALDo2FPGDC88=; b=hebutMVJO5Hx2GMMiMFQz1d2euTJfU+oy/uPdceWoVozBUCg5zKMDlA7K0TJ9h5aYuHsNQ9if8pE3PfeoZVjQP6/gzY+FNtw71EVq+w1eXrANGB0F23IAohLpyEC1/hA27N79vVlBqUGfvziu15m/ururNUQmeUPiN0hQ1+xQMA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559113595016668.7979953842301; Wed, 29 May 2019 00:06:35 -0700 (PDT) Received: from localhost ([127.0.0.1]:48601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVsfI-0004SA-Sm for importer@patchew.org; Wed, 29 May 2019 03:06:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48083) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVsQR-0000LH-4r for qemu-devel@nongnu.org; Wed, 29 May 2019 02:51:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hVsQQ-0002qN-0K for qemu-devel@nongnu.org; Wed, 29 May 2019 02:51:03 -0400 Received: from ozlabs.org ([203.11.71.1]:48803) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hVsQP-0002cT-EF; Wed, 29 May 2019 02:51:01 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 45DLv56MGpz9sPP; Wed, 29 May 2019 16:50:22 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1559112625; bh=h2GmXgrQc1s9kQJu5WILh6Hn0igXNXT6J623+KGV/t0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D0/dHS4WzUXyIdnq9r/3YES3Nf8fQ9ZEC7Ns5KNAXxOGfXU1k3T790umzf1MWVKpt rlcBGTobYkw2bubRZw/7ahlw2BiY3sKMgPrjQ6K1MsPQoi6B2WzQJObvkStlqoWO/r F+Tlf6WUISXhHNERPRDeSqVUQmyLJF2NV275aMbM= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 29 May 2019 16:49:51 +1000 Message-Id: <20190529065017.15149-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190529065017.15149-1-david@gibson.dropbear.id.au> References: <20190529065017.15149-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 18/44] target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Mark Cave-Ayland , qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson , Anton Blanchard , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Anton Blanchard A few small optimisations: In VSX_LOAD_SCALAR_DS() we can don't need to read the VSR via get_cpu_vsrh(). Split VSX_VECTOR_LOAD_STORE() into two functions. Loads only need to write the VSRs (set_cpu_vsr*()) and stores only need to read the VSRs (get_cpu_vsr*()) Thanks to Mark Cave-Ayland for the suggestions. Signed-off-by: Anton Blanchard Message-Id: <20190509103545.4a7fa71a@kryten> Reviewed-by: Mark Cave-Ayland Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 68 ++++++++++++++++++++++++----- 1 file changed, 58 insertions(+), 10 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 4b8f6cefe3..c39829cf33 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -227,7 +227,7 @@ static void gen_lxvb16x(DisasContext *ctx) tcg_temp_free_i64(xtl); } =20 -#define VSX_VECTOR_LOAD_STORE(name, op, indexed) \ +#define VSX_VECTOR_LOAD(name, op, indexed) \ static void gen_##name(DisasContext *ctx) \ { \ int xt; \ @@ -254,8 +254,6 @@ static void gen_##name(DisasContext *ctx) = \ } \ xth =3D tcg_temp_new_i64(); \ xtl =3D tcg_temp_new_i64(); \ - get_cpu_vsrh(xth, xt); \ - get_cpu_vsrl(xtl, xt); \ gen_set_access_type(ctx, ACCESS_INT); \ EA =3D tcg_temp_new(); \ if (indexed) { \ @@ -281,10 +279,61 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i64(xtl); \ } =20 -VSX_VECTOR_LOAD_STORE(lxv, ld_i64, 0) -VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0) -VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1) -VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1) +VSX_VECTOR_LOAD(lxv, ld_i64, 0) +VSX_VECTOR_LOAD(lxvx, ld_i64, 1) + +#define VSX_VECTOR_STORE(name, op, indexed) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + int xt; \ + TCGv EA; \ + TCGv_i64 xth; \ + TCGv_i64 xtl; \ + \ + if (indexed) { \ + xt =3D xT(ctx->opcode); \ + } else { \ + xt =3D DQxT(ctx->opcode); \ + } \ + \ + if (xt < 32) { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + } else { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + } \ + xth =3D tcg_temp_new_i64(); \ + xtl =3D tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, xt); \ + get_cpu_vsrl(xtl, xt); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA =3D tcg_temp_new(); \ + if (indexed) { \ + gen_addr_reg_index(ctx, EA); \ + } else { \ + gen_addr_imm_index(ctx, EA, 0x0F); \ + } \ + if (ctx->le_mode) { \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ + } else { \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ + } \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ + tcg_temp_free_i64(xtl); \ +} + +VSX_VECTOR_STORE(stxv, st_i64, 0) +VSX_VECTOR_STORE(stxvx, st_i64, 1) =20 #ifdef TARGET_PPC64 #define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ @@ -329,7 +378,6 @@ static void gen_##name(DisasContext *ctx) = \ return; \ } \ xth =3D tcg_temp_new_i64(); \ - get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ gen_set_access_type(ctx, ACCESS_INT); \ EA =3D tcg_temp_new(); \ gen_addr_imm_index(ctx, EA, 0x03); \ @@ -513,8 +561,8 @@ static void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i64(xth); \ } =20 -VSX_LOAD_SCALAR_DS(stxsd, st64_i64) -VSX_LOAD_SCALAR_DS(stxssp, st32fs) +VSX_STORE_SCALAR_DS(stxsd, st64_i64) +VSX_STORE_SCALAR_DS(stxssp, st32fs) =20 static void gen_mfvsrwz(DisasContext *ctx) { --=20 2.21.0