From nobody Thu May 2 10:59:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1558686189; cv=none; d=zoho.com; s=zohoarc; b=TFZDAEI9pVbq5X9ifheslfiM31WfK1nYO0bNejf2CcZTCio/h19rceZj7MzaBYEbCdRFopNaZ1Nl4j7+O8/KW6cZdlA4a/qIiwvblDn1fUIGjXDOcOa+knU/1txzpbENa8wROkVkYO933mJV+02XLeJDEJYmckZr2cTzD1e4pDk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558686189; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FOeqUB0MSl5GW1Zg+VVqh02IapqNtaagHIiH1q3Qdo0=; b=StXhVi9fcmVxu3wcns89EPLGS98J0l5tL3tmqq6c2sb5pxQJ4t6/qBZ9TeMJH1GON4gCBsT2qZwxg3CRJM8eQVCgS1/dG8eBLsxIoQsquP36kyzKatP9JtP4nq0KiixmPwygbeNj9qJRaBZSmdEMDzxPlm2q0k8opfBeZCKnbtM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558686189922620.0195685614741; Fri, 24 May 2019 01:23:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:50910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU5Td-0004LZ-Pt for importer@patchew.org; Fri, 24 May 2019 04:22:57 -0400 Received: from eggs.gnu.org ([209.51.188.92]:37287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU5Rw-0003Oc-HA for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hU5Rv-00014k-3a for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:12 -0400 Received: from mga02.intel.com ([134.134.136.20]:29952) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hU5Ru-0000Yo-QA for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:11 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 May 2019 01:21:04 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.104]) by fmsmga007.fm.intel.com with ESMTP; 24 May 2019 01:21:02 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 From: Tao Xu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Fri, 24 May 2019 16:18:38 +0800 Message-Id: <20190524081839.6228-2-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190524081839.6228-1-tao3.xu@intel.com> References: <20190524081839.6228-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 1/2] x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cohuck@redhat.com, kvm@vger.kernel.org, mst@redhat.com, jingqi.liu@intel.com, tao3.xu@intel.com, mtosatti@redhat.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions. Availability of the user wait instructions is indicated by the presence of the CPUID feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. The patch enable the umonitor, umwait and tpause features in KVM. Because umwait and tpause can put a (psysical) CPU into a power saving state, by default we dont't expose it in kvm and provide a capability to enable it. Use kvm capability to enable UMONITOR, UMWAIT and TPAUSE when QEMU use "-overcommit cpu-pm=3Don, a VM can use UMONITOR, UMWAIT and TPAUSE instructions. If the instruction causes a delay, the amount of time delayed is called here the physical delay. The physical delay is first computed by determining the virtual delay (the time to delay relative to the VM=E2=80=99s timestamp counter). Otherwise, UMONITOR, UMWAIT and TPAUSE= cause an invalid-opcode exception(#UD). The release document ref below link: https://software.intel.com/sites/default/files/\ managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Co-developed-by: Jingqi Liu Signed-off-by: Jingqi Liu Signed-off-by: Tao Xu --- linux-headers/linux/kvm.h | 1 + target/i386/cpu.c | 3 ++- target/i386/cpu.h | 1 + target/i386/kvm.c | 13 +++++++++++++ 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index c8423e760c..86cc2dbdd0 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -993,6 +993,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_ARM_SVE 170 #define KVM_CAP_ARM_PTRAUTH_ADDRESS 171 #define KVM_CAP_ARM_PTRAUTH_GENERIC 172 +#define KVM_CAP_ENABLE_USR_WAIT_PAUSE 173 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2df56fa977..c2ad7866a5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1057,7 +1057,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, NULL, "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -5196,6 +5196,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, &cpu->mwait.ecx, &cpu->mwait.edx); env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; + env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; } } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fce6660bac..66fa61f02b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -679,6 +679,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) +#define CPUID_7_0_ECX_WAITPKG (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instruc= tions */ #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ #define CPUID_7_0_ECX_GFNI (1U << 8) #define CPUID_7_0_ECX_VAES (1U << 9) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 3b29ce5c0d..b58fc7ab3a 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -389,6 +389,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, if (host_tsx_blacklisted()) { ret &=3D ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); } + } else if (function =3D=3D 7 && index =3D=3D 0 && reg =3D=3D R_ECX) { + if (enable_cpu_pm) { + ret |=3D CPUID_7_0_ECX_WAITPKG; + } } else if (function =3D=3D 7 && index =3D=3D 0 && reg =3D=3D R_EDX) { /* * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM h= osts. @@ -1654,6 +1658,15 @@ int kvm_arch_init(MachineState *ms, KVMState *s) error_report("kvm: guest stopping CPU not supported: %s", strerror(-ret)); } + + if (kvm_check_extension(s, KVM_CAP_ENABLE_USR_WAIT_PAUSE)) { + ret =3D kvm_vm_enable_cap(s, KVM_CAP_ENABLE_USR_WAIT_PAUSE, 0); + if (ret < 0) { + error_report("kvm: guest can't enable user-level" + " wait and pause: %s", + strerror(-ret)); + } + } } =20 return 0; --=20 2.20.1 From nobody Thu May 2 10:59:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558686189660839.2049609075673; Fri, 24 May 2019 01:23:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:50912 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU5Tf-0004MT-3B for importer@patchew.org; Fri, 24 May 2019 04:22:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:37300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU5Rx-0003Oj-GU for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hU5Rw-000163-DM for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:13 -0400 Received: from mga02.intel.com ([134.134.136.20]:29956) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hU5Rw-0000nK-3A for qemu-devel@nongnu.org; Fri, 24 May 2019 04:21:12 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 May 2019 01:21:06 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.104]) by fmsmga007.fm.intel.com with ESMTP; 24 May 2019 01:21:04 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 From: Tao Xu To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Date: Fri, 24 May 2019 16:18:39 +0800 Message-Id: <20190524081839.6228-3-tao3.xu@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190524081839.6228-1-tao3.xu@intel.com> References: <20190524081839.6228-1-tao3.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 2/2] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cohuck@redhat.com, kvm@vger.kernel.org, mst@redhat.com, jingqi.liu@intel.com, tao3.xu@intel.com, mtosatti@redhat.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-developed-by: Jingqi Liu Signed-off-by: Jingqi Liu Signed-off-by: Tao Xu --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 15 +++++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 66fa61f02b..9d1c8edc1f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -459,6 +459,7 @@ typedef enum X86Seg { =20 #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 +#define MSR_IA32_UMWAIT_CONTROL 0xe1 =20 #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 @@ -1360,6 +1361,7 @@ typedef struct CPUX86State { uint16_t fpregs_format_vmstate; =20 uint64_t xss; + uint64_t umwait; =20 TPRAccess tpr_access_type; } CPUX86State; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index b58fc7ab3a..7845f684fc 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -92,6 +92,7 @@ static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_hv_reenlightenment; static bool has_msr_xss; +static bool has_msr_umwait; static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; @@ -1487,6 +1488,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_XSS: has_msr_xss =3D true; break; + case MSR_IA32_UMWAIT_CONTROL: + has_msr_umwait =3D true; + break; case HV_X64_MSR_CRASH_CTL: has_msr_hv_crash =3D true; break; @@ -1667,6 +1671,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) strerror(-ret)); } } + } else { + has_msr_umwait =3D false; } =20 return 0; @@ -2033,6 +2039,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); } @@ -2426,6 +2435,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_umwait) { + kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); + } if (has_msr_spec_ctrl) { kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); } @@ -2675,6 +2687,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_XSS: env->xss =3D msrs[i].data; break; + case MSR_IA32_UMWAIT_CONTROL: + env->umwait =3D msrs[i].data; + break; default: if (msrs[i].index >=3D MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target/i386/machine.c b/target/i386/machine.c index 225b5d433b..e51285a583 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -810,6 +810,25 @@ static const VMStateDescription vmstate_xss =3D { } }; =20 +static bool umwait_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->umwait !=3D 0; +} + +static const VMStateDescription vmstate_umwait =3D { + .name =3D "cpu/umwait", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D umwait_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.umwait, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1079,6 +1098,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_hyperv_reenlightenment, &vmstate_avx512, &vmstate_xss, + &vmstate_umwait, &vmstate_tsc_khz, &vmstate_msr_smi_count, #ifdef TARGET_X86_64 --=20 2.20.1