From nobody Tue Apr 30 05:52:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558681114; cv=none; d=zoho.com; s=zohoarc; b=KEMvE4T2+PykbYdd4NSI94xbxxrG2jUq9vLMSq3iwmgSgVCYlzbhPuOJn1Ua0J17Zz96IbIuqi1AhyHUKuG7xCPbH/uiNa+jMYGcbAAQwRaefTsJhyu6FQUr7TZaipVJYX74HEjeVNWpmr9fQLwUtUTMJVxtJkfWrmLc03H7Owk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558681114; h=Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=dQ/o9C2VkzVdXpw+z4i7pzxxh8200sN66+uIKrHNGaU=; b=EUoBErr7k1rHWAXgZEtp+Geq9BhxzZLsDHbD9Z9DWf5/OFp7c/EkkDtrnaf5wsxsrT9htw2hrP+ayGgbaOtlWzBuDUs0zVoCDdIax57DGGy+hFha/EdA13a44iqT/STGoNYvPWGVgCPktMjxDf+Jo2SpW0TTaTCfWfd4/CvP/TE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558681113964882.5641105844489; Thu, 23 May 2019 23:58:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:50004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU49s-0002ED-1R for importer@patchew.org; Fri, 24 May 2019 02:58:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hU48Y-0001Tl-Rq for qemu-devel@nongnu.org; Fri, 24 May 2019 02:57:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hU48X-0002mW-OS for qemu-devel@nongnu.org; Fri, 24 May 2019 02:57:06 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:38058 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hU48X-0002Iw-IS; Fri, 24 May 2019 02:57:05 -0400 Received: from host86-185-106-199.range86-185.btcentralplus.com ([86.185.106.199] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hU44b-0002tc-2P; Fri, 24 May 2019 07:53:02 +0100 From: Mark Cave-Ayland To: david@gibson.dropbear.id.au, qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Fri, 24 May 2019 07:53:45 +0100 Message-Id: <20190524065345.25591-1-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 X-SA-Exim-Connect-IP: 86.185.106.199 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH v2] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Anton Blanchard During the conversion these instructions were incorrectly treated as stores. We need to use set_cpu_vsr* and not get_cpu_vsr*. Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() h= elpers for VSR register access") Signed-off-by: Anton Blanchard Reviewed-by: Mark Cave-Ayland Tested-by: Greg Kurz Reviewed-by: Greg Kurz --- target/ppc/translate/vsx-impl.inc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 199d22da97..cdb44b8b70 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); + gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); =20 @@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); =20 EA =3D tcg_temp_new(); @@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx) if (ctx->le_mode) { gen_bswap16x8(xth, xtl, xth, xtl); } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx) } xth =3D tcg_temp_new_i64(); xtl =3D tcg_temp_new_i64(); - get_cpu_vsrh(xth, xT(ctx->opcode)); - get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free(EA); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); --=20 2.11.0