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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 23 May 2019 15:23:53 +0100
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Subject: [Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to
ICC_CTLR_EL3
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The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 000bdbd6247..3b212d91c8f 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1856,7 +1856,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
=20
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
- cs->icc_ctlr_el1[GICV3_NS] &=3D (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIM=
ODE);
+ cs->icc_ctlr_el1[GICV3_NS] &=3D ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOI=
MODE);
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
cs->icc_ctlr_el1[GICV3_NS] |=3D ICC_CTLR_EL1_EOIMODE;
}
@@ -1864,7 +1864,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
cs->icc_ctlr_el1[GICV3_NS] |=3D ICC_CTLR_EL1_CBPR;
}
=20
- cs->icc_ctlr_el1[GICV3_S] &=3D (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMO=
DE);
+ cs->icc_ctlr_el1[GICV3_S] &=3D ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIM=
ODE);
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
cs->icc_ctlr_el1[GICV3_S] |=3D ICC_CTLR_EL1_EOIMODE;
}
--=20
2.20.1